High-speed Frequency Synthesizer Research Articles

Low Voltage and High Speed Dual-Modulus Prescaler with E-TSPC Technology for Frequency Synthesizer

In this paper, a new extended true-single-phase-clock (E-TSPC) based divide-by-2/3 prescaler is proposed for low supply voltage and low power consumption applications. By using pass transistor logic and changing the logic gates, the critical path between the E-TSPC flip-flops has been reduced. Prescaler is designed by Cadence in chartered 0.18 µm CMOS process. Simulation results show that proposed dual-modulus prescaler can work up to 3.9 GHz under 0.9 V supply voltage with 226 µW power consumption and it is suitable for low power and high speed frequency synthesizer in wireless communication system.

DDS를 이용한 광대역 고속 주파수 합성기

Abstract In this paper, a 613 GHz ultra high speed frequency synthesizer having minimum 30 kHz step size and minimum 500 ns frequency settling time is proposed. In order to obtain fast settling time, fine resolution, and good phase noise performance, wideband output frequencies were synthesized based on DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology. The phase noise performance of wideband frequency synthesizer was estimated by the superposition theory and its results were compared with mea-sured ones. The measured frequency settling time was below 500 ns, phase noise was below 106 dBc @ 10 kHz at 13 GHz, and frequency accuracy was measured below ±2 kHz. Key words: Wideband Synthesizer, High Speed, Fine Resolution, DDS OPQRS(Agency for Defense Development) *TU QGVWQ(Department of Radio Science & Engineering, Chungnam National University)Manuscript received August 29, 2014 ; Revised September 29, 2014 ; Accepted November 7, 2014. (ID No. 20140829-066)Corresponding Author: Dong-Chul Park (e-mail: dcpark@cnu.ac.kr)

이중 PLL 구조 주파수 합성기의 위상 잡음 개선

Abstract This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of 1 st PLL used as reference frequency of 2 nd PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5A8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about 3 dBm, the maximum lock-in time and phase noise are within 60 us and 95 dBc/Hz at 10 kHz offset, respectively.Key words: Frequency Synthesizer, Dual PLL, Phase Noise, Fractional Spur QRSTE%U(Agency for Defense Development)Manuscript received July 21, 2014 ; Revised September 5, 2014 ; Accepted September 12, 2014. (ID No. 20140721-11S)Corresponding Author: Jung-Hoon Kim(e-mail: jhkim1@add.re.kr) V. 서 론 WXY!Z [O ], Y!^_`, abcdefg9hi j 3klm, 9no#_ Npq mHr s*2tudvwN3klm-. Y!Z udv'( )* LO(Local Oscillator) 1wx23y0z{|}#-. '( )*)*R~€‚ #9ƒ„'( )*(DS: Direct Synthe-sis), „)*R~(PLL), ƒ„BCD)*R~(DDS: Direct Digital Synthesis) eG†‡ˆlm

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.

Dual-Modulus Prescaler Based on Transmission Gates and Pseudo-PMOS Logic

The Dual Modulus Prescaler is a critical block in CMOS systems like high speed frequency synthesizers. The design of high divide-by-value, high speed and low power dual modulus prescaler, however, remains a design challenge. In order to face the challenge, this paper introduces an idea of using transmission gates and pseudo-PMOS logic in realization of the dual modulus prescaler. The topology of the prescaler proposed in this paper is different from the prior designs primarily in two ways: (i) it uses transmission gates in the critical path and (ii) the D-flip flops used in the synchronous counter are comprised of pseudo-PMOS invertors and ratioed latches. A design of the pseudo-PMOS logic based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35 ? m CMOS technology. Its maximum operating frequency is observed as 2.4 GHz. It consumes 4.8 mW power from a 3 V supply. Circuit operations and measurement results are provided. The silicon estate required is only 0.06 mm2. There is no flip flop and logic gate in the critical path. The proposed topology is suitable firstly for the high speed and high divide-by-value prescaler designs. Secondly, it reduces: (i) design complexity, (ii) power consumption and (iii) load to preceding circuit.

Implementation of a high speed frequency synthesizer employing a dual input phase accumulator

We present a new PLL based frequency synthesizer, in which we have replaced the conventional phase frequency detector and the dividers (programmable counters) with a sequential dual input phase accumulator (DIPA), consisting of a digital circuit employing adders, registers and a ladder. The main feature of the DIPA is that the two input frequencies are not required to be normalized (divided down) to the step frequency of the synthesizer. Instead, the two different high frequencies, that is the reference and the output frequency of the synthesizer, are applied directly. The DIPA samples and normalizes their phases at very high rates, calculates their phase difference, producing an output that consists of a dc component proportional to the phase difference and harmonics of the two input high frequencies. These harmonics are high frequencies and can easily be rejected by a wide bandwidth filter of the loop, without affecting the high convergence speed of the loop. Moreover, these harmonics do not generate spurs near the output frequency. The resolution of the DIPA based synthesizer depends only on the length of the digital word of the DIPA, and its convergence speed depends on the lower of the two input frequencies. The output of the DIPA is a linear function of the phase difference of the two input frequencies and its dynamic range exceeds the limit of ±2π that governs the conventional phase detectors. Thus, the proposed frequency synthesizer based on the DIPA has low phase noise, no spurs nearby the output frequency, high resolution and fast convergence rate. Additionally, the output frequency can be digitally modulated under the control of the closed loop, either by phase or frequency modulation.