High-speed lossless networks widely adopt hybrid retransmission architecture at the link and physical layers to enhance the reliability of data transmission. However, the integration of Forward Error Correction (FEC) coding techniques introduces substantial latency, and existing configurable bypass error correction approaches struggle to adapt to the channel Bit Error Rate (BER) variability and granularity variations of transaction layer packets and FEC blocks. To address these challenges, this paper proposes a novel hybrid retransmission architecture, HARQ-apt, which optimizes data processing at the receiver side through a dual-path approach. Specifically, data is replicated into two paths after physical layer channel locking and reordering: one undergoes complete FEC decoding before entering the link layer, while the other bypasses FEC decoding entirely. The link layer identifies received packets using CRC and sequence numbers and employs the Go-Back-N mechanism to ensure reliable transmission of uncorrectable packets. The HARQ-apt architecture is implemented using RS(528,514) and RS(272,257) FEC coding for a 200Gbps high-speed lossless network design. Experimental results demonstrate that HARQ-apt achieves superior latency performance. ASIC (Application-Specific Integrated Circuit) synthesis using the FreePDK 45nm process shows that HARQ-apt incurs only marginal increases in hardware resources compared to traditional HARQ, with just 2.51% area overhead and 2.58% power overhead. Furthermore, FPGA (Field-Programmable Gate Array) prototype validation demonstrates its feasibility and effectiveness. These results highlight HARQ-apt as an efficient solution for high-speed data transmission, representing significant progress in addressing the challenges of FEC in high-speed networks, providing a practical approach for reliable, low-latency data transmission.

High-Speed Column Level ADC Design of Full Parallel Two-Step Nested TDC for CMOS Image Sensor

This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs) in radiation-prone environments. By leveraging extended Hamming coding and dynamic circuits, the design achieves a 29.1% RW speed improvement, reduces SEU cross-section by one order of magnitude, and incurs a 29.8% area overhead and a 95.2% dynamic power increase of the ECC module, leading to an overall chip area increase of ~14.2% compared to static logic-based RH SEC-DED SRAM. Radiation experiments validate superior tolerance across a LET range of 1.63-21.8 MeV·cm2/mg, demonstrating nearly doubled SEU resilience compared to conventional SEC-DED-based designs. This work balances error correction capabilities with system efficiency, making it suitable for high-reliability applications in space electronics and advanced processors.

Accurate characterisation of the static and cyclic behaviour of coarse-grained railway base materials is essential for high-speed rail design and maintenance. Laboratory triaxial testing is often constrained by apparatus size, necessitating particle size scaling to satisfy the one-sixth maximum particle size criterion. This study evaluates the influence of two standard scaling techniques—scalping and parallel gradation—on the mechanical response of gravel–sand mixtures used in slab track-bed foundations. Consolidated drained static and cyclic triaxial tests were performed on specimens with prototype and scaled gradations under confining pressures ranging from 50 to 200 kPa. Complementary three-dimensional Discrete Element Method (DEM) simulations, incorporating non-spherical particle shapes and flexible boundaries, were calibrated against laboratory data to investigate macro- and micro-mechanical behaviours across loading frequencies of 0.1–7 Hz. Results show that scaling alters peak and residual strengths, volumetric behaviour, shear modulus, damping ratio, and micromechanical fabric, leading to deviations from the prototype responses. Coarser gradations exhibited higher contact forces, greater deformation, and more substantial frequency-dependent stiffness changes, while scaled specimens retained stiffness and exhibited higher damping at service strains. Predictive relationships for shear modulus and damping ratio as functions of shear strain, confinement, and dimensionless train speed were derived, highlighting the need for gradation-specific calibration. The findings demonstrate that scaled laboratory results should be applied to prototype predictions with caution, and that appropriate correction factors and safety margins are required essential to avoid bias in the design and performance assessments of high-speed railway infrastructure. • Particle size scaling alters the static and cyclic response of coarse soils. • DEM simulations calibrated with triaxial tests capture scaling effects. • Scaling modifies shear modulus and damping ratio under cyclic loading. • Prototype gradation shows greater modulus degradation than scaled soils. • Predictive shear modulus and damping ratio relationships proposed for design of high-speed rail beds.

We develop a convolutional regularized least squares (CRLS) framework for reduced-order modeling of transonic flows with shocks. Conventional proper orthogonal decomposition (POD)-based reduced models are attractive because of their optimality and low online cost; however, they perform poorly when snapshots contain parameter-dependent discontinuities, leading to smeared shocks, stair-stepping, or nonphysical oscillations. In CRLS, we first map each full-order snapshot to a smoother representation by applying a one-dimensional Gaussian convolution with reflect padding along the flow field coordinates. The convolution hyperparameters (kernel width and support) are selected automatically by Bayesian optimization on a held out set of snapshots. POD bases are then extracted from the smoothed data, and the parametric dependence of the POD coefficients is learned via radial basis function interpolation. To recover sharp shock structures, we introduce an efficient deconvolution step formulated as a regularized least squares problem, where the regularization centers the reconstruction around a nearest-neighbor reference snapshot in parameter space. The resulting CRLS surrogate is evaluated on inviscid transonic flow over a transonic airfoil, modeled by the steady compressible Euler equations solved with the Stanford University unstructured code over a Latin hypercube sample of Mach number and angle of attack. Compared with standard POD and smoothed POD baselines, CRLS yields markedly improved shock location and strength, lower surface-pressure and field-level errors, and a 42% reduction in the number of POD modes required to capture a fixed fraction of snapshot energy. These results demonstrate that CRLS provides an accurate, data-efficient, and largely automated route to shock-aware reduced-order models for the high-speed aerodynamic design.

Abstract A novel monolithic 3D ternary complementary metal-oxide-semiconductor (M3D T-CMOS) inverter is proposed and evaluated for the better operating speed and integration density. It features a monolithically stacked structure with a MOS field-effect transistor (MOSFET) and a balance control transistor (BCT) for the high/low and the intermediate states, respectively. The BCT is composed of junctionless FET which can precisely control the drain current of n- and p-type devices. A contact-in-contact process is adopted for the vertical connections between the MOSFET and BCT, which precisely controls the contact resistance and ensures balanced current distribution between the devices. Therefore, the M3D T-CMOS devices are advantageous to match the current-levels of the both devices between each other. The technology computer-aided design simulation results show that the M3D T-CMOS inverter can achieve a 141 mV static noise margin, indicating stable operation as the ternary logic device. In addition, the ternary states are clearly distinguished even at 10 MHz operating speed.

• Core Innovation & Objective • Developed a novel, integrated system architecture combining a modified USRP X310 software-defined radio platform with a custom-designed high-power LED optical transceiver. • Achieved high-speed, low-latency, and highly reliable audio-video transmission over Visible Light Communication (VLC) for intelligent transportation and vehicle-to-vehicle (V2V) applications, particularly in electromagnetically sensitive environments. • Key Technical Breakthroughs • LED Bandwidth Extension: Designed an innovative active pre-equalization circuit (based on a 4th-order high-pass RC bypass and op-amps) that dramatically increased the 3dB modulation bandwidth of a commercial 15W LED from 3 MHz to 120 MHz. • High-Speed Modulation: Successfully implemented 64QAM-OFDM modulation/demodulation using GNU Radio on the USRP, enabling spectrally efficient data transmission. • Advanced Optical Design: Custom-designed optical lenses (transmitter and receiver) and a high-power Bias-T circuit for efficient AC/DC coupling, ensuring the LED operates in its linear region and maximizing optical power transfer. • Stable Link Performance: Incorporated an Automatic Gain Control (AGC) circuit at the receiver, stabilizing the output voltage between 1.2V - 2.0V and maintaining a modulation signal-to-noise ratio (SNR) > 23 dB over varying distances. • Outstanding System Performance • The experimentally demonstrated performance metrics are exceptional for a VLC system: • Peak Data Rate: 500 Mbps • Communication Distance: 0 - 110 meters • Bit Error Rate (BER): As low as 1.74 × 10⁻⁵ (far below the 1 × 10⁻⁴ target) • End-to-End Latency: < 0.1 s • Beam Angle: 11.5° (Transmitter) • Field of View (FOV): ≤ 18° (Receiver) • System Integration and Design • Hardware-Software Co-Design: Seamless integration of the USRP X310 (handling digital baseband processing) with the custom analog optical front-end. • Compact and Practical: The system is designed for external mounting on vehicles, offering a practical solution for real-world deployment. • Simulation-Guided Design: Used LightTools for optical design and Optisystem for communication link simulation to validate the design before implementation. • Significance and Application Value • Solves Critical Challenges: Provides a high-speed, secure, and EMI-free communication alternative to traditional RF in environments like military operations, petroleum facilities, and intelligent transportation systems. • 6G Potential: Serves as a practical reference for the development of VLC as a complementary technology in 6G networks. • Demonstrates Feasibility: Successfully proves the viability of using commercial LEDs and USRP platforms for building high-performance, medium-to-long-range optical communication systems. • This work represents a significant step forward in practical high-speed VLC system design, combining theoretical innovation with robust engineering to achieve state-of-the-art performance. Existing vehicular VLC systems suffer from limited bandwidth, short transmission distances, low data rates, and support only a narrow range of communication services. To address these issues, this paper proposes a vehicle-mounted high-speed LED visible light communication (VLC) system based on Universal Software Radio Peripheral (USRP). Leveraging 64QAM-OFDM digital modulation, an improved USRP X310 hardware platform, and a PC, we establish a novel architecture comprising digital baseband and optical transceiver modules. The baseband module eliminates traditional spectrum-shifting circuits and antennas, retaining only FPGA and ADC/DAC units. Audio/video files undergo 64QAM-OFDM modulation directly on the PC, with modulated signals output via DAC to a custom-designed wide-bandwidth LED transceiver. A broadband hardware equalization network based on a fourth-order RC bypass circuit was designed expands the 3dB bandwidth of high-power LEDs from 3 MHz to 120 MHz. Combined with automatic gain control (AGC), this achieves an optical transceiver with 12–15 W output power, >23 dB optical modulation signal-to-noise ratio (SNR), and stable receiver output voltage (1.2–2.0 V). The resulting compact system delivers low latency, high data rates, and high reliability. Under aligned optical path conditions, the system achieves >1 Mbit/s at 110 m (BER 0.49 × 10⁻⁵, delay 0.009-0.05s) and a peak rate of 500 Mbit/s at 10 m (BER 7.4 × 10⁻⁵), with an 11.5° transmit angle and a receiver field of view (FOV) of less than 18°. This work demonstrates the feasibility of high-power LED-based 64QAM-OFDM communication using USRP X310 for medium- to long-range vehicular links, providing a reference for intelligent transportation systems.

In high-speed ship design, accurate hydrodynamic prediction is crucial to optimizing performance and efficiency. One of the strategies is to take advantage of interceptors, which have proven to be a promising solution for resistance reduction and trim control. However, most studies focus on vessels with undisturbed stern geometries. In contrast, certain high-speed vessels, such as patrol craft or military fast boats, are equipped with tunnel propeller configurations designed to protect the propeller while ensuring optimal performance at high Froude numbers. This study investigates interceptors on hulls fitted with tunnel propellers through experimental and numerical approaches. Interceptors of various span dimensions are strategically installed on the tunnel propellers, with consistent blade height. The computational fluid dynamics approach was used to investigate the hydrodynamic characteristics of the hull, providing a comprehensive analysis of total resistance, pressure distribution, wave elevation, and dynamic trim. This study shows that interceptors can still perform effectively, even on hulls equipped with tunnel propellers. Furthermore, vessel speed and configuration play a significant role in interceptor effectiveness. The mid-tunnel interceptor configuration produced the greatest reduction in resistance, up to 9.7% at Fr=0.85.

In this letter, a high-speed Reed–Solomon erasure code (RS-EC) decoder circuit is proposed for accelerating the data reconstruction in storage. By utilizing a check matrix instead of a regular Cauchy matrix for encoding the original data, the size of the matrix for decoding the damaged data can be reduced significantly. Moreover, in order to accelerate the matrix inversion related to the RS-EC decoder, the large matrix is partitioned into several small matrices and these small matrices execute the inversion operations individually. Subsequently, an equation method instead of the Gaussian elimination method is proposed for further speeding up the inversions of the small matrices. Eventually, a novel algorithm is proposed for reducing the overall data stream of the RS-EC decoder. The results show that the proposed RS (14, 10) decoder is able to achieve a 6,800 MBps throughput, under the synthesis of TSMC 130 nm process design kits (PDK). The corresponding data stream of the decoder is reduced to 55% if only one data block is required to reconstruct.

High speed arithmetic units are fundamental components in modern VLSI systems, directly affecting the performance, area, and efficiency of processors, digital signal processing units, and embedded hardware.In many applications, the addition of more than two operands is frequently required, and implementing such operations using conventional two operand adders leads to increased delay and hardware overhead.This work presents the design of a high speed three operand binary adder using an area efficient VLSI architecture.The proposed design performs the addition of three binary inputs within a single computation framework, thereby reducing the critical path delay and minimizing redundant logic.An optimized carry generation and propagation strategy is employed to enhance speed while maintaining low area complexity.The architecture is described using hardware description language and validated through functional simulation and synthesis.Performance evaluation demonstrates that the proposed three-operand adder achieves improved speed and efficient area utilization compared to traditional adder based approaches, making it suitable for high performance and resource constrained VLSI applications.

Abstract High-temperature superconducting (HTS) maglev technology shows significant potential for tourist rail transportation due to its self-stabilization, environmental benefits, and low noise. Existing researches on HTS maglev vehicles focuses more on high-speed design, while as sightseeing vehicles, they will face more complex routes, especially smaller curve radius, which puts higher demands on the curve passing performance. Therefore, additional analysis should be conducted on the working conditions during small-radius curve negotiation. As one of the main components of maglev vehicles, the rationality of the structural design of the levitation bogie is the key to the safety and stability of the vehicle, and it also directly affects the vehicle’s curve passing performance. This paper first conducted a geometric analysis of the lateral displacement of the levitation bogie when passing through the curve, and designed a radial mechanism (RM). Then, a prototype of the HTS maglev bogie experiment considering the RM was constructed, and the vibration response of the levitation bogie under different conditions was tested using the HTS ring test line platform. Finally, a dynamic model of the HTS maglev sightseeing vehicle with the RM was established, and the curve passing performance and dynamic response were analyzed. The results confirm that under the action of RMs, the lateral displacement of HTS levitators is significantly reduced, which can effectively improve the curve passing performance of HTS maglev system, providing theoretical basis and reference suggestions for the engineering application of HTS maglev bogie in small curve radius passing scenarios.

The rising need for high-performance and energy-efficient VLSI systems has highlighted the limitations of CMOS technology at nanoscale dimensions, particularly because of the increased leakage current, short-channel effects, and reduced power efficiency. Carbon Nanotube Field-Effect Transistors (CNTFETs) offer a promising alternative because of their near-ballistic transport, high carrier mobility, and strong electrostatic control. The research work evaluates logic gates, adders, encoders, decoders, multiplexers, and flip-flops implemented using the Stanford 32 nm CNTFET model in Cadence Virtuoso. CMOS baselines at 90 nm were used to provide relative technology-behavior insights. Detailed transient, DC, and AC simulations were conducted to extract delay, power, and PDP. Based on the simulation results, CNTFET implementations with respect to conventional CMOS technology demonstrated power reductions ranging from approximately 45% to 69% and delay improvements between 21% and 67%, depending on the circuit complexity. These results indicate that CNTFET technology offers significant potential for low-power and high-speed digital designs at advanced technology nodes, making it a strong for memory circuits, and future scalable nano-electronics.

ABSTRACT: High-speed printed circuit board (PCB) design has become increasingly complex due to rising data rates, dense component integration, and stringent signal and power integrity requirements. Traditional PCB design approaches rely heavily on manual expertise and iterative trial-and-error methods, which often lead to prolonged design cycles and suboptimal performance. Recent advances in Artificial Intelligence (AI) and machine learning provide new opportunities to automate and optimize high-speed PCB design processes. This paper presents an AI-assisted framework for high-speed PCB design that integrates machine learning techniques into the conventional design flow to address signal integrity, electromagnetic interference, and routing optimization challenges. The proposed methodology leverages design data and electrical constraints to train intelligent models capable of predicting optimal routing strategies and layout parameters. Experimental evaluation demonstrates that the AI-assisted approach significantly improves signal integrity performance while reducing design iterations and development time when compared with conventional design techniques. The results highlight the potential of AI-driven automation in enhancing PCB design efficiency and reliability, making it a promising solution for next-generation high-speed electronic systems.

Ramjet and scramjet engines are air-breathing power systems that work more efficiently than gas turbine engines at hypersonic speeds. However, their high-speed operation demands specific design strategies to ensure flame stabilization and adequate residence time. In the present study, the effect of the forewall inclination angle of the cavity-based flame holder on combustion characteristics was investigated numerically in 2D geometry using Ansys Fluent. For this purpose, the combustion reactions of a total of 9 different forewall approaches, in which the angle of the forewall with the vertical axis was changed between -40 and 40 degrees at 10-degree intervals, were modeled with a 2.5 Mach inlet speed and 1 Mach hydrogen fuel injected from the cavity bottom. Results show that positive forewall angles are more efficient than neutral or negative inclined forewalls. Nevertheless, they lead to drag penalty compared to lower inclined wall angles. Qualitative evaluations show that a positive cavity with forewall angle enhances vortex in the upstream of fuel injection, hence improves combustion efficiency while sacrificing static parameters such as temperature and drag. Although the global combustion efficiency gain remains slight at 0.69%, positive forewall angles significantly optimize local recirculation and thermal distributions, offering better conditions for reactive flow stability inside the cavity. As a result, a positive inclined forewall is promising to improve combustion; however, temperature and drag rise should also be considered during the design process.

High-speed digital interfaces including USB 3.2, PCIe Gen 4, and HDMI 2.1 operate at data rates exceeding 10 Gbps where PCB material properties significantly impact signal integrity. This research evaluated signal integrity performance of four PCB material categories spanning the cost-performance spectrum: standard FR-4, high-speed FR-4, Megtron 6, and Rogers 4350B. Test vehicles incorporating controlled impedance traces at 6-inch length were characterized using vector network analysis from 100 MHz to 20 GHz and time-domain eye diagram analysis at data rates from 1 Gbps to 12 Gbps. Standard FR-4 exhibited insertion loss of 4.1 dB/inch at 10 GHz with eye height degrading below the 200 mV minimum threshold at 6 Gbps data rate. High-speed FR-4 extended viable operation to 8 Gbps with insertion loss reduced to 3.2 dB/inch. Megtron 6 achieved 2.1 dB/inch insertion loss maintaining adequate eye opening to 10 Gbps. Rogers 4350B demonstrated lowest loss at 1.6 dB/inch with eye height remaining above 400 mV at 12 Gbps. Cost analysis revealed material expense ranging from €15/m² for standard FR-4 to €180/m² for Rogers, representing 12× cost differential. The crossover point where premium materials become cost-effective occurs when re-spin costs from signal integrity failures exceed material price premium, typically at data rates above 5 Gbps for consumer applications. These findings establish quantitative material selection criteria balancing signal integrity requirements against cost constraints for high-speed digital design.

Electrical impedance tomography (EIT) is an advanced visualization modality. In recent years, high-speed devices are commonly employed in EIT systems to accomplish complex tasks and enhance the real-time capability. Signal integrity (SI) and power integrity (PI) are major concerns in the high-speed system design. However, SI/PI issues have received limited attention due to their negligible impact on early developed low-speed EIT systems. The hardware performance degradation introduced by SI/PI issues gradually emerges in the high-frequency range, which may degrade the SNR of the EIT system and aggravate the image distortion caused by the inherent ill-posed problem of the EIT technique. This study comprehensively analyzes the major causes of SI/PI issues in the high-speed EIT systems and proposes the corresponding hardware optimization methods. The proposed methods are applied to a practical EIT system to validate their effectiveness. Experimental results illustrate that the SI/PI issues are effectively mitigated. The average signal-to-noise ratio (SNR) of the EIT system is improved by 5.4dB and the imaging quality is generally enhanced. The methods proposed in this study offer a low-cost, supplementary approach to improve the hardware performance of the high-speed EIT systems.

With the development of the automotive industry towards higher efficiency and lower emissions, electric turbocharged high-speed machines (HSMs) have garnered significant attention due to their potential to enhance power performance and fuel economy. This paper investigates a 5kW, 100,000r/min high-speed permanent magnet synchronous machine (HSPMSM) for electric turbochargers, focusing on its electromagnetic and mechanical performance. Firstly, based on the general air-gap field modulation theory (GAFMT), this study proposes a theoretical analysis method for cogging torque that considers machine slot-pole combinations. It reveals the relationship between magnetic field harmonics generated by modulation behavior and torque ripple, while elucidating the significance of magnetic field modulation in cogging torque generation. The proposed method is validated by comparing the results from finite element analysis (FEA), a preliminary selection of slot-pole combinations with low cogging torque and torque ripple is conducted. Secondly, a systematic and in-depth comparative analysis is conducted on six different slot-pole combinations, covering key performance indices such as no-load back electromotive force (EMF), cogging torque, losses, torque, and torque ripple. Moreover, the rotor's mechanical stress and dynamic performance under ultra-high-speed conditions are also evaluated. The most suitable slot-pole combination for electric turbocharger applications is identified through a comprehensive evaluation of electromagnetic performance, efficiency, and manufacturability. Finally, a prototype machine is manufactured, and experimental validation confirms the accuracy of the proposed analysis and modeling methods.

Approximately 25% of all electricity worldwide is consumed by pumps, compressors, and blowers in industrial applications. High-speed electric machines based on magnetic suspension technology present a significant opportunity to improve the efficiency of these drivelines, thus reducing total energy consumption, costs, and pollution levels. However, a major challenge in adopting the high-speed drivelines in industrial applications lies in their implementation. The design lead time for such machines typically spans years, whereas an ideal time-frame would be mere weeks. This study presents a systematic multidisciplinary design process for thrust active magnetic bearing to accelerate design work. By structuring the design steps in a precise order, automation can be integrated to develop the design space, which can then be directly utilized in the system level design analysis. In practice, when another design area is modified, a thrust bearing design that fulfils the overall design requirements can be automatically updated from the design space. Consequently, non-viable solutions are directly excluded, reducing the iterative nature of high-speed machine system design. Part I of this paper details the methodology of the multidisciplinary design process, while Part II illustrates the application of the proposed design method using a one-megawatt high-speed electric machine for a heat pump compressor.

As data transmission rates escalate across successive generations, the impact of timing jitter on the performance of high-speed systems becomes increasingly significant. Moreover, jitter is exacerbated by frequency-dependent channel characteristics as signals propagate through the interconnects. In this paper, an analytical methodology based on phase noise theory is proposed to accurately quantify the random jitter amplification factor in clock signals. To ensure the high accuracy, the proposed method incorporates the higher-order spectral components of the clock waveform rather than relying on sinusoidal approximations. Extensive simulations and empirical measurements conducted on transmission lines and 5th-generation double data rate (DDR5) channels validate the effectiveness and precision of the proposed approach. This methodology provides essential insights into jitter mitigation strategies pertinent to high-speed channel design.

In this letter, a response-time-improvement method for liquid crystal reflectarrays (LCRAs) is proposed by doping a small amount of chiral molecules with a polar group into nematic liquid crystals (NLCs). The dopant introduces additional intermolecular interactions that accelerate molecular relaxation and thus shorten the decay time, while an overdrive (OD) voltage is applied to mitigate the rise-time increase. LC cells with various chiral-dopant concentrations are characterized, where it is found that the concentration of 0.5 wt% yields the shortest effective decay time. An LCRA prototype using this concentration was fabricated and measured, achieving a significantly reduced decay time, while the rise time is effectively shortened by the OD technique. This work represents the first investigation of chiral-dopant effects on both rise and decay times within a reflectarray configuration, providing guidance for high-speed chiral LCRA design.