High-resistivity Silicon-on-insulator Research Articles

Improvement of linearity in trap-rich substrates for radio frequency applications: Which of donor and acceptor trap is the best?

This paper investigates the effect of volume traps intentionally introduced into a silicon-on-insulator (SOI) substrate by inserting a layer of polysilicon beneath buried oxide. In radio frequency applications, this type of substrate, referred to as trap-rich, is known to considerably reduce the generation of harmonics resulting from the parasitic non-linear charge dynamics introduced by the substrate handler under the buried oxide. This analysis focuses on a test vehicle in the form of an integrated coplanar waveguide on two types of substrates, namely, high-resistivity SOI substrates with and without a trap-rich layer. From a modeling point of view, a simulation methodology is implemented in order to convert the 3D simulation of the coplanar waveguide into a 2D treatment that takes into account the wave propagation effect associated with the distributed nature of the transmission line. As a first step, this modeling strategy is implemented to reproduce the effect of increasing substrate resistivity on 2nd and 3rd harmonic reductions, leading to an excellent agreement with experimental data. Building on this validation of the simulation method, we have opted to simulate the non-linear response of the transmission line on the SOI trap-rich substrate by simplifying the trap distribution model. To avoid the adoption of unverified and strongly process-dependent trap distributions across the bandgap, a midgap monovalent trap density has been introduced, either acceptor or donor density. A monovalent density of acceptor traps with a concentration of 1016 cm−3 and a carrier lifetime of 0.1 ns has been shown to reproduce the experimental data very accurately with a substantial reduction in 2nd and 3rd harmonics. A detailed analysis of the displacement current waveforms explains the beneficial role of acceptor traps compared with donor traps.

Substrate-Induced Dissipative and Non-Linear Effects in RF Switches: Probing Ultimate Performance Based on Laser-Machined Membrane Suspension

With the evolution of radio frequency (RF)/microwave technology, there is a demand for circuits that are able to meet highly challenging RF front end specifications. Silicon-on-insulator (SOI) technology is one of the leading platforms for upcoming wireless generation. The degradation of performance due to substrate coupling is a key problem to address for telecommunication circuits, especially for the high throw count switches in RF front ends. In this context, a fast, flexible and local laser ablation technique of the silicon handler allows for the membrane suspension of large millimeter-scale circuits. This approach enables the evaluation of the ultimate performance in the absence of the substrate, i.e., without dissipative losses and substrate-induced non-linear effects, on capacitive comb coupling structures and RF switches. Compared to high-resistivity SOI substrates, the high frequency characterization of RF membrane switches reveals a superior linearity performance with a reduction in second and third harmonics by 17.7 dB and 7.8 dB, respectively. S-parameter analysis also reveals that membrane suspension entails insertion losses that are improved by 0.38 dB and signal reflection lowered by 4 dB due to a reduced off-state capacitance. With reference to a trap-rich substrate, the membrane suspension also achieves an additional 7.8 dB reduction in the second harmonic, indicating that there is still scope for improvement in this figure of merit. The obtained results demonstrate a new way to evaluate optimized circuit performance using post-fabrication substrate engineering.

Comparative Investigation on Bias Dependent RF Performance of SOI Substrates

In this work, direct current (DC) bias effects on radio frequency (RF) performance of three types of RF silicon-on-insulator (RF-SOI) substrates are comparatively investigated by using coplanar waveguide (CPW) lines. It is demonstrated that the loss and harmonic distortion of CPW line on high resistivity silicon-on-insulator (HR-SOI) substrate are more sensitive to variations of DC bias. This is attributed to the parasitic nonlinear capacitance and conductance in the parasitic surface conduction (PSC) layer. In comparison, the influence of DC bias on the RF performance of trap-rich silicon-on-insulator (TR-SOI) substrate can be negligible due to the trap-rich layer which can get rid of the PSC by trapping free carriers inside the substrate. Bias effects on the RF performance of two types of TR-SOI substrates with different high resistivity substrate are also compared. The results show that the RF characteristics of TR-SOI #2 (TR2) is more independent with respect to the applied bias than that of TR-SOI #1 (TR1). This stems from the smaller parasitic effects and increased effective resistivity.

RF Small- and Large-Signal Characteristics of CPW and TFMS Lines on Trap-Rich HR-SOI Substrates

The main objective of this paper is to evaluate RF losses and nonlinear behavior of coplanar wave- guide (CPW) and thin-film microstrip (TFMS) lines from room temperature up to 175 °C fabricated on two different types of high resistivity (HR) silicon-on-insulator (SOI) substrates. One standard high-resistivity and one trap-rich (TR) substrates, Soitec RFeSI90 product, are used. It is also shown that by using stacked CPW lines on the TR HR-SOI wafer, transmission lines with performances as high as TFMS lines are achievable, with low losses and low-harmonic distortion, while providing much more flexibility in their design. Through measurements, it is shown that the TR HR SOI substrate shows good stability in terms of losses and linearity up to 120 °C.

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Partially depleted SOI MOSFET is now the mainstream technology adopted by all major foundries and fabless companies for the design of several wireless sub-systems. Today, more than 95 percent of substrates used in fabricating cellular and connectivity switches for handsets are SOI (from Navian market analyst, 2016 report) whereas it was not even in production in 2008, GaAs being mainstream at that time. Beside main switch, front-end module complexity has increased drastically: more than ten integrated switches are required in 4G Tier 1 phones, plus antenna tuners as well as Low Noise Amplifiers (LNA). RF-SOI Power Amplifiers (PA) market adoption is slowly ongoing being mainly position on entry market favoring price-performance-integration trade-off. The concept of trap-rich SOI substrate proposed in 2005 is at the origin of the RF-SOI success story. Indeed, substrate losses and crosstalk were the remaining killer features of Si-based technologies for RF applications these last decades. Thanks to the introduction of a high density of defects called traps at the buried oxide (BOX) / Si handle substrate interface, it has been possible to manufacture high-resistivity (HR) SOI substrates characterized with an effective resistivity as high as 10 kΩ.cm. Those traps originate from the grain boundaries in a thin (less than 1 µm-thick) polysilicon layer. This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along coplanar waveguide (CPW) transmission lines and purely capacitive crosstalk similarly to quartz substrate. It has been shown that the presence of a trapping layer does not alter the DC or RF behavior of SOI MOS transistors. And more importantly, it has been demonstrated that harmonics level originated from the substrate is reduced by at least 20 dB moving from standard resistivity SOI substrate (~ 10 Ω.cm) to high resistivity SOI (~ 1 kΩ.cm), and an additional drop of 40 dB is achieved with the innovative trap-rich HR SOI substrate. The low harmonic level achieved is comparable with insulating substrate. The improvement of the HR SOI substrate with the introduction of defects brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors, tunable MEMS (microelectromechanical systems) capacitors, as well as for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc. Université catholique de Louvain and Soitec have been working together to manufacture the trap-rich SOI substrate concept to further improve the high-frequency performance of commercially available HR-SOI substrates. In 2013, Soitec has unveiled a new flavor of HR-SOI called RF-eSITM-SOI, for enhanced Signal IntegrityTM substrate with a measured effective resistivity as high as 10 kΩ.cm. RF-eSI-SOI substrate can really be considered as a lossless Si-based substrate. Beyond switch, RF-eSI-SOI technology opens the path to further system integration in the Front-End Module (FEM) space as well as even more complex mixed signal System-on-Chip. Based on its 45 nm baseline SOI process, GlobalFoundries just released a RF-SOI mmW offering targeting applications like 5G, satellite communication, automotive radar, WiGig, backhaul. The SOI substrates roadmap for RF and millimeter-waves applications will be presented. Future generations of mobile communication systems such as 5G or the Internet-of-Things will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. Their analog/RF behavior will be described and compared in the paper. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances. The relative impact of the transistor characteristics and the substrate properties on different RF ICs performances will be presented. As it will be demonstrated, the use of specific RF test structures at the early stage of a technological node development is of first importance to analyze the transistor parasitic resistances and capacitances, the transistor cutoff frequencies, the self-heating, and the substrate coupling and non-linear behavior.

A SPDT RF Switch Small- and Large-Signal Characteristics on TR-HR SOI Substrates

This paper evaluates the small- and large-signal characteristics of a single pole double thru (SPDT) RF antenna switch including its insertion loss, isolation, and nonlinear behavior. It is fabricated on three different types of high resistivity (HR) silicon-on-insulator (SOI) substrates: one standard (HR-SOI) and two trap-rich (RFeSI80 and RFeSI90). Using a special test structure, the contribution of substrate and active devices is separated for both in small- and large-signal. It is shown that by using trap-rich substrate technology, a reduction of over 16 dB of 2nd harmonic is achieved compared with HR SOI substrate. In off-state, it is shown that 35 dB increase of harmonic level is due to the nonlinearity of active devices. The effect of body bias on small- and large-signal FoMs of the SPDT is investigated and discussed. It is illustrated that trap-rich HR-SOI substrates having much thinner BOX, still outperform classical HR-SOI wafer.

Physical Models of Planar Spiral Inductor Integrated on the High-Resistivity and Trap-Rich Silicon-on-Insulator Substrates

High-resistivity(HR) silicon-on-insulator (SOI) substrates provide low substrate loss, so planar spiral inductors integrated on them presenting higher quality factor ( $Q$ ) than those on traditional Si substrates. However, the parasitic surface conduction (PSC) effect in the SOI substrate constitutes a conductive layer underneath the buried oxide layer, which deteriorates the inductors performance. This effect can be effectively eliminated by introducing a trap-rich layer. In this paper, physical models that can accurately characterize the behavior of inductors integrated on the HR and radio frequency enhanced signal integrity (RFeSI) SOI substrates are presented, and the analysis and evaluation of PSC effect on the performance of inductors, i.e., the inductance, the quality factor, the self-resonant frequency, and the frequency, where $Q$ peaks, are shown. Planar spiral inductors integrated on HR and RFeSI SOI substrates are fabricated and measured, validating the feasibility of the models we use. The experiment results show that the value of $Q$ and the frequency where it peaks can be improved significantly by eliminating the PSC effect. The temperature effects are also explored, showing that the PSC effect gets worse with raising temperature and accelerates the degradation rate of $Q$ .

Radio-Frequency Characteristics of Partial Dielectric Removal HR-SOI and TR-SOI Substrates

High-resistivity silicon-on-insulator (HR-SOI) and trap-rich high-resistivity silicon-on-insulator (TR-SOI) substrates have been widely adopted for high-performance rf integrated circuits. Radio-frequency loss and non-linearity characteristics are measured from coplanar waveguide (CPW) transmission lines fabricated on HR-SOI and TR-SOI substrates. The patterned insulator structure is introduced to reduce loss and non-linearity characteristics. A metal-oxide-semiconductor (MOS) CPW circuit model is established to expound the mechanism of reducing the parasitic surface conductance (PSC) effect by combining the semiconductor characteristic analysis (pseudo-MOS and C–V test). The rf performance of the CPW transmission lines under dc bias supply is also compared. The TR-SOI substrate with the patterned oxide structure sample has the minimum rf loss (<0.2 dB/mm up to 10 GHz), the best non-linearity performance, and reductions of 4 dB and 10 dB are compared with the state-of-the-art TR-SOI sample's, HD2 and HD3, respectively. It shows the potential application for integrating the two schemes to further suppress the PSC effect.

RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

In this work three different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard HR-SOI and two types of trap-rich high resistivity HR-SOI substrates named enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) provided by SOITEC are studied and compared. The DC and RF performances of these wafers are compared by means of passive and active devices such as coplanar waveguide (CPW) lines, crosstalk- and noise injection-structures as well as partially-depleted (PD) SOI MOSFETs. It is demonstrated that by employing enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) compared to HR-SOI wafer, a reduction of 24dB is measured on both generations of trap-rich HR-SOI for 2nd harmonics. Furthermore, it is shown that in eSI HR-SOI, digital substrate noise is effectively reduced compared with HR-SOI. Purely capacitive behavior of eSI HR-SOI is demonstrated by crosstalk structure. Reduction of self-heating effect in the trap-rich HR-SOI with thinner BOX is finally studied.

Design of High-Order Switches for Multimode Applications on a Silicon-on-Insulator Technology

A silicon-on-insulator (SOI) CMOS technology on high-resistivity silicon substrates is presented for the design of high-power switches for cellular and wireless local area network handset applications. A design methodology is introduced to design high-order switches for optimal insertion loss and isolation performance. Sources of nonlinearities in SOI switches are discussed. To the best of our knowledge, this work is the first demonstration of high-power switches on a high-resistivity SOI CMOS technology for high-volume cellular handset applications with adequate intermodulation and harmonic distortion performance. The design details and measurement results for a variety of RF switches with general-purpose input/output and mobile industry processor interface control interfaces, flip-chip/wire-bond packaging, and for various standards are discussed.

Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High ${\rm I}_{\rm ON}/{\rm I}_{\rm OFF}$ Ratio Ge FinFETs

Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high ION/IOFF ratio (~5×105, at VD=0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (VTH) shift can be maintained at the level of ~110 mV/V and ~ 0.1 V, respectively, for Ge n-channel FinFET with Lchannel=120 nm and WFin=40 nm. Multifin Ge FinFET with Lchannel=170 nm and WFin=50 nm is also illustrated. Both N- and P-FinFETs possess high ION/IOFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.

Unusual $C$– $V$ Characteristics of High-Resistivity SOI Wafers

The maximum capacitance for bulk or Silicon on Insulator (SOI) wafers is governed by the gate/contact area. During our capacitance-voltage (C-V) characterization of high-resistivity SOI wafers with Al contacts directly on the Si film, we observed the maximum capacitance to be much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and buried oxide capacitance. In addition, an “S”-shape C-V plot was observed in the accumulation region.

Impact of Crosstalk into High Resistivity Silicon Substrate on the RF Performance of SOI MOSFET

Crosstalk propagation through silicon substrate is a serious limiting factor on the performance of the RF devices and circuits. In this work, substrate crosstalk into high resistivity silicon substrate is experimentally analyzed and the impact on the RF behavior of silicon-on-insulator (SOI) MOS transistors is discussed. The injection of a 10 V peak-to-peak single tone noise signal at a frequency of 3 MHz ( fnoise) generates two sideband tones of −56 dBm separated by fnoise from the RF output signal of a partially depleted SOI MOSFET at 1 GHz and 4.1 dBm. The efficiency of the introduction of a trap-rich polysilicon layer located underneath the buried oxide (BOX) of the high resistivity (HR) SOI wafer in the reduction of the sideband noise tones is demonstrated. An equivalent circuit to model and analyze the generation of these sideband noise tones is proposed.

The properties of high-k gate dielectric films deposited on HRSOI

In this paper, HfO 2 dielectric films with blocking layers (BL) of Al 2O 3 were deposited on high resistivity silicon-on-insulator (HRSOI), and the interfacial and electrical properties are reported. High-resolution transmission electron microscopy (HRTEM) indicated that BL could thin the interfacial layer, keep the interface smooth, and retain HfO 2 amorphous after annealing. Energy dispersive X-ray spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) confirmed that BL weaken Si diffusion and suppressed the further growth of HfSiO. Electrical measurements indicated that there was no hysteresis was observed in capacitance–voltage curves, and Flatband shift and interface state density is 0.05 V and −1.3 × 10 12 cm −2, respectively.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100 V and average leakage current densities at 70 V were only 55 nA/cm 2. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45 × 10 11 cm −2 for a dose of 2.7 Mrad.

Impact of substrate-surface potential on the performance of RF power LDMOSFETs on high-resistivity SOI

This paper presents an in-depth study of the effects of substrate-surface potential on the RF power performance of laterally diffused MOSFETs (LDMOSFETs) fabricated on high-resistivity silicon-on-insulator (HR-SOI). Substrate-surface inversion and accumulation substantially degrade the RF power performance of these devices by providing an RF shunt between source and drain through the substrate surface. The degradation is most prominent under conditions of low gain, high frequency, and high power compression. The potential of HR-SOI for RF applications can only be realized by preventing the appearance of a continuous conducting path at the substrate surface. Under appropriate conditions of substrate-surface depletion, an RF power LDMOSFET on HR-SOI with a peak PAE of 40% at 7.2 GHz is demonstrated

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.

Low Resistivity SOI for Substrate Crosstalk Reduction

Crosstalk in silicon-on-insulator (SOI)-substrates has been investigated using different equivalent circuit models and measurements on crosstalk test structures. The models reveal that a very low resistivity (LR) substrate (LR-SOI) can have significantly lower crosstalk, compared to both high resistivity and medium resistivity substrate. The low crosstalk for the LR-SOI is the result of effective shunting of the signal to ground through the low resistive substrate, which means that an effective substrate ground is crucial. Measurements on the crosstalk test structures also confirmed the results predicted by the models. The measurements show an improvement in the range of 20-40 dB for very low resistivity SOI substrates compared to high resistivity SOI substrates.