High Resistivity Epitaxial Layer Research Articles

Comparison of different sensor thicknesses and substrate materials for the monolithic small collection-electrode technology demonstrator CLICTD

Small collection-electrode monolithic CMOS sensors profit from a high signal-to-noise ratio and a small power consumption, but have a limited active sensor volume due to the fabrication process based on thin high-resistivity epitaxial layers. In this paper, the active sensor depth is investigated in the monolithic small collection-electrode technology demonstrator CLICTD. Charged particle beams are used to study the charge-collection properties and the performance of devices with different thicknesses both for perpendicular and inclined particle incidence. In CMOS sensors with a high-resistivity Czochralski substrate, the depth of the sensitive volume is found to increase by a factor two in comparison with standard epitaxial material and leads to significant improvements in the hit-detection efficiency and the spatial and time resolution.

Low Gain Avalanche Detector development for the LHC’s High-Luminosity upgrade at Teledyne e2v

The need for ultra-fast timing is a result of the expected pile-up at the High-Luminosity LHC General-Purpose Detectors. Track timing resolution of the order of tens of picoseconds is required to sufficiently resolve individual vertices. In collaboration with Teledyne e2v, 22 six-inch wafers with Low Gain Avalanche Detectors, featuring a 50μm thick high-resistivity epitaxial layer and different gain layer implants, have been completed successfully. Using transient current technique, the charge gain of a 1 × 1 mm 2 LGAD device from one of the wafers was found to be higher than 10, with jitter reaching 10 ps when biased at 240 V. Tests with other wafers are under way.

Combining TCAD and Monte Carlo methods to simulate CMOS pixel sensors with a small collection electrode using the Allpix[formula omitted] framework

Combining electrostatic field simulations with Monte Carlo methods enables realistic modeling of the detector response for novel monolithic silicon detectors with strongly non-linear electric fields. Both the precise field description and the inclusion of Landau fluctuations and production of secondary particles in the sensor are crucial ingredients for the understanding and reproduction of detector characteristics.In this paper, a CMOS pixel sensor with small collection electrode design, implemented in a high-resistivity epitaxial layer, is simulated by integrating a detailed electric field model from finite element TCAD into a Monte Carlo based simulation with the Allpix2 framework. The simulation results are compared to data recorded in test-beam measurements and very good agreement is found for various quantities such as cluster size, spatial resolution and efficiency. Furthermore, the observables are studied as a function of the intra-pixel incidence position to enable a detailed comparison with the detector behavior observed in data.The validation of such simulations is fundamental for modeling the detector response and for predicting the performance of future prototype designs. Moreover, visualization plots extracted from the charge carrier drift model of the framework can aid in understanding the charge propagation behavior in different regions of the sensor.

Analyses of Pinned Photodiodes With High Resistivity Epitaxial Layer for Indirect Time-of-Flight Applications

This article analyzes the performance of pinned photodiode (PPD) for Time-of-Flight(ToF) applications on high resistivity epitaxial wafers. Due to its wide depletion region, high epitaxial resistivity PPDs feature some key advantages in collecting photogenerated charges. This article compares the demodulation contrast of the same pixel design on epitaxial wafers with different resistivity at near-infrared wavelength to analyze their performance. By comparing the simulated profile of pixels with different epitaxial resistivity, the characteristics of the PPD pixel on high resistivity epitaxial wafer when collecting photogenerated charges are concluded. This article also discusses the effects of using high resistivity epitaxial wafer with various design parameters. It is found that the use of high resistivity epitaxial wafer can greatly improve crosstalk performance, allow pixels to work at higher modulation frequencies, and enable large-sized pixels to have good demodulation capabilities.

Simulations of CMOS pixel sensors with a small collection electrode, improved for a faster charge collection and increased radiation tolerance

CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel sizes larger than approximately forty micrometers. This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations. The studied design uses a 0.18 μm process implemented on a high-resistivity epitaxial layer.

Comparison of small collection electrode CMOS pixel sensors with partial and full lateral depletion of the high-resistivity epitaxial layer

Abstract Large area silicon pixel trackers are currently under development for the High Luminosity upgrade of the LHC detectors. They are also foreseen for the detectors proposed for the future high energy Compact Linear Collider CLIC. For the CLIC tracker a single hit resolution of 7 μ m, a timing resolution of a few nanoseconds and a material budget of 1–2 % of radiation length per detection layer are required. Integrated CMOS technologies are promising candidates to reduce the cost, facilitate the production and to achieve a low material budget. CMOS sensors with a small size of the collection electrode benefit from a small sensor capacitance, resulting in a large signal to noise ratio and a low power consumption. The Investigator is a test-chip developed for the ALICE Inner Tracking System upgrade, implemented in a 180 nm CMOS process with a small collection electrode on a high resistivity epitaxial layer. The Investigator has been produced in different process variants: the standard process and a modified process, where an additional N-layer has been inserted to obtain full lateral depletion. This paper presents a comparison of test-beam results for both process variants, focuses on spatial and timing resolution as well as efficiency measurements.

Technologies for future vertex and tracking detectors at CLIC

CLIC is a proposed linear $e^{+}e^{-}$ collider with center-of-mass energies of up to $3\,\textrm{TeV}$. Its main objectives are precise top quark and Higgs boson measurements, as well as searches for Beyond Standard Model physics. To meet the physics goals, the vertex and tracking detectors require not only a spatial resolution of a few micrometers and a very low material budget, but also timing capabilities with a precision of a few nanoseconds to allow suppression of beam-induced backgrounds. Different technologies using hybrid silicon detectors are explored for the vertex detectors, such as dedicated readout ASICs, small-pitch active edge sensors as well as capacitively coupled High-Voltage CMOS sensors. Monolithic sensors are considered as an option for the tracking detector, and a prototype using a CMOS process with a high-resistivity epitaxial layer is being designed. Different designs using a silicon-on-insulator process are under investigation for both vertex and tracking detector. All prototypes are evaluated in laboratory and beam tests, and newly developed simulation tools combining Geant4 and TCAD are used to assess and optimize their performance. This contribution gives an overview of the R&D program for the CLIC vertex and tracking detectors, highlighting new results from the prototypes.

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ∼10 m2, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10−6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 1013 1 MeV neq/cm2, which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm2. This contribution will provide a summary of the ALPIDE features and main test results.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120V. The TowerJazz 180nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15mm×30mm and contains a matrix of 512×1024pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5 and a spatial resolution of 5μm. The capability to read out Pb–Pb interactions at 100kHz is provided. The power density of the ALPIDE chip is projected to be less than 35mW/cm2 for the application in the Inner Barrel Layers and below 20mW/cm2 for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported.

Characterization of vertical Au/β-Ga2O3 single-crystal Schottky photodiodes with MBE-grown high-resistivity epitaxial layer**Project supported by the National Nature Science Foundation of China (Grant No. 61223002) the Science and Technology Commission of Shanghai Municipality, China (Grant No. 13111103700), and the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 2012018530003).

High-resistivity β-Ga2O3 thin films were grown on Si-doped n-type conductive β-Ga2O3 single crystals by molecular beam epitaxy (MBE). Vertical-type Schottky diodes were fabricated, and the electrical properties of the Schottky diodes were studied in this letter. The ideality factor and the series resistance of the Schottky diodes were estimated to be about 1.4 and 4.6× 106 Ω. The ionized donor concentration and the spreading voltage in the Schottky diodes region are about 4 × 1018 cm−3 and 7.6 V, respectively. The ultra-violet (UV) photo-sensitivity of the Schottky diodes was demonstrated by a low-pressure mercury lamp illumination. A photoresponsivity of 1.8 A/W and an external quantum efficiency of 8.7 × 102% were observed at forward bias voltage of 3.8 V, the proper driving voltage of read-out integrated circuit for UV camera. The gain of the Schottky diode was attributed to the existence of a potential barrier in the i–n junction between the MBE-grown highly resistive β-Ga2O3 thin films and the n-type conductive β-Ga2O3 single-crystal substrate.

Injection-dependent Minority Carrier Lifetime in Epitaxial Silicon Layers by Time-resolved Photoluminescence

Time-resolved photoluminescence (TRPL) is used to evaluate the injection-dependent effective minority carrier lifetime of high resistivity epitaxial silicon layers grown on highly doped CZ-Si substrates. Effective lifetimes ranging from 10μs to 200μs are estimated for excess carrier densities between 1x1017 cm-3 and 2x1016 cm-3. Standard models are used to separate the contribution from the different recombination mechanisms. The influence of the epitaxial layer and substrate parameters on the minority carrier effective lifetime measurement is discussed.

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018–2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500MeV.

MAPS development for the ALICE ITS upgrade

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

CMOS monolithic active pixel sensors for high energy physics

Monolithic pixel detectors integrating sensor matrix and readout in one piece of silicon are only now starting to make their way into high energy physics. Two major requirements are radiation tolerance and low power consumption. For the most extreme radiation levels, signal charge has to be collected by drift from a depletion layer onto a designated collection electrode without losing the signal charge elsewhere in the in-pixel circuit. Low power consumption requires an optimization of Q/C, the ratio of the collected signal charge over the input capacitance [1]. Some solutions to combine sufficient Q/C and collection by drift require exotic fabrication steps. More conventional solutions up to now require a simple in-pixel readout circuit. Both high voltage CMOS technologies and Monolithic Active Pixel Sensors (MAPS) technologies with high resistivity epitaxial layers offer high voltage diodes. The choice between the two is not fundamental but more a question of how much depletion can be reached and also of availability and cost. This paper tries to give an overview.

Effects of Substrate Thinning on the Properties of Quadruple Well CMOS MAPS

The chip prototype Apsel4well, including monolithic active pixel sensor (MAPS) test structures, has been designed for vertexing applications requiring a fast and low material silicon vertex tracker. The chip is fabricated in a 180 nm CMOS process called INMAPS, featuring a quadruple well and a high resistivity epitaxial layer option. The main advantage with this approach lies in the chance of increasing the in-pixel intelligence as compared to standard three transistor MAPS schemes. Moreover, the presence of the quadruple well and of the high resistivity epitaxial layer leads to better charge collection performance and radiation resistance. Different samples of the Apsel4well chip have been thinned down to about 25 μm and 50 μm. This minimization of the material can further improve the tracker performance virtually with no charge signal loss. At the beginning, this paper focuses on the results from charge collection TCAD simulations of the Apsel4well pixel structure performed at different thicknesses and substrate bias voltages. Later on, results from measurements relevant to the thinned chips both in terms of analog front-end channel performance and charge collection properties will be shown and compared to those from non-thinned chips.

A Digital Monolithic Active Pixel Sensor Chip in a Quadruple-Well CIS Process for Tracking Applications

A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 μm Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement of the radiation hardness, the power dissipation and the readout speed of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. In this paper a digital CMOS sensor prototype developed in order to validate the key analog blocks (from sensing element to 1-bit digital conversion) of a binary Monolithic Active Pixel Sensor (MAPS) in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 μm pitch 64 × 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. Some irradiation results will also be given.

Modeling Charge Loss in CMOS MAPS Exposed to Non-Ionizing Radiation

A model, approximating minority carrier diffusion with a discrete random walk and accounting for radiation induced reduction of minority carrier lifetime, is proposed to predict the effects of neutron irradiation on the charge collection properties of monolithic active pixel sensors (MAPS) in CMOS technology. The model has been implemented in a Monte Carlo code to simulate MAPS operation in minimum ionizing particle detection systems. For the purpose of validating it, the results from the characterization of monolithic sensors irradiated up to an integrated fluence of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> 1- MeV-neutron equivalent/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> have been compared with the outcomes of the Monte Carlo simulations. The monolithic sensors taken into consideration for the model validation are based on two different CMOS processes, one featuring a triple well option, the other one featuring a quadruple well structure and a standard (10 Ω·cm) or high (1 kΩ·cm) resistivity epitaxial layer. Simulation results are shown to be in good agreement with experimental data. The consistency between the model and the measurement results seems to confirm that radiation induced increase in the recombination rate is the main source of charge collection degradation in neutron-irradiated MAPS.

Optimization of CMOS pixel sensors for high performance vertexing and tracking

CMOS Pixel Sensors tend to become relevant for a growing spectrum of charged particle detection instruments. This comes mainly from their high granularity and low material budget. However, several potential applications require a higher read-out speed and radiation tolerance than those achieved with the available devices based on a 0.35μm feature size technology. This paper shows preliminary test results of new prototype sensors manufactured in a 0.18μm process based on a high resistivity epitaxial layer of sizeable thickness. Grounded on these observed performances, we discuss a development strategy over the coming years to reach a full scale sensor matching the specifications of the upgraded version of the Inner Tracking System (ITS) of the ALICE experiment at CERN, for which a sensitive area of up to ∼10m2 may be equipped with pixel sensors.