high-Q Inductors Research Articles

Compact low voltage high-Q CMOS active inductor suitable for RF applications

A compact active inductor circuit is proposed. The circuit is based on the gyrator-C approach with both transconductance stages realized by MOS transistors in common-source configuration. The circuit has minimal number of transistors, is suitable for low voltage operation, offers a wide inductive band, high quality factor and low power dissipation. Simulation results are provided for a 0.13 μm CMOS process with 1.2 V supply voltage.

Vertical co-integration of AlSi MEMS tunable capacitors and Cu inductors for tunable LC blocks

This paper describes a new process for the vertical co-integration of AlSi MEMS tunable capacitors and thick-Cu high-Q inductors. Tunable area MEMS capacitors with fragmented electrodes and with both thermal and electrostatic actuators are designed and validated. Thick copper layers are used for a double purpose: (i) to design and fabricate vertically integrated high-Q inductors and (ii) to define lateral electrostatic actuators for the MEMS capacitors. The achievable performances and flexibility associated with the new process to fabricate LC tanks are finally discussed.

High-$Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW

On-Chip High-$Q$Variable Inductor Using Wafer-Level Chip-Scale Package Technology

In this paper, the authors propose an on-chip high-Q variable inductor embedded in wafer-level chip-scale package (WL-CSP). The variable inductor has a metal plate and a spiral inductor fabricated by the WL-CSP technology. The metal plate can be moved by a microelectromechanical systems (MEMS) actuator, and the inductance is varied according to the position of the metal plate. At the present time, the MEMS actuator has not been implemented yet. In this paper, the authors present a feasibility study on the proposed variable inductor. The inductor is evaluated with measurement results using a metal plate moved by a micromanipulator instead of the MEMS actuator. At 2 GHz, the measured inductance is varied from 4.80 to 2.27 nH, i.e., the variable ratio is 52.6%. The maximum value of quality factor is 50.1

High-Performance 2-GHz CMOS LC VCO With High-Q Embedded Inductors Using Wiring Metal Layer in a Package

This paper focuses on high-performance LC CMOS voltage-controlled oscillator (VCO) design at 2 GHz with high-Q inductors realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. A fine-pitch ball-grid array (FBGA) package and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared with a Si on-chip inductor. The effects of the high Q-factor on the VCO performance are investigated. In addition, the dominant loss factor in an LC-tank is analyzed from the phase noise perspective. The VCOs using three different inductor technologies are presented. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously

Grating Metal Structure with Low-K Benzocyclobutene and Electroplated Copper for High-Q Spiral Inductors

In this paper, we propose a grating metal structure with low-K benzocyclobutene (BCB) and electroplated copper to increase the Q-factor of a spiral inductor. The grating metal structure was fabricated using simple electroplated copper and showed a maximum quality factor (Qmax) of 4 nH in spiral inductors, which is 15% more than that in normal spiral inductors with the same metal thickness. From the proposed equivalent lumped element model, the enhancement in quality factor was found to result from the reduction in series resistance, which was caused by the increase in effective current area. This technique can be applied to increasing the Q-factor of a spiral inductor in a silicon-based radio-frequency-integrated circuit (RFIC).

Equivalent circuit model of a stacked inductor for high-Q on-chip RF applications

A novel design for a stacked inductor using RLC elements is presented. The proposed model used to predict the stacked inductor is based on a 4-port circuit design with semi-empirical derivation. The modified R S formulas are implemented accurately to predict the series resistance of the stacked inductor. The verification has been carried out using a mature 0.18 mum process to fabricate stacked inductor with various sizes and types. All the measured data are extracted from a silicon device based on a physical layered test system (PLTS). The predicted and measured S-parameter results show excellent correlation in terms of performance for frequencies up to 15 GHz. A high-Q on-chip active inductor is demonstrated using a multiple turns stacked inductor

A 22-GHz push-push CMOS oscillator using micromachined inductors

This letter presents a low phase noise 0.35-/spl mu/m CMOS push-push oscillator utilizing micromachined inductors. This oscillator results in an improvement in phase noise compared with the previously published Si-based voltage-controlled oscillators (VCOs) around 20GHz. With the high-Q inductors introduced by the micromachined structure, the oscillator achieves an oscillating frequency of 22.2GHz while exhibiting an output power of -7.5dBm with a phase noise of -110.1dBc/Hz at 1-MHz offset. This work also demonstrates the highest operating frequency among previously published Si-based VCOs using micromachined structures.

Passive and heterogeneous integration towards a Si-based System-in-Package concept

Recently Philips launched their first highly integrated cellular RF-transceiver systems using a new Si-based System-in-Package (SiP) technology. This technology utilizes back-end processing to integrate passive components onto a Si-substrate that serves as a platform for heterogeneous integration with active dies, MEMS dies, etc. As an example, a transceiver IC is flip-chip mounted onto this passive component substrate, thus minimizing interconnect parasitics and footprint area. Next, this sub-assembly is flipped back into a standard single IC-sized lead frame package. This paper reports on such Si-based SiP transceiver modules and the underlying technologies. Here, the passive die is made by the so-called PICS ( Passive Integration Connecting Substrate) technology that integrates passive components on one die, such as high-Q inductors, resistors, accurate MIM capacitors and, in particular, high-density (∼ 20–30 nF/mm 2) MOS ‘trench’ capacitors for decoupling. These MOS capacitors integrated in RF power amplifiers showed superior signal stability compared to discrete ceramic capacitors. Ultralow-loss factors were measured: series inductance ESL < 40 pH and resistance ESR < 150 mΩ, combined with superior dielectric breakdown voltage (30 V), low leakage (< 1 nA/mm 2 at 22 V) and long lifetime of 10 years at 100 °C and 10 V).

Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.

Characterization of high-Q spiral inductors on thick insulator-on-silicon

This paper reports on the fabrication and characterization of high quality factor (Q) copper (Cu) inductors with thick insulator on standard silicon (Si) substrate (ρ = 10–20 Ω cm). The thickness and the area of the insulating layer are optimized for high Q by fabricating inductors on very thick (∼50 µm) embedded silicon dioxide (SiO2) islands and 4–20 µm thick PECVD SiO2 coated standard Si substrate. The effect of the dielectric permittivity is verified by comparing the performances of identical inductors fabricated on 20 µm thick SiO2 and 20 µm thick low-k polymer coated standard Si substrate. Measurement results show saturation behavior for the inductor Q versus the area and the thickness of the insulating layer. A 0.9 nH inductor fabricated on a 50 µm thick embedded oxide island (OI) exhibits a high peak Q of 53 at 2 GHz. The Q of an identical inductor on 20 µm thick PECVD SiO2 is 45 at 2 GHz.

A 0.35-/spl mu/m CMOS 2-GHz VCO in wafer-level package

This letter presents a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) with a high-Q inductor in a wafer-level package for the LC-resonator. The on-chip inductor is implemented using the redistribution metal layer of the wafer-level package (WLP), and therefore it is called a WLP inductor. Using the thick passivation and copper metallization, the WLP inductor has high quality-factor (Q-factor). A 2-nH inductor exhibits a Q-factor of 8 at 2 GHz. The center frequency of the VCO is 2.16 GHz with a tuning range of 385 MHz (18%). The minimum phase noise is measured to be -120.2 dBc/Hz at an offset frequency of 600 kHz. The dc power consumed by the VCO-core is 1.87 mW with a supply voltage of 1.7 V and a current of 1.1 mA. The output power with a 50-/spl Omega/ load is -12.5/spl plusmn/1.3 dBm throughout the whole tuning range. From the best of our knowledge, compared with recently published 2-GHz-band 0.35 /spl mu/m CMOS VCOs in the literature, the VCO in this work shows the lowest power consumption and the best figure-of-merit.

Fabrication and modeling of silicon-embedded high-Q inductors

In this paper, we report on the fabrication and modeling of a CMOS-compatible silicon-embedded high-Q integrated inductor (µH range). The fabrication process is based on DRIE, pulse-reverse super-conformal electroplating of copper and chemical–mechanical polishing. A lumped-element equivalent circuit model based on electromagnetic finite-element simulations for the determination of the element values was also developed. Inductors with different geometric design parameters were simulated to show the optimization possibility using the model. A Q-factor of over 60 (at 30–40 MHz) for a 2 µH inductor was measured, which is the highest reported in the literature for integrated inductors at such frequencies. The measurement results closely match the simulations from the lumped circuit model.

A deep submicrometer CMOS process compatible high-Q air-gap solenoid inductor with laterally laid structure

A high-quality (Q) on-chip solenoid inductor has been fabricated by 0.18 mm CMOS technology with air-gap structure. The solenoid structure with laterally laid out structure saves the chip area significantly and the air-gap suppresses the parasitic capacitances to obtain high-Q value. Additionally, with software ANSYS simulation, the solenoid inductor also possesses a higher strength for impact (80 000 times) in comparison to a spiral inductor. The measured peak-Q and peak-Q frequency with an air-gap are 8.8 and 1.7 GHz, respectively, which present almost 9% improvements in the magnitude and 54% in the peak-Q frequency in comparison to the conventional solenoid inductor at 8.1 and 1.1 GHz.

Comparison of the "pad-open-short" and "open-short-load" deembedding techniques for accurate on-wafer RF characterization of high-quality passives

The impedance errors remaining after applying the industry standard open-short, a pad-open-short, and a open-short-load deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz. Since the latter two deembedding schemes both correct for all parasitic elements of the test structures, they are, at least in principle, error free. The accuracy of the open-short-load deembedding scheme, however, critically depends on how well the reactive part of the load resistance is accounted for. This issue makes the more simple pad-open-short deembedding scheme an attractive choice because the required split between external and internal capacitances is easy to make, either based on process and layout information or from measurements done on a pad dummy structure

Low-noise and high-linearity LNA based on InGaP/GaAs HBT for 5.3-GHz WLAN

This paper presents a low-noise and high-linearity LNA based on InGaP/GaAs HBT for 5.3-GHz WLAN. Previous LNAs based on FET series (such as HEMTs) show excellent noise characteristics, but poor linearity. The InGaP/GaAs HBT LNA shows excellent linearity and noise characteristics because of its high base-doping concentration. The proposed LNA is fully integrated in a single chip of area 0.9 × 0.9 mm2 with high-Q spiral inductors and MIM capacitors, and is biased at the current point for optimum noise figure and gain characteristics; furthermore, excellent linearity is achieved. The measured result of the proposed LNA shows 13-dB gain, 2.1-dB noise figure, and excellent linearity with IIP3 of 5.5 dBm. The figure of merit (FOM), defined as a function of the linearity and noise figure, is 20.1 dB, which is the best result among previous LNAs. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 46: 550–553, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21047

Accurate characterization of MEM inductors on lossy silicon

AbstractThis paper presents the performance characteristics of an air‐suspended high‐Q MEM inductor that is characterized based on an open‐short deembedding scheme and used for accurate and reliable evaluation of the parasitic effects experienced from feed lines as well as contact pads. The validity and effectiveness of the de‐embedding method are proven with a fixed‐length MEM transmission line along with various feed‐line topologies. The measured inductances of the 20‐μm elevated transmission line provide consistent data, as compared to the simpler open de‐embedding method. For more realistic and complicated MEM inductors with 1.5 and 2.5 turns, the characterized inductance values agree very well with the calculated data, based on the Greenhouse algorithm. The measured and calculated inductances are within the 5% range. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 43: 355–358, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20468

CMOS-Compatible Micromachined Edge-Suspended Spiral Inductors With High Q-Factors and Self-Resonance Frequencies

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-/spl mu/m suspended edge in 25-/spl mu/m-wide lines.

3-D-Integrated RF and Millimeter-Wave Functions and Modules Using Liquid Crystal Polymer (LCP) System-on-Package Technology

Electronics packaging evolution involves system, technology, and material considerations. In this paper, we present a novel three-dimensional (3-D) integration approach for system-on-package (SOP)-based solutions for wireless communication applications. This concept is proposed for the 3-D integration of RF and millimeter (mm) wave embedded functions in front-end modules by means of stacking substrates using liquid crystal polymer (LCP) multilayer and /spl mu/BGA technologies. Characterization and modeling of high-Q RF inductors using LCP is described. A single-input-single-output (SISO) dual-band filter operating at ISM 2.4-2.5 GHz and UNII 5.15-5.85 GHz frequency bands, two dual-polarization 2/spl times/1 antenna arrays operating at 14 and 35 GHz, and a WLAN IEEE 802.11a-compliant compact module (volume of 75/spl times/35/spl times/0.2 mm/sup 3/) have been fabricated on LCP substrate, showing the great potential of the SOP approach for 3-D-integrated RF and mm wave functions and modules.

Wafer-Level Packaging Technology for High-&amp;lt;tex&amp;gt;$Q$&amp;lt;/tex&amp;gt;On-Chip Inductors and Transmission Lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.