High-performance ZnO Thin-film Transistors Research Articles

High-Performance ZnO Thin-Film Transistors on Flexible PET Substrates With a Maximum Process Temperature of 100 °C

In the present work, we testify a strategy to achieve high-performance ZnO thin film transistors (TFTs) on a flexible PET substrate at a maximum process temperature no more than 100 °C. Interestingly, the ZnO TFTs exhibit superior electrical properties, including a field-effect mobility of 14.32 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , a sub-threshold swing of 0.21 V/decade, and an on-to-off current ratio of 3.03 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> . Also, ideal uniformity, hysteresis property, contact resistance, and stability are achieved. Threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) under positive and negative bias stress are 0.17 and -0.18 V, respectively. Moreover, the ZnO TFTs manifest good mechanical performance at a bending radius of 10 mm. We expect that our findings propel practical application of the oxide TFTs in flexible electronics.

Solution-Processed La Alloyed ZrOx High-k Dielectric for High-Performance ZnO Thin-Film Transistors

We report La alloyed ${ZrO}_{x}$ high- ${k}$ gate insulator (GI) for $ZnO$ thin-film transistors (TFTs) by solution-process. The La concentration in ${ZrO}_{x}$ is varied from 0 to 7.5% for optimum device performance. The atomic force microscopy and X-ray photoelectron spectroscopy analysis of 5% La alloyed ${ZrO}_{x}$ GI show smooth surface with higher metal-oxide (M – O) bonds and reduced defect density in the bulk compared with pristine ${ZrO}_{x}$ . Therefore, $ZnO$ TFT using 5% La alloyed ${ZrO}_{x}$ GI exhibits hysteresis-free device performance, with saturation mobility of $11.58 {cm}^{2}/V\cdot s$ , $I_{ \mathrm{ON}}/I_{ \mathrm{OFF}}$ ratio of $2.67\times 10^{8}$ , threshold voltage of $1.25 V$ , and subthreshold swing of $249 mV/dec$ . We also achieve highly stable ZnO TFTs under positive bias stress using 5% La alloyed ${ZrO}_{x}$ GI.

High-Performance 1-V ZnO Thin-Film Transistors With Ultrathin, ALD-Processed ZrO2Gate Dielectric

The high-performance ZnO thin-film transistors (TFTs) were fabricated on indium tin oxide glass with high-capacitance atomic layer deposition (ALD)-processed ZrO2 as the gate dielectric. The 5-nm ultrathin ZrO2 film showed a very high areal capacitance of 820 nF/cm2 at 20 Hz, a relatively high breakdown field of 14 MV/cm, and low surface root-mean-square (rms) roughness of 0.22 nm, making it possible for ZnO/ZrO2 TFT to not only be operated by an ultralow operating voltage of 1 V but also present a near theoretical limit subthreshold swing of 69 mV/dec. Furthermore, the ZnO TFT with a 5-nm ZrO2 gate dielectric exhibited excellent performance, such as a high Ion/Ioff of 107, large field effect mobility of 36.8 cm2/Vs, low-density of trapping states ( ${N}_{{\text {trap}}}$ ) of $1.6\times 10^{{11}}$ eV−1cm−2, and negligible hysteresis. In addition, the electron transport mode was built to explain the high mobility of nanocrystalline ZnO TFT. As a result, the ultralow operating voltage TFTs exhibited great potential for low-powered electronics applications.

High-Performance ZnO Thin-Film Transistors Prepared by Atomic Layer Deposition

High-performance ZnO thin-film transistors (TFTs) have been successfully fabricated by atomic layer deposition (ALD) with a maximum temperature of 200 °C. The impacts of deposition and annealing temperature on the characteristics of devices were discussed. ZnO thin films show a (002) preferred orientation at the high growth temperature. The carrier concentrations of ZnO TFTs can be optimized by appropriate growth temperature and annealing treatments. Subthreshold swing (SS) and hysteresis windows of TFTs are improved after annealing in dry O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> due to the reduction in traps at ZnO/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface or/and within the ZnO channel. The ZnO TFT deposited at 150 °C with 200 °C annealing in oxygen demonstrates excellent electrical characteristics with high saturation mobility μsat of 7.8 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , small SS of 127 mV/decade, high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of 2.8 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , and good contact between source/drain electrodes. The high-performance ZnO TFTs with low processing temperatures have great potential in application for flexible electronics.

Low temperature processing of Al2O3-GPTMS-PMMA hybrid films with applications to high-performance ZnO thin-film transistors

In this work we evaluate the synthesis of inorganic-organic Al2O3-GPTMS-PMMA hybrid films using a low temperature sol-gel process and their use as gate dielectric for thin film transistors (TFTs). The hybrid films were deposited by dip coating process and then annealed at 150 °C in air. The analysis of the hybrid films was performed by UV–VIS spectroscopy, FTIR, AFM, SEM, C-V and I-V measurements. The optical transparency above 85% in the visible range and homogeneity of the hybrid films support the proper link between inorganic and organic phases with strong bonds. At microscopic level, the hybrid films have uniform surface roughness lower than 1 nm. The C-V and I-V measurements performed on MIM structures showed leakage current density in the order of 10−7 A/cm2 at 104 kV/cm electric field. Capacitance and dielectric constant measured at 1 kHz were 20.4 pF and of 6.2, respectively. TFTs were fabricated using bottom gate and aluminium top contacts to obtain mobilities of 4.5 cm2/Vs, threshold voltage of 0.7 V and Ion/Ioff ratio of 107, while mantaining operating voltage under 8 V.

Solution-processed ZnO thin-film transistors codoped with Na and F

Na and F codoping was utilized to realize high-performance ZnO thin-film transistors derived from sol–gel solution process. The effect of NaF doping concentration on the electrical properties of ZnO thin-film transistors annealed at 350 °C was investigated. Films with 10 at.% doping exhibited excellent performance with an average mobility of 70.98 cm2 V−1 s−1 and a high Ion/Ioff ratio on the order of 106. The X-ray photon spectroscopy exhibited oxygen bound with oxide lattice with and without vacancy related peak position shifted towards lower energy side when doped at 10 at.% and did not show the hydroxyl group on the NaF doped ZnO surface which indicates the improved performance of the thin-film transistors devices. The electrical performance of the devices also changed considerably as the thickness of the NaF-doped ZnO layer increased. Increasing the grain size and realizing a smooth surface morphology by varying the NaF concentration were found to enhance the thin-film transistors mobility.

Sol-gel derived Hf- and Mg-doped high-performance ZnO thin film transistors

We report high-performance Hf- and Mg-doped ZnO thin film transistors (TFTs) with various doping concentrations and annealing temperatures of 400 and 450 °C fabricated using a sol-gel solution process. The ZnO TFTs doped with 2 at% Hf exhibited high performances with average mobilities of 4.17 and 19.04 cm2V−1s−1 when annealed at 400 and 450 °C, respectively, along with high Ion/Ioff ratios on the order of 106. The Mg-doped ZnO TFTs showed no significant change in the device performance when varying the doping concentration and annealing temperature. The chemical composition was examined using X-ray photoelectron spectroscopy and it was confirmed that the Hf was doped in the ZnO thin films at both annealing temperatures. The improved electrical performance was attributed to an increase in the grain size at the optimized doping concentration.

Fabrication of High-Performance ZnO Thin-Film Transistors With Submicrometer Channel Length

A method was developed to fabricate ZnO thin-film transistors (TFTs) with submicrometer channel length. In this scheme, mature process techniques are used to form a suspending hardmask bridge on the wafer surface, which enables the subsequent construction of a TFT by the sequential deposition of gate oxide, ZnO channel layer, and Al source/drain contacts. Excellent electrical characteristics were demonstrated by the fabricated ZnO TFTs that show high ON/OFF current ratio , low subthreshold swing (89 mV/decade), and high field-effect mobility (41 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V s). Very small variation in the device characteristics is also demonstrated.

High-performance ZnO thin-film transistors fabricated at low temperature on glass substrates

A high-performance enhancement-mode ZnO thin-film transistor (TFT) on a glass substrate is demonstrated. The ZnO thin film is deposited by RF magnetron sputtering with the presence of O2 at low deposition rate and low temperature. The IDS is as high as 1 mA when biased at the saturation region VDS=10–20 V and VGS=5 V without any post-thermal anneal. The Ion/Ioff ratio is 3×106. The results are among the best ZnO TFTs ever obtained.

High-performance ZnO thin-film transistors on gate dielectrics grown by atomic layer deposition

We fabricated high-performance ZnO thin-film transistors on gate dielectrics of HfO2, HfSiOx, and Al2O3, grown by atomic layer deposition (ALD). Devices on HfO2 had a mobility of 12.2cm2∕Vs with a threshold voltage of 2.6V and subthreshold slope of 0.5V∕decade. Device performance on Al2O3 depended on synthesis temperature. For 100nm thick Al2O3, synthesized at 200°C, ZnO devices had a mobility of 17.6cm2∕Vs with a threshold voltage of 6V and less than ∼0.1nA gate leakage at 20V. The overall trends were that devices on Hf oxides had a lower threshold voltage, while the gate leakage current density was lower on Al2O3. Device characteristics for all ALD dielectrics exhibited negligibly small hysteresis, suggesting a low defect density at the interface of ZnO with the gate dielectric.