High Performance Sense Amplifier Research Articles

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point

The transistor offset from sense amplifiers affects the sensing performance in dynamic random-access memory (DRAM). Although various offset-compensation methods are available, the voltage mismatch remains large, and some methods are susceptible to timing variation. To improve the compensation effect and stability, we propose a current-mirror and switching-point compensation sense amplifier. The amplifier compensates one bit-line voltage to the switching point of an inverter and adjusts the other bit-line by a current mirror during compensation. The configuration is robust against timing variation. Moreover, the voltage of complementary bit line considerably changes due to the high gain of the switching point. Simulation results show that the voltage mismatch can be improved by 90% compared with that of a boosted reference voltage sense amplifier. In addition, the increased bit-line differential voltage can improve the sensing speed. At a low supply voltage of 0.75 V, the sensing yield improves by 11% compared with that of a boosted reference voltage sense amplifier and by 16% compared with that of an offset-cancellation sense amplifier.

Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes

Spin-transfer torque magnetic RAM (STT-MRAM), which uses a magnetic tunnel junction to store binary data, is a promising memory technology. With many benefits, such as low leakage power, high density, high endurance, and nonvolatility, it has been explored as an SRAM replacement for cache design or a DRAM replacement for main memory. Meanwhile, along with the continuous shrinking of CMOS process technology, the bias temperature instability (BTI) effect has become a major reliability issue. Prior work has investigated the influence of the BTI effect on the SRAM sense amplifier, but no investigation has been done for the STT-MRAM sense amplifier. Therefore, this paper investigates the BTI effect on STT-MRAM sense amplifiers. We propose a majority-based technique and an alternative sensing technique to reduce circuit degradation. To further improve sensing delay, we propose using forward body bias (FBB) on an access transistor with a positive voltage. Extensive simulation results are done to show the effectiveness of the proposed techniques. The sensing delay for reading zeros and ones can be reduced by 10.61% and 4.35%, respectively, on average, with the majority-based technique. The sensing delay for reading zeros and ones can be reduced by 4.42% and 1.83%, respectively, on average, using the alternative sensing technique. The sensing delay for reading zeros and ones can be reduced by 15.37% and 6.25%, respectively, on average, by using both techniques simultaneously. When using the majority-based and alternative sensing techniques with the FBB technique, the sensing delay for reading zeros and ones can be improved by 29.93% and 57.67%, respectively, on average. We also analyze the BTI-induced degradation of a high-performance sense amplifier and a low power sense amplifier with the proposed techniques. The simulation results show that our proposed technique and simulation flow can be easily extended to other sense amplifiers.

Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory

A 200-KB embedded electrically erasable programmable read -only memory (EEPROM), which operates with a single 1.5-V power supply voltage based on an HHGRACE (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm EEPROM process, is developed. In this brief, several key design techniques are presented. An improved bit cell with a larger current sensing window is adopted in the split-source EEPROM array. To get high-speed read operation, a high-performance sense amplifier and a dynamic sensing window tracking reference voltage generating circuit have been proposed. The die size of the proposed EEPROM IP is 1.271 mm2, and the EEPROM cell size is 0.32 $\mu\text{m}^{2}$ . Access time of 30 ns is achieved at 1.5 V and 25 °C.

A 1.35-V 16-Mb Twin-Bit-Cell Virtual-Ground-Architecture Embedded Flash Memory With a Sensing Current Protection Technique

In this paper, a 1.35 V 16 Mb twin-bit-cell virtual ground architecture embedded Flash memory is presented. To reduce the sensing margin loss caused by the side-leakage current in the virtual ground architecture memory array, a sensing current protection technique has been proposed. A reference voltage generating circuit for dynamic sensing window tracking is designed to maximize the sensing window under various PVT (Process-Voltage-Temperature) conditions. With the reference voltage generating circuit and a high performance sense amplifier, high speed read operation is achieved. As four bitlines have to be selected to read one bit, an S-D-P-P (Source-Drain-Protection-Protection) style column decoding methodology has been introduced to support the sensing current protection technique. The embedded Flash IP has been fabricated in a GSMC 90 nm 4 poly 4 metal CMOS process. The die size of the proposed Flash IP is 3.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the memory cell size is 0.16 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Access time of 36 ns at 1.35 V has been achieved.

A high-performance very low-voltage current sense amplifier for nonvolatile memories

A high-performance sense amplifier for nonvolatile memories capable of working under a very low-voltage power supply is presented. The topology of the sense amplifier uses a pure current-mode comparison allowing power supplies lower than 1 V to be used and includes two subcircuits which improve slew rate performance. The sense amplifier was implemented in an EEPROM realized with a 0.18-/spl mu/m EEPROM technology. Experimental results showed a read access time of about 30 ns with a power supply of 1.65 V.

GaAs dynamic memory design

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 /spl mu/m nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns.