High-performance Polycrystalline Silicon Thin-film Transistors Research Articles

High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel

Polycrystalline silicon thin-film transistors (TFTs) integrating sputtered Al2O3 gate dielectric with bridged-grain active channel are demonstrated. The proposed TFTs exhibit excellent device performance in terms of smaller threshold voltage, steeper subthreshold swing and higher on-current/off-current ratio. More importantly, the mobility of the proposed TFT is 5.5 times that of conventional TFTs with SiO2 gate dielectric. All of these results suggest that the proposed TFT is a good choice for low-power and high-speed driving circuits in display application.

High-performance polycrystalline silicon thin-film transistors prepared via the laser crystallization of the prepatterned channel layer on the bottom-gate structure

High-performance polycrystalline silicon thin-film transistors (TFTs) using an excimer laser crystallization of the prepatterned channel layer on the bottom-gate (BG) structure were fabricated to exhibit a field-effect mobility as high as 339cm2/Vs and an on/off current ratio of 9.5×107 with respect to 102cm2/Vs and 1.5×107 for the conventional top-gate (TG) TFTs, respectively. Such a superior performance is attributed to the cross-shaped grain boundary structure formed in the channel region owing to the two-dimensional location control of grain boundaries. Moreover, the prepatterned BG TFTs show better device-to-device uniformity than the conventional TG ones due to the manipulated grain boundaries. This technology is thus promising for the future applications of system-on-panel and three-dimension integrated circuits.

High-Performance Polycrystalline Silicon Thin-Film Transistors with Two-Dimensional Location Control of the Grain Boundary via Excimer Laser Crystallization

High-performance low-temperature polycrystalline silicon (Poly-Si) thin-film transistors (TFTs) have been fabricated with two-dimensional (2-D) location-controlled grain boundaries using excimer laser crystallization (ELC). By locally increased thickness of the amorphous silicon (a-Si) film that was served as the seed crystals with a partial-melting crystallization scheme, the cross-shaped grain boundary structures were produced between the thicker a-Si grids. The Poly-Si TFTs with one parallel and one perpendicular grain boundary along the channel direction could therefore be fabricated to reach excellent field-effect mobility of 530 cm2/V-s while the conventional ones exhibited field-effect mobility of 198 cm2/V-s. Furthermore, the proposed TFTs achieved not only superior electric properties but also improved uniformity as compared with the conventional ones owing to the artificially controlled locations of grain boundaries.

High-Performance Polycrystalline Silicon TFT on the Structure of a Dopant-Segregated Schottky-Barrier Source/Drain

A high-performance polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Schottky-barrier (SB) source/drain (S/D) junctions is proposed. A p-channel operation on the intrinsic nickel (Ni) silicided S/D was successfully realized with the aid of a thin active layer, despite the fact that the Ni silicided material shows a high SB height (SBH) for holes. Furthermore, for n-channel operation, the dopant-segregation technique implemented on the intrinsic Ni silicide was utilized to reduce the effective SBH for electrons. The results show a higher on-current due to the lower parasitic resistance as well as superior immunity against short-channel effects, compared to the conventional poly-Si TFT composed of p-n S/D junctions.

CF4-Plasma-Induced Fluorine Passivation Effects on Poly-Si TFTs with High- κ Pr2O3 Gate Dielectric

High-performance polycrystalline silicon thin-film transistors ( TFTs) integrating high-κ gate dielectric and fluorine-passivated film are demonstrated. High gate capacitance density and thin equivalent-oxide thickness provided by the high-κ gate dielectric have the advantage of increasing the driving current capability of the TFT device, but an undesirable off-state leakage current could be introduced from the high electric field near the drain side. Introducing fluorine atoms into films by employing a low-temperature plasma treatment can effectively passivate the trap states. With plasma treatment on film, the electrical characteristics of TFTs can be significantly improved, including a steeper subthreshold swing, smaller threshold voltage, higher field-effect mobility, and better on/off current ratio compared with that without plasma treatment. The maximum off-state leakage current of the fluorine-passivated TFT is more than one order of magnitude lower than that of the control TFT. Furthermore, the incorporation of fluorine atoms by plasma treatment also improves the reliability of TFTs against hot carrier stressing, which is due to the formation of stronger bonds in place of weak bonds in the channel and at the gate interface. Therefore, high-performance and high-reliability TFTs with gate dielectric and plasma treatment on film are suitable for active-matrix liquid crystal display application.

High-Performance Polycrystalline-Silicon TFT by Heat-Retaining Enhanced Lateral Crystallization

High-performance low-temperature polycrystalline-silicon thin-film transistors (TFTs) have been fabricated by heat-retaining enhanced crystallization (H-REC). In the H-REC technology, a heat-retaining capping layer (HRL) is applied on the prepattern amorphous silicon islands to slow down the heat dissipation effectively. It thereby retains long duration of melting process and further enhances poly-Si-grain lateral growth. With a single shot of laser irradiation, the location-controllable poly-Si active layer with 7-mum length of grain size can be formed successfully. In addition, in this letter, the H-REC poly-Si TFT with dual gates is studied to enhanced electrical performance and stability.

High-Performance Polycrystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process

High-performance polycrystalline silicon thin-film transistors with a low trap density at the gate-SiO2/Si interface have been developed using a low-temperature process. It was found that high-performance thin-film transistors with a very low subthreshold swing could be achieved by applying postmetallization annealing at the end of the transistor fabrication. The subthreshold swing and electron mobility of the transistors were 143 mV/dec and 262 cm2 V-1 s-1, respectively, when the thickness of the gate-SiO2 was 114 nm. The ability to fabricate such high-performance thin-film transistors on a glass substrate will be very useful for realizing system-on-panel devices.

High-performance polycrystalline silicon thin-film transistors with oxide–nitride–oxide gate dielectric and multiple nanowire channels

This work presents a method to enhance the performance of polycrystalline silicon thin film transistors (poly-Si TFTs) by using an oxide–nitride–oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics compared to other TFTs. This is because a structure with more corners and a shorter radius has better gate control due to the corner effect.

Design and fabrication of high-performance polycrystalline silicon thin-film transistor circuits on flexible steel foils

This paper discusses in detail the design and fabrication process for the realization of high-performance polycrystalline silicon thin-film transistors and digital CMOS circuitry on thin flexible stainless steel foils. A comprehensive approach to substrate preparation is first presented. For transistor fabrication, distinct processing approaches are examined, such as solid-phase and excimer laser crystallization for the active semiconductor region, thermal growth and chemical vapor deposition for the gate insulator, and others. It is shown that process optimization has resulted in the fabrication of CMOS transistors with field-effect mobility values in the region of 200 cm/sup 2//V/spl middot/s and I/sub ON//I/sub OFF/ current ratios of at least seven orders of magnitude. The design and performance of high-speed digital CMOS is addressed, and the effects of the conductive foil through parasitic capacitive coupling are examined. CMOS inverter blocks in ring oscillator circuits operating with delay times as low as 1.12 ns are reported, as well as static and dynamic shift registers operating in the megahertz regime.

High-Performance Polycrystalline Silicon Thin-Film Transistors Fabricated by High-Temperature Process with Excimer Laser Annealing

Polycrystalline silicon (p-Si) thin-film transistors (TFTs) were fabricated using a high-temperature process that included solid-phase crystallization (SPC) and dry thermal oxidation with excimer laser annealing (ELA). X-ray diffraction and transmission electron microscopy analyses showed that the ELA process improved the quality of p-Si films markedly. The p-Si TFTs exhibited a higher performance than the SPC and a-Si+ELA p-Si TFTs. The field-effect mobility for n-type self-aligned TFTs was 251 cm2·V-1·s-1. The longitudinal junction diffusion length of the p-Si TFTs was shorter than that of the SPC p-Si TFTs. This is favorable for fine design rules. This fabrication process is consistent with the high-temperature-processed p-Si TFT development trend towards using large substrates, low temperatures, and fine design rules.

High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure

This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (>108), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies.

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.

Development of high-performance polycrystalline silicon thin-film transistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425/spl deg/C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO/sub 2//Si interface were controlled by a gate SiO/sub 2/ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm/sup 2/V/sup -1/s/sup -1/, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics.