High-performance poly-Si TFTs Research Articles

(Invited) Advanced Crystallization Using Blue Laser-Diode Annealing for Low Temperature Poly Si TFTs

Laser Crystallizations using Blue Laser-Diodes Annealing (BLDA) as well as conventional Excimer Laser Annealing (ELA) are discussed for mounting the TFTs on flexible panels. On glass, high crystallinity of Si films can be obtained by using multi-shots ELA as well as CW laser scanning [1, 2]. There are some issues for Si film after ELA, such as rough Si surface or shots MURA including the fabrication cost. As a result of scanning BLDA for thin Si films, remarkable crystallization occurs with keeping the surface smooth not only for CVD film but also for sputtered Si film [3]. By changing the laser power of 445 nm beam, the grain size can be controlled from micro-grains to large grains as well as to anisotropic long crystal grains [4]. For the Si films of heavily phosphorus doped condition, the resistivity decreased drastically due to the increase in the carrier mobility with high carrier concentration after BLDA of single beam scanning as well as after multi-shots ELA [5]. To realize high performance poly Si films directly not only on flexible glass [6] but also on flexible plastic sheet, effective laser annealing for high quality Si film by low temperature deposition is expected and a design for the thermal buffer layers on flexible sheet is effective [7]. To perform ultra-low temperature TFT process, metal source/drain structure without using ion implantation is also proposed. High performance poly Si TFTs with low fabrication cost on flexible panel should be possible not only for n-channel but also for p-channel [8, 9]. References M. Tai, M. Hatano, S. Yamaguchi, S. K. Park, T. Noda, M. Hongo, T. Shiba and M. Ohkura, Proc. of AM-LCD, TFT3-3, p.231 (2002)T. Noguchi, Mat. Res. Soc. Symp. Proc., 557, p.213 (1993),T. Okada, K, Sugihara, S. Chinen and T. Noguchi, J. Korean Phys. Soc., 66, No.8, pp.1266-1269 (2015). .T. Noguchi, J. Inf. Display, 11, No.1, p.12 (2010).T. Noguchi and T. Okada, J. of Inf. Display, 15, No.1, p.47 (2014).T. Harada, F. Gakiya, Y. Ishiki, T. Okada, T. Noguchi, K. Noda, A. Suwa and H. Ikenoue, Proc. of IDW, AMDp2-11L, p.444 (2016).T. Okada, J.D. Mugiraneza, K. Shirai, T. Suzuki, T. Noguchi, H. Matsushima, T. Hashimoto, Y. Ogino and E. Sahota, Jap. J. Appl. Phys. 51, 03CA02 (2012).K. Sugihara, K. Shimoda, T. Okada and T. Noguchi, J. Inf. Display, 18, No.4, 173-176 (2017).T. Ashitomi, T. Harada, T. Okada, T. Noguchi, O. Nishikata and A. Ota, J. Inf. Display, 18, No.4, 185-189 (2017).

(Invited) Advanced Crystallization Using Blue Laser-Diode Annealing for Low Temperature Poly Si TFTs

Laser Crystallizations using Blue Laser-Diodes Annealing (BLDA) is described for mounting the Si TFTs and the thin film functional sensors on panels. To realize high performance poly Si TFTs not only on glass but also on flexible sheets, effective laser annealing for high quality Si film by low temperature deposition is expected. To conduct a low temperature TFT process below 400°C, metal source/drain structure without using ion implantation is proposed as a low-cost fabrication. By inserting thermal buffer layers on flexible sheet, stable and effective crystallization of Si film using BLDA can be performed. High-performance CMOS TFT system with functional sensors is expected on arbitrary flexible sheets.

Study on Characteristics of Poly-Si TFTs With 3-D Finlike Channels Fabricated by Nanoimprint Technology

This study addresses the characteristics of polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 3-D finlike channels fabricated using ultraviolet nanoimprint lithography. The poly-Si 3-D finlike channels with a line width/space ratio of about $\sim$ 1 : 1 were fabricated and studied by scanning electron microscope and transmission electron microscopy. The poly-Si TFTs with 3-D finlike channels, fabricated using the nanoimprint technique, have superior performances in comparison to that with the single channel. Besides, the characteristics of poly-Si TFTs, such as the transfer characteristics, output drain current, transconductance, on/off current ratio, subthreshold swing, and field-effective mobility, with respect to the width/space/height of 3-D finlike structures were also investigated. The proposed approach can be utilized to fabricated high-performance poly-Si TFTs or high-sensitivity biosensors at low cost.

High-Performance Poly-Si TFTs of Top-Gate with High-κ Metal-Gate Combine the Laser Annealed Channel and Glass Substrate

High-Performance Poly-Si TFTs of Top-Gate with High-κ Metal-Gate Combine the Laser Annealed Channel and Glass Substrate

Recessed-Channel with Oxide Step Structure for High-Performance Dual-Gate Poly-Si TFTs with Controlled Grain Growth in Channel Regions

not Available.

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$\kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), relative to conventional deposited-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , as the gate dielectric had ca. 1.73 times the mobility (mu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> ) relative to that of the deposited-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> TFTs; in contrast, the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> TFTs. The immunity of the HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , TFTs was better than that of the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> TFTs-in terms of their V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift, SS degradation, mu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , rather than HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.

High performance poly-Si TFTs fabricated by continuous-wave laser annealing of metal-induced lateral crystallised silicon films

In this process, amorphous silicon was first transformed to polycrystalline silicon (poly-Si) using a metal-induced lateral crystallisation (MILC) process, followed by annealing with a continuous-wave laser lateral ( lambda~ 532 nm) crystallisation (CLC) with an output power of 3.8 W. MILC-CLC-TFT performed far superior to MILC-TFT. The mobility of the MILC-CLC-TFT was 293 cm 2 /Vs, which was much higher than that of MILC TFTs (54.8 cm 2 /Vs). In addition, MILC-CLC TFTs showed better device uniformity and reliability.

High Reliability and Performance Poly-Si TFTs for System in Displays

Narrow frame size IPS-mode LCD with high resolution system-in- display have been developed utilizing hybrid laser crystallization technology: SELAX are applied to low-power, high-speed circuits, and conventional ELC are used for the high- voltage circuits. The TFT degradation phenomena under dynamic stress are clarified, and the high-immunity TFT structure and high-quality gate insulator are proposed.

High Reliability and Performance Poly-Si TFTs for System in Displays

not Available.

High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure

In this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage.

28.2: Invited Paper: SLS Technology for High Performance Poly-Si TFTs and Its Application to Advanced LCD and SOG

SLS crystallization and CMOS LTPS process have been developed for high performance and uniform characteristics. By strictly optimizing SLS optics in conventional 2 shot SLS process, threshold voltage variation of 720 pixel TFTs in 2.2-inch QVGA panel (240×RGB) was remarkably decreased from 1.89 V to 0.56 V of 3sigma value. Mobility of the channel doped NTFT and PTFT for circuits were 146 and 38 cm2/Vs, respectively. Functional unit circuits for SOG were also fabricated and properly operated.

Effect of silicon thickness on the degradation mechanisms of sequential laterally solidified polycrystalline silicon TFTs during hot-carrier stress

We have investigated bias stress-induced aging effects in polycrystalline silicon thin-film transistors (poly-Si TFTs), as a function of the active layer thickness. Two aging mechanisms were identified: hot-carrier injection in the gate insulator and deep-state generation in the active body. Hot-carrier injection was found dominant in devices having very thin (30 nm) or thick (100 nm) active layers. Deep-state generation dominated in devices having intermediate active layer thickness (50 nm). The fully depleted aspect of ultrathin active-layer devices, as well as their relative immunity to substantial degradation under bias stress, favor the implementation of thin active layer for the fabrication of high-performance and high-reliability poly-Si TFTs.

46.3: High Performance Dual‐Gate and Multi Channel Poly‐Si TFTs fabricated by XeCl Excimer Laser Annealing on Selectively Floating a‐Si Thin Film

AbstractA high performance poly‐Si TFTs is fabricated by a new ELA method which employs floating a‐Si thin film structure and the effect of pre‐patterning. The proposed poly‐Si TFT exhibits high performance electrical characteristics which are high mobility of 504cm2/Vsec and low subthreshold slope of 0.337 V/dec.

High temperature crystallized poly-Si on Mo substrates for TFT application

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently in future high-resolution, high-performance flat panel display technology. However, it is very difficult to fabricate high performance poly-Si TFTs at temperatures lower than 300 °C and the substrate temperature of the process is limited to less than 600 °C on glass. This paper describes a high temperature process above 750 °C to obtain poly-Si films. Hydrogenated amorphous silicon (a-Si:H) layer was deposited on a flexible Mo metal substrate and crystallized by rapid thermal annealing for TFT application. The a-Si:H films were crystallized at various temperatures between 750 and 1050 °C. As annealing temperature was increased, the TFT exhibited increased transconductance ( g m) and reduced voltage between drain and source ( V ds), the threshold voltage ( V T). The high temperature annealed poly-Si film illustrated field effect mobility higher than 67 cm 2/Vs. We also investigated the types and activation energies of grain boundary trap, which are the function of annealing temperature. The poly-Si TFT showed an improved I on/ I off ratio of 10 6, reduced gate threshold voltage, and an increased field effect mobility by three orders.

Application of CW Laser Crystallization for Display Devices.

High-performance poly-Si TFTs were created using the diode pumped solid-state (DPSS) continuous-wave (CW) laser lateral crystallization (CLC) method through fabrication processes at no higher than 450 °C. With decreasing Si film thickness, the grain size became finer and the surface orientation of the grains changed from (100) to other orientations. These effects reduced the field-effect mobility as the Si film became thinner, but with the CLC method we can still obtain a high field-effect mobility of over 300 cm2/Vs without applying special processing techniques, even from a Si film as thin as 50 nm. We expect this crystallization method to lead to the fabrication of high-performance Si-LSI circuits on large non-alkaline glass substrates.

Electrical characteristics of polycrystalline silicon thin film transistors using the Cu-field aided lateral crystallization process

Polycrystalline silicon thin film transistors (poly-Si TFTs) were fabricated on glass substrate by using a concept of Cu-field aided lateral crystallization (Cu-FALC). The crystallization of a-Si was significantly enhanced when an electric field of 30 V/cm was applied to selectively Cu-deposited amorphous silicon (a-Si) film during thermal annealing at 500 °C for 3 h. These FALC TFTs using Cu exhibited a low off-state leakage current of 6.2 ×10−12 A at Vg=−10 V and a maximum on/off current ratio of 3.1×105. The field-effect mobility and the threshold voltage of the fabricated poly-Si TFT were about 22.0 cm2/V s and 3.9 V, respectively. Therefore, the possibility of high-performance and low-temperature (&amp;lt;500 °C) poly-Si TFTs was demonstrated by using Cu-FALC technology.

High-Quality SiO2/Si Interface Formation and Its Application to Fabrication of Low-Temperature-Processed Polycrystalline Si Thin-Film Transistor

Improvement of SiO2/Si interface quality and its effect on the performance of low-temperature-processed polycrystalline silicon thin-film transistors (poly-Si TFTs) are investigated. Two gate SiO2 formation conditions for realizing the density of interface states (Dit) at mid-gap of 1.4×1011 and 4.1×1010 cm-2eV-1 were applied to a 425°C TFT fabrication process using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). By reducing Dit, reduction of threshold voltage from 1.97 to 1.12 V, reduction of sub-threshold swing from 303 to 250 mV/decade and increase of mobility from 196 to 309 cm2V-1s-1 were observed. The analysis of TFT characteristics indicated the decrease of both deep and shallow level trap states. As a result, not only threshold voltage and sub-threshold swing, but also the mobility of the poly-Si TFT was significantly improved. The results indicate that low-temperature process technologies for forming a high-quality SiO2/Si interface are important for next-generation high-performance poly-Si TFTs.

Current and future technology of low‐temperature poly‐Si TFT‐LCDs

Abstract— The state of the art of large‐area low‐temperature TFT‐LCDs will be reported in this paper. High‐performance poly‐Si TFTs are expected to realize various applications such as system display where various signal‐processing functions are added to the display. In the past few years, low‐temperature poly‐Si thin‐film‐transistor (LTPS TFT) technology has made great progress, especially in the areas of excimer laser annealing (ELA) of high‐quality poly‐Si film, ion doping for large‐area doping, and high‐quality gate SiO2 film formation by using the low‐temperature PE‐CVD method. Also, technology trends and possible applications, such as a system displays, will be discussed.

Low temperature poly-Si TFT-LCD by excimer laser anneal

Excimer laser anneal (ELA) has allowed the production of large-area poly-Si thin-film transistor liquid crystal displays (TFT-LCDs) on a glass substrate. The state of the art of large-area low-temperature TFT-LCDs is reported in this paper. High-performance poly-Si TFTs are expected to achieve various applications such as system-on-glass where various functions are added on to the display. Possible applications and future trends are discussed together with the technologies required to achieve this goal.

Simple fabrication of offset-gated poly-Si TFTs by in situ fluorine passivation and excimer-laser doping

We have proposed a simple fabrication method of offset-gated polycrystalline silicon thin film transistors (poly-Si TFTs) by employing excimer-laser-induced in situ fluorine passivation and excimer-laser doping technique. In the proposed process, the crystallization and in situ fluorine passivation of active layer and the doping of source/drain region are performed simultaneously with only one excimer-laser annealing (ELA). Using phosphosilicate glass (PSG) films as a diffusion source, excimer-laser doping was accomplished successfully and the minimum sheet resistance was 500 Ω/□ for 5 pulses at 320 mJ/cm 2. The subthreshold and the on-state properties of devices with in situ fluorine passivation were improved compared to those without in situ fluorine passivation. The threshold voltage and the maximum transconductance for the device with in situ fluorine passivation were improved from 5.7 ± 0.4 V and 8.7 ± 1.1 μA/V to 4.3 ± 0.3 V and 12.8 ± 0.8 μA/V, respectively. Such an improvement is due to the fluorine passivation effects of trap states in poly-Si channel, offset region and SiO 2/poly-Si interface. Our experimental data show that the proposed method is effective to simply obtain the high performance poly-Si TFTs.