High-performance IP Research Articles

Design and implementation of dynamic balance in ultra-high speed IP network

Abstract Nowadays, with the rapid development of IP network service demand, network construction is also accelerating, IP network is expanding at a higher rate, and gradually moving toward ultra-high speed networks above 40G. In view of the problems of inconsistent IP packet order, random IP packet length and traffic burst brought by the application environment of high traffic, high bandwidth and high concurrency in ultra-high speed IP network, this paper introduces a kind of dynamic balance processing technology of ultra-high speed IP network based on information label. By optimizing the IP processing architecture, a two-level scheduling architecture of multi-board and multi-module is established, and VPN is established in ultra-high speed IP network by using dynamic balance processing technology and order preserving technology to realize high performance IP processing, so as to achieve ultra-high speed data transmission.

Spatio-temporal fragmentation-aware time-varying service provisioning in computing power networks based on model-assisted reinforcement learning

Widespread application of AI with high computing requirements has promoted the rapid development of cloud and edge computing. Ubiquitous computing resources need to be interconnected through high-performance IP and optical networks. Computing power networks (CPNs) have been studied as an IP/optical cross-layer architecture to provide on-demand computing services. The service provisioning in CPNs can be modeled as a virtual optical network embedding problem; however, the time-varying characteristics of service requirements increase the complexity. In particular, there can be stranded computing or bandwidth resources that are isolated in the spatio-temporal dimension and therefore difficult for other requests to utilize. This phenomenon is referred to as spatio-temporal resource fragmentation, which will lead to inefficient use of resources and higher energy consumption. To meet the time-varying requirements and achieve an energy-efficient CPN, in this paper, we first analyze the main reason for spatio-temporal resource fragmentation and excess energy consumption in cross-layer CPNs, which is the mismatched embedding scheme and the inappropriate scheduling order. Therefore, an auxiliary-graph-model-assisted edge-featured graph-attention-network-enabled DRL algorithm, DeepDefrag, is studied to solve the problem. Its core highlight is co-optimizing the scheduling and embedding of time-varying virtual networks along with the awareness of resource fragmentation. In addition, an integer linear programming algorithm is developed to determine the performance bounds. We validate DeepDefrag through a series of ablation studies and comparison algorithms under different numbers of requests. The results show that DeepDefrag can achieve >26.4% lower energy consumption for CPNs compared with the DRL-based baseline. Moreover, it is shown to generalize well across requests and networks.

Implementation and Verification of Steganography IP Core Based on HLS and OpenCV

Steganography is a safe transmission method that hides secret data in public information to avoid attacks as much as possible. However, the current steganography research and application mainly stay in the software stage. Although the secure transmission of data is realized, it is difficult to realize the purpose of high-speed data transmission. This thesis solves this problem with the help of a fully parallel, high-speed and high-bandwidth FPGA. This paper uses HLS to design a steganography IP core that can be applied to FPGA, and uses OpenCV to quickly and effectively verify the IP core. The final result proves that this paper successfully designed a high-performance IP core that can realize steganography, which effectively solves the problem of difficult high-speed transmission of encrypted data. This IP core combines the AXI bus protocol, which not only facilitates data interaction with DDR3 and other devices, but also conducive to the design and optimization of the complete secret data transmission system in the future.

High-performance IP lookup using Intel Xeon Phi: a Bloom filters based approach

IP lookup is a core operation in packet forwarding, which is implemented using a Longest Prefix Matching (LPM) algorithm to find the next hop for an input address. This work proposes and evaluates the use of parallel processors to deploy an optimized IP lookup algorithm based on Bloom filters. We target the implementation on the Intel Xeon Phi (Intel Phi) many-core coprocessor and on multi-core CPUs, and also evaluate the cooperative execution using both computing devices with several optimizations. The experimental evaluation shows that we were able to attain high IP lookup throughputs of up to 182.7 Mlps (Million packets per second) for IPv6 packets on a single Intel Phi. This performance indicates that the Intel Phi is a very promising platform for deployment of IP lookup. We also compared the Bloom filters to an efficient approach based on the Multi-Index Hybrid Trie (MIHT) in which the Bloom filters was up to 5.1 × faster. We also propose and evaluate the cooperative use of CPU and Intel Phi in the IP lookup, which resulted in an improvement of about 1.3 × as compared to the execution using only the Intel Phi.

Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode

Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode

Design of priority-based active queue management for a high-performance IP switch

Multimedia services such as IPTV and video conferencing constitute a substantial portion of the traffic sources in new communication systems requiring high-speed IP switching. This paper presents a scalable architecture for a high-performance IP switch based on Priority Active Queue Management (PAQM), which provides multimedia services with improved quality of service (QoS) in the communication system. Better QoS, in terms of delay, throughput, and loss rate, can be provided by a packet scheduling technique and a buffer management architecture for packet switching networks. The proposed architecture consists of a PAQM with a dedicated memory management data structure based on circular linked lists. The linked lists include different priority levels in a pipelined organization for the management of active queues. The architecture also scales dynamically to support a large number of priority levels and a large queue size. A performance analysis of an optimized PAQM algorithm is presented using an NS-2 network simulator to evaluate the capacity of the IP switch to support QoS. The results show that this system can achieve the maximum throughput with low levels of delay. To achieve high performance, we have implemented the proposed algorithm using 0.35-μm CMOS technology, the performance of which is subsequently analyzed.

Design of a Qos-Based Reconfigurable Priority Active Queue Management for IP Networks

This paper presents a reconfigurable and scalable architecture of a high-performance IP switch to improve network quality of service (QoS). Quality of services, in terms of delay, through-put and loss rate, can be provided by using a mechanism support like scheduling and buffer management architecture of packet switching IP networks. The proposed architecture consists of a new memory management data structure based on circular linked lists. The linked lists include different priorities levels with a pipelined organization for the reconfigurable priority active queues management. The ar- chitecture also scales dynamically to support a large number of priority levels and a large queue size. The new data structure enables us to configure the architecture based on network service domain. Detailed description of new data structures of the proposed algorithms and their corresponding implementations are presented as well.

Advanced hashing schemes for packet forwarding using set associative memory architectures

Building a high performance IP packet forwarding (PF) engine remains a challenge due to increasingly stringent throughput requirements and the growing size of IP forwarding tables. The router has to match the incoming packet’s IP address against all entries in the forwarding table. The matching process has to be done at increasingly higher wire speed; hence, scalability and low power consumption are critical for PF engines. Various hash table based schemes have been considered for use in PF engines. Set associative memory can be used for hardware implementations of hash tables with the property that each bucket of a hash table can be searched in a single memory cycle. However, the classic hashing downsides, such as collisions and worst case memory access time have to be dealt with. While open addressing hash tables, in general, provide good average case search performance, their memory utilization and worst case performance can degrade quickly due to collisions (that lead to bucket overflows). The two standard solutions to the overflow problem are either to use predefined probing (e.g., linear or quadratic probing) or to use multiple hash functions. This work presents two new simple hash schemes that extend both aforementioned solutions to tackle the overflow problem efficiently. The first scheme is a hash probing scheme that is called Content-based HAsh Probing (CHAP). As the name suggests, CHAP, based on the content of the hash table, avoids the classical side effects of predefined hash probing methods (i.e., primary and secondary clustering phenomena) and at the same time reduces the overflow. The second scheme, called Progressive Hashing (PH), is a general multiple hash scheme that reduces the overflow as well. The basic idea of PH is to split the prefixes into groups where each group is assigned one hash function, then reuse some hash functions in a progressive fashion to reduce the overflow. Both schemes are amenable to high-performance hardware implementations with low overflow and constant worst-case memory access time. We show by experimenting with real IP lookup tables and synthetic traces that both schemes outperform other existing hashing schemes.

Achieving O(1) IP lookup on GPU-based software routers

IP address lookup is a challenging problem due to the increasing routing table size, and higher line rate. This paper investigates a new way to build an efficient IP lookup scheme using graphics processor units(GPU). Our contribution here is to design a basic architecture for high-performance IP lookup engine with GPU, and to develop efficient algorithms for routing prefix operations such as lookup, deletion, insertion, and modification. In particular, the IP lookup scheme can achieve O (1) time complexity. Our experimental results on real-world route traces show promising 6x gains in IP lookup throughput.

Design of versatile academic infrastructure for multilayer network services

This paper describes the network design and configurations of the new Japanese academic infrastructure, called SINET3, which provides a rich variety of network services to more than 700 universities and research institutions. Since the start of full-scale operations in June 2007, the network has expanded its services to include multi-layer transfer services (IP, Ethernet, and layer-1), enriched virtual private network services (L3VPN, L2VPN, VPLS, and L1VPN), enhanced QoS services (packet-based and circuit-based), and brand-new layer-1 bandwidth-on-demand (BoD) services. This paper explains how the network provides these various network services on a single network platform by effectively configuring leading-edge networking components, such as high-performance IP routers, layer- 1 switches, and a BoD server. Evaluations of the network design and configurations confirmed that the networking functions were effectively coordinated. The procedures and techniques related to the configuration validation that covered all phases of the network design and construction are also presented.

FPGA technology for multi-axis control systems

The research presented in this article applies the newest Field-Programmable-Gate-Arrays to implement motor controller devices in accordance with the actual core-based design. The flexibility of the System-on-a-Programmable-Chips in motor multi-axis control systems enables the processing of the most intensive computation operations by hardware (PID IP cores) and the trajectory computation by software in the same device. In those systems, the trajectory generation software may run in powerful microprocessors embedded in the FPGA. In this paper, we present a high-performance PID IP core controller described in VHDL; the design flow that has been followed in its design and how the simulation and the PID constants tuning has been approached. The reusability of this module is demonstrated with the design of a 4 axis SoPC controller. Additionally, an experimental self-reconfigurable SoPC design using Run-Time-Reconfiguration is presented. In this case, the control IP core can be replaced dynamically by another module with another with different features.

Design of a High-Performance IP Switching Architecture

In this study we present the architecture for use in high-performance switching networks with support quality of service (QoS) guarantees. Quality of services guarantees in terms of delay, through-put and loss rate can be provided by using mechanism's support like scheduling and buffer management at switching architecture in packet switching networks. Our architecture is based on a new data structure for the scheduling and memories management which is the circular linked list and the pipeline for the active queues elements. In addition to being very fast, the architecture also scales very well to a large number of priority levels and to large queue size. We give a detailed description of the block that support QoS guarantees. However our proposed architecture is composed of three parts: input controller, backplane and output controller. And we give the corresponding algorithms and the corresponding implementation of this architecture.

High-performance IP forwarding with efficient routing-table update

There has been an extensive study in constructing the routing tables during the past few years. Although the existing works have certain advantages, those approaches either use complicated data structures which result in large storage requirement and high complexity for updating/building the forwarding table or they are not scalable to fit in Internet protocol version 6 (IPv6). In this work, we propose a fast forwarding-table construction algorithm. With the modified multiway search tree, we can further reduce the depth of the tree and eliminate the storage for pointers. It leads to reduce the FT size and shorten the routing-table lookup time. While considering the route flaps, the forwarding performance will degrade by only 3.1% with 4000 BGP updates per 30 s in the worst case. Moreover, it is simple enough to fulfill the need of the fast packet forwarding. An extension approach to solve the IPv6 routing lookup is also presented for the future deployment.

High-performance IP routing table lookup

Nowadays, the commonly used table lookup scheme for IP routing is based on the so-called classless interdomain routing (CIDR). With CIDR, routers must find out the best matching prefix (BMP) for IP packets forwarding, which complicates the IP lookup. Currently, this process is mainly done in software and several schemes have been proposed for hardware implementation. Since the IP lookup performance is a major design issue for the new generation routers, in this article we propose a fast IP address lookup scheme, which significantly reduces the forwarding table to fit into SRAM with very low cost. It can also be implemented in hardware using the pipeline technique. By using our proposed method, the required memory space can be 90–170 Kb less than the previous scheme and three memory accesses for a lookup in the worst case. When implemented in hardware pipeline architecture, our mechanism can achieve one routing lookup per memory access.

IP router architectures: an overview

AbstractIn the emerging environment of high performance IP networks, it is expected that local and campus area backbones, enterprise networks, and internet service providers (ISPs) will use multigigabit and terabit networking technologies where IP routers will be used not only to interconnect backbone segments but also to act as points of attachments to high performance wide area links. Special attention must be given to new powerful architectures for routers in order to play that demanding role. In this paper, we identify important trends in router design and outline some design issues facing the next generation of routers. It is also observed that the achievement of high throughput IP routers is possible if the critical tasks are identified and special purpose modules are properly tailored to perform them. Copyright © 2001 John Wiley & Sons, Ltd.

Multicast performance measurement on a high-performance IP backbone

This paper describes an approach to IP multicast performance measurement on the National Science Foundation's very-high-speed Backbone Network Service (vBNS). Using OC-12c ATM attached workstations that act as either multicast senders or receivers distributed throughout the vBNS backbone, we create arbitrary topologies, generate synthetic IP multicast traffic and measure loss encountered. We present packet loss results as a function of time and as a function of router hop count (distribution tree depth). We analyze the multicast join latency incurred and consider both raw results and results with the loss due to the initiation of multicast state removed. We then correlate these loss measurements to the multicast distribution tree where results show less correlation than expected. We attribute various factors including unbalanced non-binary distribution trees, loss on the receiver links and the individual characteristics of different wide area links as factors affecting the correlation.

Survey and taxonomy of IP address lookup algorithms

Due to the rapid growth of traffic in the Internet, backbone links of several gigabits per second are commonly deployed. To handle gigabit-per-second traffic rates, the backbone routers must be able to forward millions of packets per second on each of their ports. Fast IP address lookup in the routers, which uses the packet's destination address to determine for each packet the next hop, is therefore crucial to achieve the packet forwarding rates required. IP address lookup is difficult because it requires a longest matching prefix search. In the last couple of years, various algorithms for high-performance IP address lookup have been proposed. We present a survey of state-of-the-art IP address lookup algorithms and compare their performance in terms of lookup speed, scalability, and update overhead.

Multicast and multiprotocol support for ATM based Internets

Both the Internet Engineering Task Force (IETF) and ATM Forum are addressing the issue of building higher layer networks using ATM. The IETF's focus is on IP, while the ATM Forum has expanded its vision to include all common Network layer protocols. The task faced by both organizations is to develop solutions that will cause minimal interoperability problems, both for users and network architects. This paper focuses on the solutions coming out of the IETF's IP over ATM working group, including the author's proposal for flexible, high performance IP multicast over ATM. The emerging Next Hop Resolution Protocol from the IETF's Routing Over Large Cloud group is briefly examined, and its possible conflict with the ATM Forum's Multiprotocol Over ATM'work is also discussed. The author finishes by noting how current IETF work could support 'multiprotocol' networks.

An experimental active memory based I/O subsystem

We describe an I/O subsystem based on an active memory called SWIM, designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to communicate with a disk or a communication line through a backend port. The processing logic is specially designed to perform operations such as pointer dereferencing, memory indirection, searching and bounds checking efficiently. The I/O subsystem is built using an interconnected ensemble of such memory logic pairs. This allows a complex I/O task to be distributed between a large number of small memory processors each doing a sub-task, while still retaining a common locus of control for higher level functions. This enables more powerful, scalable and robust designs for storage and communications subsystems that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year. We present the application of SWIM to three network functions that we have currently implemented: a national phone database server, a high performance IP router, and a call screening agent.

Towards a Gigabit IP Router

In this paper we illustrate the application of SWIM's Active Storage Element (ASE) module in constructing high performance IP routers. The logic associated with each ASE is a wide-instruction-word micro-programmable engine, that has been specially designed to efficiently perform operations such as pointer dereferencing, memory indirection, bounds checking, and so forth. This makes it well suited to performing operations such as parsing of the IP header, routing table lookup, checksum computation and exception processing. Our results show that a single ASE running at 20 MHz can process 400,000 packets per second: well over that required to sustain a gigabit router. Multiple ASEs can be used in parallel to achieve even higher processing rates.