High Performance FFT Research Articles

High performance and resource efficient FFT processor based on CORDIC algorithm

Fast Fourier Transform is widely used in communication and signal processing. I propose an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm. By optimizing the intermediate data processing process and the first stage of pipelining, the architecture improves the system's computing speed and reduces the use of registers. I propose a multiplication scheme based on CORDIC and binary decomposition coding to realize complex number multiplication and constant multiplication and to eliminate the use of a multiplier. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

Design and analysis of high performance and low power FFT for DSP datapath using Vedic Multipliers

ABSTRACT Fast Fourier Transform is one of the most efficient methods of performing computation in Digital signal processing blocks. These computations are basically performed by the inherent floating-point multiplier units residing inside the butterfly units of any FFT. To optimise an FFT for higher efficiency and performance, it is inevitable to use highly efficient adder and multiplier units within the datapath architecture of a FFT processor. This work proposes high-performance FFT units designed using optimised Vedic multiplier units for DSP processor cores. Choice of Vedic multiplier decreases power and delay overheads of design which leads to production of an efficient FFT. A comparative analysis is presented for 24-bit Vedic multiplier using nine adder variants. A separate analysis of inherent adders is also done. Using the two best proposed Vedic multipliers, FFT units of 8, 16 and 64-point are designed respectively. The designed FFT units are compared for dynamic power, area and delay with existing designs and an analysis is presented. Power efficiency of nearly 25% and delay efficiency of around 50% is achieved with respect to the existing designs. The design is simulated on Virtex-7 FPGA using Verilog HDL.

Automatic Generation of High-Performance FFT Kernels on Arm and X86 CPUs

This article presents AutoFFT, a template-based code generation framework that can automatically generate high-performance FFT kernels for all natural-number radices. AutoFFT is based on the Cooley-Tukey FFT algorithm, which exploits the symmetric and periodic properties of the DFT matrix, as the outer parallelization framework. Because butterflies are the core operations of the Cooley-Tukey algorithm, we explore additional symmetric and periodic properties of the DFT matrix and formulate multiple optimized calculation templates to further reduce the number of floating-point operations for butterflies of arbitrary natural numbers. To fully exploit hardware resources, we encapsulate a series of optimizations in an assembly template optimizer. Given any DFT problem, AutoFFT automatically generates C FFT kernels using these calculation templates and converts them into efficient assembly kernels using the template optimizer. Through a series of experiments on Arm, Intel, and AMD processors, we show that AutoFFT-generated kernels can outperform those in Fastest Fourier Transform in the West (FFTW), the Arm Performance Libraries (ARMPL), and the Intel Math Kernel Library (MKL).

A high performance fast-Fourier-transform spectrum analyzer for measuring spin noise spectrums**Project supported by the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDC0702200), the National Key R&D Program of China (Grant Nos. 2018YFA0306600 and 2016YFB0501603), the National Natural Science Foundation of China (Grant No. 11927811), the Chinese Academy of Sciences (Grants Nos. GJJSTD20170001 and QYZDY-SSW-SLH004), Anhui

A high performance fast-Fourier-transform (FFT) spectrum analyzer, which is developed for measure spin noise spectrums, is presented in this paper. The analyzer is implemented with a field-programmable-gate-arrays (FPGA) chip for data and command management. An analog-to-digital-convertor chip is integrated for analog signal acquisition. In order to meet the various requirements of measuring different types of spin noise spectrums, multiple operating modes are designed and realized using the reprogrammable FPGA logic resources. The FFT function is fully managed by the programmable resource inside the FPGA chip. A 1 GSa/s sampling rate and a 100 percent data coverage ratio with non-dead-time are obtained. 30534 FFT spectrums can be acquired per second, and the spectrums can be on-board accumulated and averaged. Digital filters, multi-stage reconfigurable data reconstruction modules, and frequency down conversion modules are also implemented in the FPGA to provide flexible real-time data processing capacity, thus the noise floor and signals aliasing can be suppressed effectively. An efficiency comparison between the FPGA-based FFT spectrum analyzer and the software-based FFT is demonstrated, and the high performance FFT spectrum analyzer has a significant advantage in obtaining high resolution spin noise spectrums with enhanced efficiency.

Low power and high performance FFT with different radices

<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.</p>

Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

Two-dimensional discrete Fourier transform (DFT) is an extensively used and computationally intensive algorithm, with a plethora of applications. 2D images are, in general, nonperiodic but are assumed to be periodic while calculating their DFTs. This leads to cross-shaped artifacts in the frequency domain due to spectral leakage. These artifacts can have critical consequences if the DFTs are being used for further processing, specifically for biomedical applications. In this paper we present a novel FPGA-based solution to calculate 2D DFTs with simultaneous edge artifact removal for high-performance applications. Standard approaches for removing these artifacts, using apodization functions or mirroring, either involve removing critical frequencies or necessitate a surge in computation by significantly increasing the image size. We use a periodic plus smooth decomposition-based approach that was optimized to reduce DRAM access and to decrease 1D FFT invocations. 2D FFTs on FPGAs also suffer from the so-called “intermediate storage” or “memory wall” problem, which is due to limited on-chip memory, increasingly large image sizes, and strided column-wise external memory access. We propose a “tile-hopping” memory mapping scheme that significantly improves the bandwidth of the external memory for column-wise reads and can reduce the energy consumption up to 53%. We tested our proposed optimizations on a PXIe-based Xilinx Kintex 7 FPGA system communicating with a host PC, which gives us the advantage of further expanding the design for biomedical applications such as electron microscopy and tomography. We demonstrate that our proposed optimizations can lead to 2.8× reduced FPGA and DRAM energy consumption when calculating high-throughput 4096×4096 2D FFTs with simultaneous edge artifact removal. We also used our high-performance 2D FFT implementation to accelerate filtered back-projection for reconstructing tomographic data.

Low Cost CORDIC-Based Configurable FFT/IFFT Processor for OFDM Systems

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18μm technology, the core area of the processor is 3.47mm2 and the maximum operating frequency can be up to 500MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

Real-Time Implementation of Chirp Scaling Algorithm

Echo data generated by Synthetic aperture radar (SAR) has the characteristics of high data rate and huge data quantity. However, the complex Chirp Scaling (CS) algorithm in SAR processing leads to excessive calculations. To solve this problem, this paper presents an implementation on a parallel structure real-time image processing board, which adopts principal-subordinate parallel processing structures. The principal FPGA board is responsible for the control of the entire image processing, data collection, distribution and interaction. Each subordinate FPGA, as an independent processing unit, is able to independently finish the FFT transformation and phase factor compensation. The performance of the high-performance parallel FFT processors is 4 times as efficient as that of a single butterfly processor.The phase factor generation and compensation is optimized through two steps, one is fast algorithm in phase factor generation and compensation; the other is the optimization among the processing procedures,The proposed architecture can process an image in size16384 × 65536 at 100MHZ operation frequency within 12.5s.

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.

New datasheet on RF Engines'HyperSpeed range of high-performance FFT cores now available

New datasheet on RF Engines'HyperSpeed range of high-performance FFT cores now available

데이터 재구성 기법을 이용한 고성능 FFT

데이터 재구성 기법을 이용한 고성능 FFT

A High-Performance Microprocessor-Based FFT Processor

A high-performance FFT processor based on a microprogrammable microprocessor is described here. The system processes a 256-point complex transform in less than 5.3 ms and is capable of processing a variable length (4 to 256, radix-2) complex transform. The system uses fixed point arithmetic, and each complex piece of data consists of a 16-bit 2's complement real part and a 16-bit 2's complement imaginary part. The hardware consists of Intel 3000-bit-slice microprocessor, TRW's multiplier chip (MPY 16A-J), input and output RAM's, control PROM's, and some TTL logic.