High-performance 4H-SiC Research Articles

High-Performance 4H-SiC EUV Photodiode With Lateral p-n Junction Fabricated by Selective-Area Ion Implantation

High-Performance 4H-SiC EUV Photodiode With Lateral p-n Junction Fabricated by Selective-Area Ion Implantation

Accurate TCAD Simulation Model for High Performance 4H-SiC Alpha-particle Detectors

Accurate TCAD Simulation Model for High Performance 4H-SiC Alpha-particle Detectors

A novel high-performance junctionless 4H-SiC trench MOSFET with improved switching characteristics

A high-performance novel 4H-SiC trench power MOSFET employing the junctionless concept is proposed in this work. The presented design is modeled and investigated numerically by Devedit and Atlas TCAD tools, where the advantages of the junctionless concept are used to maximize the performance of the trench structure. This new structure helps lowering the input and reverse transfer capacitances of the trench power MOSFET compared to the conventional structures. The proposed device shows a lower high frequency (HF) Figure of Merits (FoM) value of 1078 mΩ.pF as compared to the conventional counterpart (4600 mΩ.pF), with a relative improvement of 76.5%. Moreover, a superior agreement between the breakdown voltage and the specific on-resistance has been revealed by a higher FoM (BV2/Ron = 2580 MV/mΩ.cm−2) in comparison to the conventional power MOSFET (860 MV/mΩ.cm−2). In addition, the proposed design proves to support a higher critical electric field at the gate edge (E = 3.93 MV/cm) in comparison to that of its conventional counterpart (E = 3.7 MV/cm). The substantial outcomes of this study pairing improvements in switching, blocking and conducting electrical performances, forcefully suggest this cost-effective design as a potential candidate in developing low-cost and high-performance 4H-SiC power MOSFETS.

4H-SiCδn-i-p Extreme Ultraviolet Detector With Gradient Doping-Induced Surface Junction

Extreme ultraviolet (EUV) detectors are key components required in many critical applications. In this work, a high-performance 4H-SiC <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta \text{n}$ </tex-math></inline-formula> -i-p EUV detector with gradient doping-induced surface junction is designed and fabricated. The detector demonstrates ultra-low leakage current and excellent photo-response uniformity across the ~6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> photo-sensitive area. Under photovoltaic operation mode, the detector exhibits high responsivity of 0.104 A/W and corresponding quantum efficiency of 960%@13.5 nm, which are close to the theoretical limit. Meanwhile, the equivalent noise power of the device under 0 V bias is determined to be <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.35\times {10}^{\text {-12}}$ </tex-math></inline-formula> W by 1/f noise test, proving that the device has a very low noise level and corresponding high detectivity. In addition, the high-temperature working capability and radiation-resistant performance of the EUV detector are preliminarily verified.

Demonstration of Picosecond 4H-SiC Diode Avalanche Shaper With Voltage Rise Rate of 11.14 kV/ns and Peak Power Density of 62 MW/cm$^2$

In this letter, for the first time, a high-performance picosecond 4H-SiC diode avalanche shaper (DAS) with a novel <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${p^+/p^-/n^+}$</tex-math></inline-formula> multilayer epitaxial structure is experimentally demonstrated and characterized. For fabrication of our 4H-SiC DAS, the multilayer epitaxial stacks have been designed in detail and grown using continuous multilayer epitaxial wafer growth. To excite the delayed avalanche breakdown (DAB) effect, the electric field profile in multilayer epitaxial stacks has been numerically simulated in detail to suppress the surface electric field crowding and premature breakdown during the overvoltage pulse applied. A 2.5-kV, 1-ns pulsed power generator is adopted to drive our fabricated SiC DAS, the output on a 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> load is 1860 V, 100 ps, lead a voltage rise rate of 11.14 kV/ns, and a peak power density of 62 MW/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> . Furthermore, the fabricated SiC DAS operates stably in multipulse mode at 1 MHz. To the best of our knowledge, this is the first experimental result reported for picosecond DAS based on the 4H-SiC. This article is significant for developing 4H-SiC-based ultrafast closing switches.

High performance 4H-SiC MOSFET with deep source trench

In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s figure of merit of DST-MOSFET improved by 9% and 104%, respectively, in comparison with those of UMOSFET; and by 37% and 64%, respectively, compared to those of DT-MOSFET. Additionally, the SPR reduced the gate-to-drain capacitance of the DST-MOSFET and improved the switching characteristics. Consequently, the total switching energy loss of the proposed DST-MOSFET reduced by 63% and 47% in comparison with those of the UMOSFET and DT-MOSFET, respectively.

Demonstration of High-Performance 4H-SiC MISIM Ultraviolet Photodetector With Operation Temperature of 550 °C and High Responsivity

In this article, a 4H-SiC metal-insulator-semiconductor-insulator-metal (MISIM) ultraviolet (UV) photodetector (PD) with a normal working temperature up to 550 &#x00B0;C, has been successfully fabricated and characterized for the first time. At 550 &#x00B0;C, the dark current of our fabricated MISIM remains at &#x007E;0.2 nA level and a record photo-to-dark current ratio (PDCR) of 62.7 is achieved at a reverse bias voltage of &#x2212;15 V. Under 275 nm illumination, high responsivity (R) of 0.23 and 0.54 A/W have been achieved at room temperature (RT) and 550 &#x00B0;C, respectively. To the best of our knowledge, this is the best result reported for high-temperature UV detectors based on the 4H-SiC. This work is significant for developing high-temperature 4H-SiC-based UV PDs.

Oxygen atom ordering on SiO2/4H-SiC {0001} polar interfaces formed by wet oxidation

In the processing of 4H-SiC MOSFET devices, it is crucial to optimize the condition of wet oxidation based on the wafer surface orientation to obtain excellent electronic properties. However, the mechanism of surface oxidation and the effect of surface polarity remain unclear. The atomic structures of SiO2/4H-SiC (0001) [Si-face] and (0001¯) [C-face] interfaces can be analyzed by aberration-corrected STEM and first-principles MD calculations. On the Si-face, interfacial O atoms on the amorphous SiO2 layer show clear atomic ordering with a rigid O-Si bridge structure across the SiO2/4H-SiC interface, involving a slow oxidation rate. The C-face can be rapidly oxidized, resulting in dangling bonds, bond bending, rough interface, and residual carbon in the SiO2. A key feature is the formation of a stable and flat oxidation front by O atom ordering and then the suppression of interface defects or residual C, which provides an approach for designing high-performance 4H-SiC MOSFET devices.

A High-Performance 4H-SiC JFET With Reverse Recovery Capability and Low Switching Loss

A novel high-performance 1700-V 4H-Silicon carbide (SiC) junction field-effect transistor (JFET) with reverse recovery capability and low switching loss is proposed in this article. As for the proposed 4H-SiC JFET, the gate region of the conventional 4H-SiC JFET is split into two segments, one of which is replaced by the source. A Schottky barrier diode (SBD) is integrated in the sidewall of the channel region, which greatly improves the performances of the 4H-SiC JFET. Compared with the conventional 4H-SiC JFET, the numerical simulation results show that the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON},\text{ sp}}$ </tex-math></inline-formula> ), gate–drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text{GD}}$ </tex-math></inline-formula> ), and gate–drain charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{\text{gd}}$ </tex-math></inline-formula> ) of the proposed 4H-SiC JFET are reduced by 25.57%, 99.96%, and 72.91%, respectively. The switching loss is reduced by about 91%, and the average gate drive power consumption is reduced by more than 36% while the frequency range is from 10 to 400 kHz. The results also demonstrate that the proposed device has good reverse recovery performance and reduces switching loss, compared with the current commercial SiC devices.

Single-Photon-Counting Performance of 4H-SiC Avalanche Photodiodes With a Wide-Range Incident Flux

In this letter, high-performance 4H-SiC ultraviolet (UV) single-photon avalanche diodes (SPADs) with a large diameter of $300~\mu \text{m}$ were designed and fabricated. For the first time, the influence of an incident UV photon flux on the single-photon-counting performance of 4H-SiC SPADs is investigated. With the UV photon flux increasing from ~100 photons/ $\text{s}\cdot \mu \text{m}^{2}$ to $2.3\times 10^{4}$ photons/ $\text{s}\cdot \mu \text{m}^{2}$ , the ratio of photon count rate (PCR) to dark count rate (DCR) exhibits a non-monotonic variation while the single-photon detection efficiency (SPDE) is monotonically decreased. A maximum SPDE of 9.8% with a DCR of 10 Hz/ $\mu \text{m}^{2}$ is obtained for our large-area 4H-SiC SPAD with a photon flux of 209 photons/ $\text{s}\cdot \mu \text{m}^{2}$ at the wavelength of 280 nm. In addition, the stability of our 4H-SiC SPAD is also preliminarily proved by the high-temperature storage test at 150 °C for more than 200 hours in N2 ambient, which indicates the potential capability of our 4H-SiC SPADs to operate in harsh environment for UV single-photon detection.

Experimental Study of High Performance 4H-SiC Floating Junction JBS Diodes

This paper reports the demonstration of a high performance 4H-SiC floating junction junction barrier Schottky (FJ_JBS) rectifier with a 30μm, 6×10 15 cm -3 -doped epitaxial layer. Extensive simulations have been performed to design, optimize and analyze the structure of the FJ_JBS rectifier. The fabricated FJ_JBS shows that breakdown voltage (BV) and differential R on,sp are 3.4 kV, yielding the highest BV value reported for 4H-SiC FJ diodes, and 5.67 mΩ·cm 2 , respectively. Compared with the conventional JBS, the BV value of FJ_JBS increases by 33.3% and the R on,sp only slightly rises by 6.2%. The corresponding Baliga figure-of-merit (BFOM) (4 BV 2 /R on_sp ) of this FJ_JBS diode is 8.16 GW/cm 2 .

Design and fabrication of high performance 4H-SiC TJBS diodes

Abstract In this paper, high performance 4H-SiC trench junction barrier Schottky diodes (TJBS) have been successfully designed and fabricated. For making a larger design window that enables good reverse blocking and forward conduction capabilities at the same time in TJBS, trench profile, especially bevel angle (θ) of a tapered trench sidewall, are further studied. The optimal design is verified by the experimental results measured from the fabricated 4H-SiC JBS and TJBS diodes. Experimental results show that the reverse leakage current (Ir) of the TJBS is only 1.62 × 10−7 A/cm2 at Vr of 1200 V, which is about one order of magnitude less than that of planar JBS (PJBS) fabricated at the same time. The figure of merit (FOM) of TJBS is improved by 56.3% when compared with that of the PJBS.

Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO2/Al2O3Gate-Stack

High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm2/ $\text{V}\,\cdot $ s, and a peak field effect mobility of 154 cm2/V s, in 2- $\mu $ m gate length MOSFETs. The gate-stack was designed to minimize interface states and comprised a 0.7-nm thermally grown SiO2 on 4H-SiC, followed by Al2O3 and a metal gate contact. In this way, carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range of $6 \times 10^{11} - 5 \times 10^{10}$ cm−2eV−1 is also obtained. Temperature-dependent electrical data reveal that the high mobility results from conduction being phonon-limited, rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in the Si devices. Expressions for electric field-dependent contributions to mobility are presented. A steep subthreshold slope of 127 mV/decade indicates low electrical defect density. A temperature coefficient of −4.6 mV/K in threshold voltage is similar to that in the Si MOSFETs.

High-performance 4H-SiC p-i-n ultraviolet avalanche photodiodes with large active area

Ultraviolet (UV) detectors with large photosensitive areas are more advantageous in low-level UV detection applications. In this Letter, high-performance 4H-SiC p-i-n avalanche photodiodes (APDs) with large active area (800 μm diameter) are reported. With the optimized epitaxial structure and device fabrication process, a high multiplication gain of 1.4 × 106 is obtained for the devices at room temperature, and the dark current is as low as ∼10 pA at low reverse voltages. In addition, record external quantum efficiency of 85.5% at 274 nm is achieved, which is the highest value for the reported SiC APDs. Furthermore, the rejection ratio of UV to visible light reaches about 104. The excellent performance of our devices indicates a tremendous improvement for large-area SiC APD-based UV detectors. Finally, the UV imaging performance of our fabricated 4H-SiC p-i-n APDs is also demonstrated for system-level applications.

Large-Area 4H-SiC Ultraviolet Avalanche Photodiodes Based on Variable-Temperature Reflow Technique

In this letter, we report high-performance 4H-SiC separated absorption charge multiplication ultraviolet (UV) avalanche photodiodes (APDs) with a large active area (800- $\mu \text{m}$ diameter). For the first time, a variable-temperature photoresist reflow technique is presented to obtain very smooth sidewalls for positive beveled mesa, which is very useful for suppressing the reverse leakage and premature edge breakdown. At room temperature, the dark current of our fabricated large-area APD remains at ~1-pA level (0.2 nA/cm2) at low reverse bias voltage, and a high multiplication gain of over 106 is achieved. The peak responsivity at the wavelength of 274 nm reaches 0.18 A/W, corresponding to a maximum external quantum efficiency of 81.5% at unity gain. Moreover, an excellent UV/visible rejection ratio of more than 103 is obtained. To the best of our knowledge, this is the best result reported for visible-blind UV detectors based on the large-area 4H-SiC APDs.

4H-SiC SACM Avalanche Photodiode With Low Breakdown Voltage and High UV Detection Efficiency

In this paper, a high-performance 4H-SiC separated absorption charge multiplication ultraviolet avalanche photodiode (APD) with low breakdown voltage is designed and fabricated. The room temperature dark current of the APD remains at ∼0.1 pA level ( $\rm{\sim}29\;\text{pA/ cm}^{- 2}$ ) when reverse bias is below 50 V and then rises by several orders of magnitude before avalanche breakdown occurs. An avalanche gain up to 106 is achieved at 67 V. Based on secondary ion mass spectroscopy measurement, the electric field distribution within the as-fabricated APD is numerically simulated. The ionization ratio of Al in the p-type charge control layer is estimated to be 40%. The frequency dispersion phenomenon in capacitance–voltage (C-V) measurement should be caused by structural defects existing within the APDs, which may also be the source of the enhanced dark current before avalanche breakdown. The room-temperature maximum quantum efficiency is ∼80% at 270 nm with an ultraviolet (UV)/visible rejection ratio more than 10 4.

High-Performance 4H-SiC p-i-n Ultraviolet Photodiode With p Layer Formed by Al Implantation

In this letter, a high-performance 4H-SiC p-i-n ultraviolet (UV) photodiode (PD) with its p layer formed by Al implantation is designed and fabricated. The dark current density of the PD remains lower than 1 nA/cm2 at −100 V in the entire temperature range from room temperature (RT) up to 175 °C. The RT maximum external quantum efficiency of the PD under 0 V bias is 44.4% at 270 nm with a UV/visible rejection ratio larger than $10^{4}$ . The photoresponse characteristics of the PD are studied as the functions of reverse bias and temperature, which suggest that the device is advantageous to detect UV signals in high-temperature harsh environment. Compared with a 4H-SiC p-i-n PD formed entirely by epitaxial growth, the PD formed by Al implantation exhibits larger frequency dispersion in capacitance–voltage measurement, which should be caused by residual structural defects introduced during the ion implantation process.

Modeling of High Performance 4H-SiC Emitter Coupled Logic Circuits

SiC, a wide band gap semiconductor, is capable of robust operation at temperatures well above 600°C. SiC bipolar transistors are well suited for applications at high temperatures as, unlike MOSFET, it does not have a critical gate oxide, and hence oxide reliability at high temperatures is not an issue. In this paper, the design of optimized emitter coupled logic technology circuits using 4H-SiC bipolar transistors is presented. The circuits work over a wide range of temperatures and power supply voltages at high speeds, demonstrating the potential of robust high speed ECL integrated circuits in SiC for small-scale logic applications.

High-performance 4H-SiC junction barrier Schottky diodes with double resistive termination extensions

4H-SiC junction barrier Schottky (JBS) diodes with a high-temperature annealed resistive termination extension (HARTE) are designed, fabricated and characterized in this work. The differential specific on-state resistance of the device is as low as 3.64 mΩ·cm2 with a total active area of 2.46 × 10−3 cm2. Ti is the Schottky contact metal with a Schottky barrier height of 1.08 V and a low onset voltage of 0.7 V. The ideality factor is calculated to be 1.06. Al implantation annealing is performed at 1250°C in Ar, while good reverse characteristics are achieved. The maximum breakdown voltage is 1000 V with a leakage current of 9 × 10−5 A on chip level. These experimental results show good consistence with the simulation results and demonstrate that high-performance 4H-SiC JBS diodes can be obtained based on the double HARTE structure.

Investigation of Oxide Films Prepared by Direct Oxidation of C-Face 4H-SiC in Nitric Oxide

Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.