Small, lightweight mobile devices are the beneficiaries of fabrication miniaturization that follow Moore’s law predictions, advances in complex integration concepts, and wireless technology. Successful implementations have therefore stimulated unprecedented growth in mobile applications. Within these miniaturized devices, contact electrodes with small form factors in some applications are needed but unfortunately present many challenges and can lead to unwanted parasitic effects. Identifying ways to meet this need without introducing parasitic effects is essential to minimize signal distortion and loss in integrated circuits. The plethora of applications, however, produce large number of users and also generate extremely large amounts of data that require higher data rates. Higher frequency designs satisfy bandwidth requirements and maintain miniature size; unfortunately, this comes at a cost. When operating frequencies increase, available power decreases due to transistor technology limitations and the corresponding shrinkage in circuit size results in higher resistance leading to more power consumption. To address this conundrum, approaches are needed that allow losses to much be managed, and ideally reduced to achieve the desired performance requirements.This talk will present the investigation of copper nanowire (CuNW) technology for use in millimeter wave regime (30 GHz to 300 GHz) interconnect design in silicon integrated circuits. The parallel nature of nanowires to behave like bundles offers the potential to minimize loss and parasitic effects at millimeter wave frequencies. Co-integration of CuNW into coplanar waveguide (CPW) interconnect configurations that are single and multi-layer architectures will be discussed. Two types of interconnects are studied: vertical via and CuNW integrated into CPW lines. The findings from the study of these structures will include a discussion on the fabrication and characterization methods used for each technology followed by the loss performance results observed for the different types of designs.At 40 and 60 GHz, vertical CuNW via loss values of 0.095 dB and 0.149 dB was observed, respectively. These responses were lower than those of other via technologies and comparable to those in anodized aluminum substrates. Thus, they were favorable and indicate that CuNW can be used in a co-integrate manner to incorporate small contact features into designs that can maintain or reduce loss in the millimeter wave regime. CuNWs integrated CPW interconnects can also be used as a transmission line. In this case, loss responses, observed in the millimeter wave regime, can be reduced. In one design, loss values of 0.48 dB/mm and 0.59 dB/mm at 90 and 180 GHz, respectively, were determined, suggesting that conductor loss can be reduced in upper millimeter regime. At these frequencies, higher order mode suppression is essential to minimize unwanted substrate losses. Another design, however, improved losses in the low RF and microwave frequency regime, suggesting that low frequency designs can also experience conductor loss reduction. The conclusion thus far is that CuNW co-integration into CPW lines show promise for improving the performance of interconnect design across the RF to millimeter-wave spectrum when designed carefully.
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May 16, 2024
Lena Engel + 4
Open Access
