Higher Order Bits Research Articles

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

We present a voltage-scalable and process-variation resilient, hybrid memory architecture, suitable for use in MPEG-4 video processors such that power dissipation can be traded for graceful degradation in “quality.” The key innovation in our proposed work is a hybrid memory array, which is a mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that the human visual system is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show that under iso-area condition, we can obtain at least 32% power savings in the hybrid memory array compared to the conventional 6T SRAM array.

Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications

This paper presents a dynamically reconfigurable SRAM array for low-power mobile multimedia application. The proposed structure use a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits. The architecture allows reconfigure the number of bits in the low-voltage mode to change the error characteristics of the array in run-time. Simulations in predictive 70 nm nodes show that the proposed array can obtain 45% savings in memory power with a marginal (~10%) reduction in image quality.

REDUCING THE ENERGY DISSIPATION OF THE ISSUE QUEUE BY EXPLOITING NARROW IMMEDIATE OPERANDS

In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating component due its complex scheduling logic. In addition to the energy dissipated for scheduling activities, read and write lines of the issue queue entries are also high energy consuming pieces of the issue queue. When these lines are used for reading and writing unnecessary information bits, such as the immediate operand part of an instruction that does not use the immediate field or the insignificant higher order bits of an immediate operand that are in fact not needed, significant amount of energy is wasted. In this paper, we propose two techniques to reduce the energy dissipation of the issue queue by exploiting the immediate operand files of the stored instructions: firstly by storing immediate operands in separate immediate operand files rather than storing them inside the issue queue entries and secondly by issue queue partitioning based on widths of immediate operands of instructions. We present our performance results and energy savings using a cycle accurate simulator and testing the design with SPEC2K benchmarks and 90 nm CMOS (UMC) technology.

An ASIC implementation of a low power robust invisible watermarking processor

Digital watermarking is the process of embedding data called watermark into a multimedia object so that it can be detected or extracted later to make an assertion about the object. Several software implementations of watermarking algorithms are available, but very few attempts have been made for hardware implementation. The objective of this research paper is to implement ''low power robust invisible binary image watermarking processor'' in an Application Specific Integrated Circuit (ASIC) using Hardware Description Language (HDL). An 8-bit processor has been used since it consumes less power than other higher order bit (16-bit, 32-bit, etc.) processors. The proposed invisible watermarking algorithm is implemented in spatial domain. The proposed algorithm is prototyped (i) using XILINX FPGA (ii) using ASIC. To the best of our knowledge this is the first low power binary image watermarking processor implemented in ASIC which uses 8-bit processor with no limitation on input size. The algorithm is tested in Virtex E (xcv50e-8-cs144) Field Programmable Gate Arrays (FPGA) and implemented in an ASIC.

Reducing Soft Errors through Operand Width Aware Policies

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. As a faster but less fault tolerant alternative to ECC and parity, we offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of different data-holding components of a processor. On average, techniques that make use of the narrowness of the values can provide 49 percent error detection, 45 percent error correction, or 27 percent error avoidance coverage for single bit upsets in the first level data cache across all Spec2K. In other structures such as the immediate field of the issue queue, an average error detection rate of 64 percent is achieved.

An Iterative Fusion Technique for Dynamic Side Information Refinement in Pixel Domain Distributed Video Coding

Distributed video coding (DVC) technology has been considered to be capable of reducing the processing complexity of the encoder immensely, while majority of the computational overheads are taken over by the decoder. In the common DVC framework, the pictures are decoded using the Wyner-Ziv encoded bit stream received from the encoder and the side information estimated using previously decoded information. As a result, accuracy of the side information estimation is very critical in improving the coding efficiency. In this paper we propose a novel side information refinement technique for DVC using multiple side information streams and sequential motion compensation with luminance and chrominance information involving iterative fusion of parallel information streams. In the bit plane wise coding architecture, previously decoded higher order bit planes are incrementally used to perform the motion estimation jointly in luminance and chrominance spaces to estimate multiple redundant bit streams for iterative fusion to produce more improved side information for subsequent bit planes. Simulation results show significant objective quality gain can be achieved at the same bit rate by utilizing the proposed refinement algorithms.

Factorization of Square-Free Integers with High Bits Known

In this paper we propose an algorithm of factoring any integer N which has k different prime factors with the same bit-length, when about (1/k+2+ε/k-1)log2N high-order bits of each prime factor are given. For a fixed ε, the running time of our algorithm is heuristic polynomial in (log2N). Our factoring algorithm is based on a lattice-based algorithm of solving any k-variate polynomial equation over Z, which might be an independent interest.

The Vanstone-Zuccherato Schemes Revisited

In 1995, Vanstone and Zuccherato proposed a novel method of generating RSA moduli having a predetermined set of bits which are the ASCII representation of user's identification information (i.e., name, email address, etc.). This could lead to a savings in bandwidth for data transmission and storage. In this paper, we apply this idea of Vanstone and Zuccherato for reducing the storage requirement of RSA public moduli to integer factoring based public-key schemes with their moduli of the form prq. More precisely, we explicitly propose two efficient methods for specifying high-order bits of prime factors of their public-keys. We also consider the security of the proposed methods.

Inferring sequences produced by a linear congruential generator on elliptic curves missing high-order bits

Let p be a prime and let be an elliptic curve defined over the finite field of p elements. For a given point the linear congruential genarator on elliptic curves (EC-LCG) is a sequence (Un) of pseudorandom numbers defined by the relation: where denote the group operation in and is the initial value or seed. We show that if G and sufficiently many of the most significants bits of two consecutive values U n, Un+1 of the EC-LCG are given, one can recover the seed U0 (even in the case where the elliptic curve is private) provided that the former value U n does not lie in a certain small subset of exceptional values. We also estimate limits of a heuristic approach for the case where G is also unknown. This suggests that for cryptographic applications EC-LCG should be used with great care. Our results are somewhat similar to those known for the linear and non-linear pseudorandom number congruential generator.

Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design

Energy-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Because of the encoding format and operating sequence, dual-rail encoding circuits do not naturally energy aware to the changing of input precisions. A novel technique named Zero Insertion for designing energy-aware arithmetic circuits in dual-rail encoding logic is developed. By using Null to replace the redundant Data 0’s in high order bits, the designed circuits have significant energy savings as well as latency reduction at different input precisions while maintaining speed-independency. Parallel adders, multipliers, and a rank-order filter, have been designed and simulated to demonstrate the effectiveness of this technique. The overhead and additional costs in the control circuit are also discussed.

Exploiting Narrow Values for Soft Error Tolerance

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors In a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors canted by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. We offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of level-1 data cache of the processor

Spectral prefetcher

Effective data prefetching requires accurate mechanisms to predict embedded patterns in the miss reference behavior. This paper proposes a novel prefetching mechanism, called the spectral prefetcher (SP), that accurately identifies the pattern by dynamically adjusting to its frequency. The proposed mechanism divides the memory address space into tag concentration zones (TCzones) and detects either the pattern of tags (higher order bits) or the pattern of strides (differences between consecutive tags) within each TCzone. The prefetcher dynamically determines whether the pattern of tags or strides will increase the effectiveness of prefetching and switches accordingly. To measure the performance of our scheme, we use a cycle-accurate aggressive out-of-order simulator that models bus occupancy, bus protocol, and limited bandwidth. Our experimental results show performance improvement of 1.59, on average, and at best 2.10 for the memory-intensive benchmarks we studied. Further, we show that SP outperforms the previously proposed scheme, with twice the size of SP, by 39% and a larger L2 cache, with equivalent storage area by 31%.

The shortest vectors of lattices connected with a linear congruent generator

Let ε > 0 be a fixed real number, ⊂ R s be a full rank lattice with determinant Δ ∈ Q . We call this lattice ε -regular if λ 1 () > Δ 1/ s ( h (Δ)) – ε , where λ 1 () is the length of the shortest nonzero vector of and h (Δ) is the maximum of absolute values of the numerator and the denominator of the irreducible rational fraction for Δ. In this paper, we consider two full rank lattices in the space R s : the lattice ℒ( a , W ) connected with the linear congruent sequence ( x N ), x N +1 = ax N (mod W ), N =1 ,2, . . . , (1) and the lattice ℒ ∗ ( a , W ) dual to ℒ( a , W ). There is a conjecture which states that for any natural number s , any real number 0 < ε < ε 0 ( s ), and any natural number W > W 0 ( s , ε ), the lattices ℒ( a , W ) and ℒ ∗ ( a , W ) are ε -regular for all a = 0 ,1, . . . , W – 1 excluding some set of numbers a of cardinality at most W 1– ε . In the case s = 3, A. M. Frieze, J. Hestad, R. Kannan, J. C. Lagarias, and A. Shamir in a paper published in 1988 proved a more weak assertion (in their estimate the number of exceptional values a is at most W 1– ε /2 ). Using the methods of this paper, it is not difficult to prove the conjecture for s = 1 and s = 2. In our paper, we prove the conjecture for s = 4. With the help of our methods we improve the result of the paper mentioned above and prove the conjecture for s = 3. Our result can be applied to the reconstruction of a linear congruent sequence (1) if the high-order bits of its first s elements are given.

Area Allocation Strategies for Enhancing Yield of R -2 R Ladders

A new strategy for allocating area, at layout, for enhancing the soft yield of R-2R ladders is introduced. In contrast to the conventional and convenient approach of allocating equal area to each R/2R bit-slice, the new strategy allocates progressively larger areas to higher-order bits. With this strategy, the INL yield for a fixed total resistor area as determined by local random variations in the sheet resistance is optimized. Simulation results show that the new area allocation strategy provides significant improvements in INL yield compared to what is achievable with the conventional area allocation strategy.

Theoretical analysis of word-level switching activity in the presence of glitching and correlation

This paper presents a novel analytical approach to compute the switching activity in digital circuits at the word level in the presence of glitching and correlation. The proposed approach makes use of signal statistics such as mean, variance, and autocorrelation. It is shown that the switching activity /spl alpha//sub f/ at the output node f of any arbitrary circuit in the presence of glitching and correlation is computed as /spl alpha//sub f/=/spl Sigma//sub i=1//sup S-1//spl alpha/(f/sub i,i+1/)=/spl Sigma//sub i=1//sup S-/ /sup 1/p(f/sub i+1/)(1-p(f/sub i/))(1-/spl rho/(f/sub i,i+1/)) (1) where /spl rho/(f/sub i,i+1/)=/spl rho/(f/sub i,i+1/)=(E[f/sub i/(Sn)f/sub i+1/(Sn)]- p(f/sub i/)p(f/sub i+1/))/(/spl radic/(p(f/sub i/)-p(f/sub i/)/sup 2/)(p(f/sub i+1/)- p(f/sub i+1//sup 2/))) (2). S number of time slots in a cycle; /spl rho/(f/sub i/,+1) time-slot autocorrelation coefficient; E[x]=expected value of x; p/sub x/=probability of the signal x being one. The switching activity analysis of a signal at the word level is computed by summing the activities of all the individual bits constituting the signal. It is also shown that if the correlation coefficient of the higher order bits of a normally distributed signal x is /spl rho/(x/sub c/), then the bit P/sub 0/ where the correlation begins and the correlation coefficient is related hy /spl rho/(x/sub c/)=erfc{(2(P/sub 0/-1)-1)/(/spl radic/2/spl sigma//sub x/)} where erfc(x)=complementary error function; /spl sigma//sub x/=variance of x. The proposed approach can estimate the switching activity in less than a second which is orders of magnitude faster than simulation-based approaches. Simulation results show that the errors using the proposed approach are about 6.1% on an average and that the approach is well suited even for highly correlated speech and music signals.

Asynchronous analogue-to-digital converter for single-electroncircuits

An analogue-to-digital conversion scheme based on the e-periodic transfer characteristics of an SET inverter is proposed. The authors demonstrate the 4 bit analogue-to-digital converter performance using Monte-Carlo simulation in which an SET inverter implements a binary quantiser and encoder for one significant bit. This scheme can be easily extended to higher order bits.

Voice encoding method and voice decoding method

A compressed digital speech signal is encoded to provide a transmission error-resistant transmission signal. The compressed speech signal is derived from a digital speech signal by performing a pitch search on a block obtained by dividing the speech signal in time to provide pitch information for the block. The block of the speech signal is orthogonally transformed to provide spectral data, which is divided by frequency into plural bands in response to the pitch information. A voiced/unvoiced sound discrimination generates voiced/-unvoiced (V/UV) information indicating whether the spectral data in each of the plural bands represents a voiced or an unvoiced sound. The spectral data in the plural bands are interpolated to provide spectral amplitudes for a predetermined number of bands, independent of the pitch. Hierarchical vector quantizing is applied to the spectral amplitudes to generate upper-layer indices, representing an overview of the spectral amplitudes, and lower-layer indices, representing details of the spectral amplitudes. CRC error detection coding is applied to the upper-layer indices, the pitch information, and the V/UV information to generate CRC codes. Convolution coding for error correction is applied to the upper-layer indices, the higher-order bits of the lower-layer indices, the pitch information, the V/UV information, and the CRC codes. The convolution-coded quantities from two blocks of the speech signal are then interleaved in a frame of the transmission signal, together with the lower-order bits of the respective lower-layer indices.

Distributed directory tags

This paper concerns a new directory scheme that can be used as an alternative to the current three types of directory schemes; direct mapped, set associative and fully associative. Both direct mapped and fully associative cache directories can be considered as a special case of the set associative directory since in the direct mapped case there are N congruent classes with a set size of 1 while in the fully associative case there are N sets and only 1 congruent class. However, irrespective of which class of directory scheme is used, since memory or cache directories generally provide a many-to-one mapping of a large address space to a small fast storage, a tag field must be associated with each element to identify one of the many addresses which actually map to the current value in the cache element. Thus, there are as many tags as there are total elements in the directory. The Distributed Directory Tag scheme described here uses the direct mapping of the addresses and distribution of the tags over the directory elements and thereby reduces the storage requirement for the directory tags by a significant factor. Our early findings indicate that addresses from application programs follow a particular distribution, with a strong bias towards less frequent change in the higher order bits. It is this observation that is exploited in the scheme described in this paper. The actual savings depend on the particular distribution chosen for an implementation, but in general, a factor of three reduction can be obtained while providing a hit ratio comparable to the other directory schemes. This savings in the tag bits is achieved while still providing set associativity within each congruent class. This scheme is particularly useful when cost/performance tradeoffs are a consideration. Thus, this novel directory design adds another type to the three existing cache directory schemes.

A high speed mechanism for short branches

A semi-absolute branch instruction supplies the low-order bits of the destination address, or an offset into a frame, while the high-order bits the destination address, or frame number, are derived from the current frame number. The branch mechanism proposed here compares a small number of the most significant bits of a current and destination frame offsets followed by a possible increment or decrement of the current frame number, allowing branches to be effected more rapidly, for a given hardware cost, than by adding an offset to the instruction pointer. The increment can be performed upon branching or prior to it in order to hide the latency of the increment operation. If, for example, the three most significant bits of the frame offsets are compared the overall branch range is reduced to 94% of the range of conventional relative branches. This technique over comes the branch range restriction that occurs when the instruction pointer points to near a frame boundary and the destination address is generated by a simple bit-field substitution.

Reconstructing Truncated Integer Variables Satisfying Linear Congruences

We propose a general polynomial time algorithm to find small integer solutions to systems of linear congruences. We use this algorithm to obtain two polynomial time algorithms for reconstructing the values of variables $x_1 , \cdots ,x_k $ when we are given some linear congruences relating them together with some bits obtained by truncating the binary expansions of the variables. The first algorithm reconstructs the variables when either the high order bits or the low order bits of the $x_i $ are known. It is essentially optimal in its use of information in the sense that it will solve most problems almost as soon as the variables become uniquely determined by their constraints. The second algorithm reconstructs the variables when an arbitrary window of consecutive bits of the variables is known. This algorithm will solve most problems when twice as much information as that necessary to uniquely determine the variables is available. Two cryptanalytic applications of the algorithms are given: predicting linear congruential generators whose outputs are truncated and breaking the simplest version of Blum’s protocol for exchanging secrets.