high-NA EUV Lithography Research Articles

Fast source mask co-optimization method for high-NA EUV lithography

Fast source mask co-optimization method for high-NA EUV lithography

Chemically amplified resist CDSEM metrology exploration for high NA EUV lithography

Background: The chemically amplified resist (CAR) has been the workhorse of lithography for the past few decades. During the evolution of projection lithography to extreme ultraviolet lithography (EUVL), a continuous reduction in feature size is observed. Also, a reduction in resist film thickness (FT) is required to prevent large aspect ratios that lead to pattern collapse. A further reduction in resist FT, into an ultrathin film regime (<30 nm resist FT), is expected when advancing to high NA EUVL. This brings along associated challenges with (1) resist critical dimension scanning electron microscope (CDSEM) metrology and (2) resist patterning performance. Aim: Assessment of metrology challenges and patterning limits of a CAR working in this ultrathin film regime. Deconvoluting the metrology and patterning effect on the determination of the unbiased line width roughness (uLWR). Approach: Patterning a CAR at different nominal resist FTs on two different underlayers to quantify the changes in CDSEM image quality and resist patterning performance with the resulting uLWR changes. Results: The CDSEM image signal-to-noise ratio (SNR) depends on resist FT and the underlayer. The uLWR increases with a reduction in resist FT but scales differently on the two underlayers. Conclusions: A relationship between CDSEM image SNR and uLWR is found. The SNR and uLWR scaling difference on the two underlayers, as well as the uLWR dependency on SNR was determined to be a metrology effect. The general uLWR increase for a reduced resist FT was determined to be a patterning effect.

Contribution of mask defectivity in stochastics of EUVL-based wafer printing

Two earlier publications showed that mask defectivity contributes to the stochastics of the EUVL-printed image on wafer. The present contribution gives more insights into the methodology and resist models used therein. In addition, an extended study of two types of mask roughness is presented, comprising mask absorber line-edge roughness and rippling of the multilayer mirror on the mask. For both, it is shown that contributions to stochastics are larger than expected purely from normalized intensity log-slope considerations. As a second topic, printability of local defects is readdressed at smaller pitches and more state-of-the-art illumination settings, in preparation to a genuine study of mask defectivity contribution to wafer printing stochastics at high-NA EUV lithography. First results for one-dimensional mask patterns indicate an influence of the anamorphic characteristic of high-NA imaging, showing a different behavior for vertical and horizontal orientations.

고 개구수 극자외선 노광 기술용 위상 변위 흡수체 구조의 설계

고 개구수 극자외선 노광 기술용 위상 변위 흡수체 구조의 설계

Waveguide effect in high-NA EUV lithography: The key to extending EUV lithography to the 4-nm node

One of the main concerns about EUV lithography is whether or not it can be extended to very high numerical aperture. In this paper, rigorous electromagnetic simulation is first used to show that there is an interesting waveguide effect occurring in the 4-nm feature size regime. An exact mathematical analysis is then presented to explain the effect observed in the simulation. This waveguide effect is applied to simulate the printing of 4-nm lines and spaces with excellent aerial-image contrast and peak intensity. The feasibility of EUV lithography for printing logic circuits containing general two-dimensional patterns with 4-nm feature size is also demonstrated.

Challenges of 22 nm and beyond CMOS technology

It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

Effect of PAG Distribution on ArF and EUV Resist Performance

High NA immersion and EUV lithography processes are challenged to meet stringent control requirements for the 22nm node and beyond. Lithography processes must balance resolution, LWR and sensitivity (RLS) performance tradeoffs while scaling resist thickness to 100nm and below. Hardware modules including coat, bake and development seek to enable resist processes to balance RLS limitations. The focus of this paper is to study the fundamentals of the RLS performance tradeoffs through a combination of calibrated resist simulations and experiments. This work seeks to extend the RLS learning through the creation of calibrated resist models that capture the exposure kinetics, acid diffusion properties, deprotection kinetics and dissolution response as a function of PAG loading in a 193nm polymer system. The calibrated resist models are used to quantify the resolution and sensitivity performance tradeoffs as well as the degradation of resist contrast relative to image contrast at small dimensions. Calibrated resist simulations are capable of quantifying resolution and sensitivity tradeoffs, but lack the ability to model LWR. LWR is challenging to simulate (lattice models) and to measure due to the dependence on spectral frequency.