High-k Metal Oxide Research Articles

Application of Solution-Processed High-Entropy Metal Oxide Dielectric Layers with High Dielectric Constant and Wide Bandgap in Thin-Film Transistors

High-k metal oxides are gradually replacing the traditional SiO2 dielectric layer in the new generation of electronic devices. In this paper, we report the production of five-element high entropy metal oxides (HEMOs) dielectric films by solution method and analyzed the role of each metal oxide in the system by characterizing the film properties. On this basis, we found optimal combination of (AlGaTiYZr)Ox with the best dielectric properties, exhibiting a low leakage current of 1.2 × 10−8 A/cm2 @1 MV/cm and a high dielectric constant, while the film’s visible transmittance is more than 90%. Based on the results of factor analysis, we increased the dielectric constant up to 52.74 by increasing the proportion of TiO2 in the HEMOs and maintained a large optical bandgap (>5 eV). We prepared thin film transistors (TFTs) based on an (AlGaTiYZr)Ox dielectric layer and an InGaZnOx (IGZO) active layer, and the devices exhibit a mobility of 18.2 cm2/Vs, a threshold voltage (Vth) of −0.203 V, and an subthreshold swing (SS) of 0.288 V/dec, along with a minimal hysteresis, which suggests a good prospect of applying HEMOs to TFTs. It can be seen that the HEMOs dielectric films prepared based on the solution method can combine the advantages of various high-k dielectrics to obtain better film properties. Moreover, HEMOs dielectric films have the advantages of simple processing, low-temperature preparation, and low cost, which are expected to be widely used as dielectric layers in new flexible, transparent, and high-performance electronic devices in the future.

The comprehensive study of hybrid dielectric layer adopted organic thin film transistors for low voltage operation

Organic electronics hold immense promise due to their flexibility, low-cost processing, and diverse applications. Despite tremendous progress, low-voltage operation has remained a significant hurdle, impacting device efficiency. Our investigation introduces a new class of low voltage driven pentacene transistors, featuring hybrid gate insulators composed of polymer buffer layer and oxygen-plasma reacted high-k metal oxides viz. AlOx, TiOx, and TaOx. We demonstrate that a combination of titanium dioxide (TiOx) as the high-k dielectric layer and poly vinyl phenol (PVP) as a buffer layer in organic thin-film transistors (OTFTs) achieves exceptional performance compared to aluminium oxide (AlOx) and tantalum oxide (TaOx). This innovative approach yields the notable field-effect mobility (1.5 cm2/Vs) and a commendable on/off ratio (3.4 × 104), surpassing devices fabricated with other high-k oxides. The success lies in the PVP’s ability to smooth surfaces and reduce interface defects, while TiOx’s superior dielectric constant fosters stronger gate control. These findings pave the way for the development of next-generation organic devices with significantly lower operating voltages, opening doors for energy-efficient and flexible electronics.

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.

Towards modeling of ZrO2 atomic layer deposition at reactor scale based on experimental kinetic approximation

In this study, the growth kinetics of ZrO2 via the atomic layer deposition (ALD) using a mixed alkylamido-cyclopentadienyl zirconium precursor are proposed based on experimental data to evaluate the film growth behavior using reactor-scale simulation. In the ALD process, the hydroxyl concentration on the targeted surface govern the saturated growth per cycle values. However, we found that the bulkiness of remaining ligands on adsorbed species hinders the adsorption of Cp-Zr molecules.Considering this phenomenon, we proposed a kinetic model by calculating the energetic terms to quantify the “steric hindrance effect” of the first elementary surface reaction of CpZr(N(CH3)2)3 precursor (Cp-Zr), which enables the film growth prediction with the reactor-scale computational fluid dynamic (CFD) model.According to the experimental ALD process, the film growth was found to be influenced by the steric hindrance factor, especially at the temperature range from 150 °C to 250 °C, but the hindrance effect decreases with increasing temperature and disappears at 300 °C. The effective activation energy of the adsorption of Cp-Zr molecules on Si substrate was estimated to be 0.175 eV. Further understanding of the kinetic of ZrO2 deposition in this study is estimated to contribute to the optimization of the high-k metal oxides ALD deposition processes.

Hafnium oxide - graphene electrodes for highly efficient aqueouselectrolyte supercapacitors

Hafnium Oxide (HO) has emerged as a novel material which has significantly revolutionized semi-conductor industry while role of this high-k metal oxide has not been investigated in-depth when it comes to the discovery of electroactive species for energy storage applications. In this context, herein we have reported the excellent electrochemical energy storage of stoichiometrically synthesized (HO)x – (GNPs)1-x nanocomposites (where x = 1, 0.75, 0.50, 0.25, 0) in different weight ratios. The presented research work aims to provide an insight into the charge storage mechanism in HO based energy storage devices by linking structural aspects with physical factors that are instrumental in impacting specific capacitance. Agile experimental techniques have been applied for structural authentication followed by a series of electrochemical experiments that have been conducted to provide in depth account of various physical parameters and their impact in achieving a superior charge storage of 925 F g−1 at a scan rate of 5 mV s−1 in 1 M H2SO4. Moreover, an energy density of 30.67 Wh - kg−1 and a power density of 235 W - kg−1 has been achieved, with a capacity retention of 80 % over 1000 cycles.

Impact of high-k metal oxide as gate dielectric on the certain electrical properties of silicon nanowire field-effect transistors: A simulation study

Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-? HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-? HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperatureinduced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models.

Dual-gated single-molecule field-effect transistors beyond Moore\u2019s law

As conventional silicon-based transistors are fast approaching the physical limit, it is essential to seek alternative candidates, which should be compatible with or even replace microelectronics in the future. Here, we report a robust solid-state single-molecule field-effect transistor architecture using graphene source/drain electrodes and a metal back-gate electrode. The transistor is constructed by a single dinuclear ruthenium-diarylethene (Ru-DAE) complex, acting as the conducting channel, connecting covalently with nanogapped graphene electrodes, providing field-effect behaviors with a maximum on/off ratio exceeding three orders of magnitude. Use of ultrathin high-k metal oxides as the dielectric layers is key in successfully achieving such a high performance. Additionally, Ru-DAE preserves its intrinsic photoisomerisation property, which enables a reversible photoswitching function. Both experimental and theoretical results demonstrate these distinct dual-gated behaviors consistently at the single-molecule level, which helps to develop the different technology for creation of practical ultraminiaturised functional electrical circuits beyond Moore’s law.

Improvement of device performance of Ph-BTBT-10 field-effect transistors fabricated on a HfO2/alicyclic polyimide double-layered gate insulator

We report on the FET properties of 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) on a HfO2/alicyclic polyimide double-layered gate insulator at an elevated temperature. The patterning of semiconductor and polymeric insulator layers is also discussed using the surface selective deposition of solution onto the wettable region (self-assembled monolayer-coated oxide layer) and unwettable region (bare metal oxide layer) obtained by vacuum ultraviolet light (172 nm) irradiation. A multilayered film of 20–30 nm thick Ph-BTBT-10 and a double-layered gate insulator consisting of 30–40 nm thick alicyclic polyimide on high-k metal oxide films leads to a reduction in the operating voltage and the interfacial trap density at the gate insulator interface. The mobility of the FETs was improved from 0.4 to 2.4 cm2 V−1 s−1 by thermal annealing of Ph-BTBT-10 at 120 °C due to the transition from a monolayer to a bilayer structure and the use of alicyclic polyimide as the polymer gate insulator.

Sol-gel derived high performance low-voltage thin film transistor

Sol-gel high-k metal oxide thin film transistors (TFTs) have fascinated huge interest due to their prospective applications in cost-effective, low operating voltage electronics such as sensors, radio frequency identification tags, portable electronics and backplane circuitry for flat panel display. In this work, we report a sol–gel synthesis procedure of γ-phase of lithium aluminates (γ-LiAlO2) which is a high-k material due to the ionic polarization of mobile Li+ of the crystal. This high-k dielectric has been successfully utilized as a gate insulator of a low voltage indium zinc oxide (IZO) TFT. The optimize device shows a moderate on/off ratio of 9 × 102 and electron mobility of 4 cm2 V−1 s−1 under 2.0 V operation. This γ-LiAlO2 dielectric has been synthesized by cost-effective sol–gel technique followed by annealing process at 700 °C.

A Low-Temperature Solution-Process High-k Dielectric for High-Performance Flexible Organic Field-Effect Transistors

Applying high-k dielectrics can effectively reduce the operating voltage of OFETs to a few volts, thus significantly miniaturizing the dynamic power consumption of OFETs. Aluminum oxide is known as a promising dielectric material for its high permittivity (k=6–9). In this work, a simple, low-cost, low-temperature (only 85 °C) solution process is used to prepare amorphous AlOx dielectric thin films for high-performance flexible OFET applications. The AlOx thin film was spin-coated and then solidified using deep ultraviolet irradiation without high-temperature annealing. The as-deposited AlOx thin film has a root mean square surface roughness of 0.47 nm and maintains a very low leakage current density of 8×10−9 A/cm2 at 3.5 MV/cm and high dielectric constant of about 8.3 (at 1 kHz). The complete OFET based on this dielectric can operate at a 3 V gate bias with saturation mobility of 1.8 cm2/Vs, and steep sub-threshold swing of 110 mV/dec. Our work demonstrated a low-temperature solution process to fabricate a high-k metal oxide dielectric for low-power OFET applications.

Cross-Plane Thermal Conductance of Phosphonate-Based Self-Assembled Monolayers and Self-Assembled Nanodielectrics.

Self-assembled nanodielectrics (SANDs) consist of alternating layers of polarized phosphonate-functionalized azastibazolium π-electron (PAE) and high-k dielectric metal oxide (ZrO2 or HfOx) films. SANDs are desirable gate dielectrics materials for thin-film transistor applications because of their excellent properties such as low-temperature fabrication, large dielectric strength, and large capacitance. In this paper, we investigate the cross-plane thermal boundary conductance of SANDs using the frequency domain thermoreflectance (FDTR) technique. First, we characterize the thermal conductance of PAE self-assembled monolayers (SAMs), inverted-PAE (IPAE) SAMs, and mixed PAE-IPAE SAMs, sandwiched between thin gold and silica (SiO2) films at the top and bottom surfaces. Next, we quantify the thermal conductance of SAND-n with different numbers (n) of PAE-ZrO2 layers and thicknesses ranging between 4.7 and 11.3 nm. From the FDTR measurements, we observe that the thermal boundary conductance of the SAMs can be tuned between 42.1 ± 4.6 MW/(m2 K) and 52.4 ± 2.5 MW/(m2 K), based on the relative density of the PAE and IPAE chromophores. In the SAND-n samples, we observe a monotonic decrease in the thermal conductance with increasing n. We use the measured thermal conductance data in a series resistance model to estimate a thermal interface conductance of 695 MW/(m2 K) for the contact between the PAE chromophore and the zirconium dioxide films, which is an order of magnitude larger than the SAMs. We attribute the improved thermal conductance to stronger adhesion between the PAE chromophore and the zirconium dioxide films, as compared to the weakly bonded SAMs to the gold and silicon dioxide films.

Improvement of field-effect transistor performance with highly oriented, vertically phase separated TIPS-pentacene/polystylene blends on high-k metal oxide films by using meniscus coating

We report on the quick deposition technique of the highly oriented 6, 13-bis (trisopropylsilylethynyl) pentacene (TIPS-pentacene) crystalline films from the polystylene (PS)/TIPS-pentacene blend solution onto the oxide dielectric films at an elevated temperature for fabricating organic field-effect transistors (FETs). A vertical phase separation between TIPS-pentacene and PS films on high-k metal oxide films leads to the reduction of operating voltage and the interfacial trap density at the gate insulator interface. The polarized optical microscopy image and in-plane X-ray diffraction analysis suggest the pi-stacking of TIPS-pentacene molecules along the direction parallel to the sweeping direction of meniscus coating. The highly oriented TIPS-pentacene crystalline films were obtained at 0.75–2.0 mm s−1 at 70 °C which was much faster than room temperature (0.01 mm s−1). These effects eventually lead to both the improvement of FET properties and device fabrication processes.

Performance evaluation of free-silicon organic-inorganic hybrid (SiO2-TiO2-PVP) thin films as a gate dielectric

An approach to achieve the transparent thin film transistors (TTFTs) using transparent electrodes such as ITO or FTO for gate, source and drain electrodes (Free-silicon gate electrode). On the other hand, the high-k transparent metal oxides can be used for this purpose in gate dielectric by a low temperature sol-gel technique. Furthermore, not only use of high-k organic materials in gate dielectric reduces the leakage current but also it improves the device flexibility. The organic-inorganic hybrid composites of SiO2/TiO2-PVP (STP) with different TiO2 ratios are deposited on PET-ITO substrates (Free-silicon gate electrode) as gate dielectric. The thermal behavior and structural characterization of STP films are done by TGA, XRD and XPS analyses. The AFM analyze of STP films shows that they have very smooth surface. A transparent thin layer of ZnO is used as a transistor channel by sputtering technique. Evaluation on electrical performance of OFETs exhibits that they have high mobility, low threshold voltage and acceptable Ion/Ioff ratio.

Electron mobility enhancement in solution-processed low-voltage In2O3 transistors via channel interface planarization

The quality of the gate dielectric/semiconductor interface in thin-film transistors (TFTs) is known to determine the optimum operating characteristics attainable. As a result in recent years the development of methodologies that aim to improve the channel interface quality has become a priority. Herein, we study the impact of the surface morphology of three solution-processed high-k metal oxide dielectrics, namely AlOx, HfOx, and ZrOx, on the operating characteristics of In2O3 TFTs. Six different dielectric configurations were produced via single or double-step spin-casting of the various precursor formulations. All layers exhibited high areal capacitance in the range of 200 to 575 nF/cm2, hence proving suitable, for application in low-voltage n-channel In2O3 TFTs. Study of the surface topography of the various layers indicates that double spin-cast dielectrics exhibit consistently smoother layer surfaces and yield TFTs with improved operating characteristics manifested, primarily, as an increase in the electron mobility (µ). To this end, µ is found to increase from 1 to 2 cm2/Vs for AlOx, 1.8 to 6.4 cm2/Vs for HfOx, and 2.8 to 18.7 cm2/Vs for ZrOx-based In2O3 TFTs utilizing single and double-layer dielectric, respectively. The proposed method is simple and potentially applicable to other metal oxide dielectrics and semiconductors.

Bias Stability Enhancement in Thin-Film Transistor with a Solution-Processed ZrO2 Dielectric as Gate Insulator

In this paper, a high-k metal-oxide film (ZrO2) was successfully prepared by a solution-phase method, and whose physical properties were measured by X-ray diffraction (XRD), X-ray reflectivity (XRR) and atomic force microscopy (AFM). Furthermore, indium–gallium–zinc oxide thin-film transistors (IGZO-TFTs) with high-k ZrO2 dielectric layers were demonstrated, and the electrical performance and bias stability were investigated in detail. By spin-coating 0.3 M precursor six times, a dense ZrO2 film, with smoother surface and fewer defects, was fabricated. The TFT devices with optimal ZrO2 dielectric exhibit a saturation mobility up to 12.7 cm2 V−1 s−1, and an on/off ratio as high as 7.6 × 105. The offset of the threshold voltage was less than 0.6 V under positive and negative bias stress for 3600 s.

Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of ~7 × 107 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm2/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.

Approaching Defect-free Amorphous Silicon Nitride by Plasma-assisted Atomic Beam Deposition for High Performance Gate Dielectric.

In the past few decades, gate insulators with a high dielectric constant (high-k dielectric) enabling a physically thick but dielectrically thin insulating layer, have been used to replace traditional SiOx insulator and to ensure continuous downscaling of Si-based transistor technology. However, due to the non-silicon derivative natures of the high-k metal oxides, transport properties in these dielectrics are still limited by various structural defects on the hetero-interfaces and inside the dielectrics. Here, we show that another insulating silicon compound, amorphous silicon nitride (a-Si3N4), is a promising candidate of effective electrical insulator for use as a high-k dielectric. We have examined a-Si3N4 deposited using the plasma-assisted atomic beam deposition (PA-ABD) technique in an ultra-high vacuum (UHV) environment and demonstrated the absence of defect-related luminescence; it was also found that the electronic structure across the a-Si3N4/Si heterojunction approaches the intrinsic limit, which exhibits large band gap energy and valence band offset. We demonstrate that charge transport properties in the metal/a-Si3N4/Si (MNS) structures approach defect-free limits with a large breakdown field and a low leakage current. Using PA-ABD, our results suggest a general strategy to markedly improve the performance of gate dielectric using a nearly defect-free insulator.

(Invited) ALD Materials for the Integration of III-V Based Transistors

III-V compound semiconductors are promising transistor channel materials to enable scaling beyond Si technology due to their high bulk electron mobility values. Engineering the III-V / high-k gate stack remains one of the main technical challenges to integration of these materials in CMOS technology, with Atomic Layer Deposition (ALD) continuing to play an enabling role. In this work, multiple approaches for interfacial sulfur passivation prior to high-k gate stack deposition are explored, with passivated samples exhibiting improved C-V characteristics and reduced Dit values for planar MOSCAPS. Various III-V channel / high-k metal oxide interface layers (ILs) deposited by ALD have also been evaluated in order to reduce the impact of oxide traps while also maintaining a low Dit. A novel ALD interfacial layer material has been developed which demonstrates the potential to meet challenging requirements for III-V channel transistor integration.

(Invited) A Metal Oxide Antifuse-Diode Device

Crystalline metal oxides have been used in various micro and nano electronics and optoelectronics, such as conductors, superconductors, and light emitting devices (LEDs). The amorphous metal oxide dielectric is usually a high-k material suitable for the insulation purpose. The doped metal oxide, such as the Zr-doped HfO2 (ZrHfO), high-k thin film has many advantageous material and electrical properties, such as the high crystallization temperature, low interface layer thickness in contact with Si, and low interface density of states (1). When nanocrystals are embedded into the high-k metal oxide dielectric thin film, electrons and charges can be stored for a long period of time, which is suitable for the nonvolatile memory application (2). Recently, it was proved by the author’s group that the broad band white light could be emitted from the metal oxide dielectric thin film after the dielectric breakdown due to the thermal excitation of the nano size conductive paths (3). In this talk, a new high-k dielectric based device that shows both antifuse and diode functions is reported. Figure 1 shows a large “programmed” to “unprogrammed” leakage current ratio of 105 is obtained from an original MOS capacitor made of a high-kgate dielectric on a p-type wafer, which fits the antifuse requirement. Figure 2 shows that for a same device in the programmed state, the leakage current increases with the increase of the magnitude of the gate voltage in the negative voltage range. However, the leakage current remains low and changes little over a large range of gate voltage in the positive voltage range, which is similar to the diode behavior. On the other hand, the leakage current-voltage curve of the new device is almost linear while that of the conventional diode follows the exponential relationship. The operation physics, structure, and material properties of the new device will be discussed in detail. Y. Kuo, J. Lu, S. Chatterjee, J. Yan, H. C. Kim, T. Yuan, W. Luo, J. Peterson, and M. Gardner, “Sub 2 nm Thick Zirconium Doped Hafnium Oxide High-K Gate Dielectrics,” ECS Trans., 1(5), 447-454 (2006).Y. Kuo, invited, “Nanocrystals Embedded High-k Nonvolatile Memories – bulk film and nanocrystal material effects,” ECS Trans., 53(4), 121-128 (2013).Y. Kuo, invited, “A Solid State Thin Film Incandescent Light Emitting Device,” Proc. IDEM, 104-107 (2014). Figure 1

(Invited) ALD Materials for the Integration of III-V Based Transistors

III-V compound semiconductors are considered promising transistor channel materials to enable scaling beyond Si technology due to their high bulk electron mobility values. However, unlike Si, III-V materials have comparatively poor quality oxides and the interface between commonly utilized high-k dielectrics and the III-V channel surface is problematic. Engineering the high-k gate stack remains one of the main technical challenges to integration of III-V materials in Si-based CMOS technology. Silicon dioxide (SiO2) forms an extremely high quality interface with Si and features a high bandgap (9eV) which effectively screens channel electrons from the effects of oxide traps in bulk high-k materials (e.g., hafnium oxide) which degrade electron mobility. However, unlike Si, III-V materials possess poor quality native oxides with a very high density of oxide traps, which thus prove unsuitable as channel dielectrics due to the resultant high density of interface states (Dit). Formation of these oxides must be prevented, making surface preclean and chemical passivation techniques critical. In addition, an alternative IL is required prior to deposition of the primary high-k dielectric to reduce the impact of oxide traps while also maintaining a low Dit. Optimization of the primary high-k deposition process itself may also be required. Due to the ultra-thin layers and moisture / oxygen sensitive materials in question, in-situ processing without air exposure throughout the gate dielectric sequence is beneficial, if not mandatory. Various approaches have been introduced to passivate the III-V surface prior to dielectric deposition to achieve reduced interface states. Sulfur passivation via immersion in wet chemical (NH4)2S solutions has been the most studied, with demonstration of promising interface properties. However, this approach is difficult to integrate into a vacuum deposition system, resulting in unavoidable air exposure time following sulfur passivation. To address the limitations of wet chemical processing, an innovative in-situ sulfur passivation approach is described here. In this approach, the sulfur precursor is delivered in vapor form from either (NH4)2S solution or compressed H2S gas cylinder in-situ to a hot walled cross flow ASM Pulsar® 3000 ALD reactor such that the high-k layers can be deposited immediately following passivation without air exposure. In-situ vapor passivation treatments yield higher [S] than solution-based passivation techniques per XPS analysis. Passivated samples exhibit improved C-V characteristics, and lower dispersion values compared to the HCl etched reference for planar MOSCAPS. The Ditvalues for in-situ passivated samples were reduced to ~1-2x1012 /cm2eV, promising for application to high mobility transistors. SiO2 is a candidate IL for III-V gate stacks due to its high bandgap and low density of oxide traps, but a high quality atomic layer deposited SiO2 film without significant channel oxidation has not been demonstrated on Si, let alone III-V materials, to date. The incorporation of Si into another metal oxide (e.g., Al2O3) is thus an interesting approach for evaluation. Two H2O-based ALD processes for aluminum silicate (Al1-xSixO) were developed using an ASM Pulsar®. Trimethylaluminum (TMA) and aluminum chloride (AlCl3), have been compared as Al precursors with silicon tetrachloride (SiCl4) as the Si precursor. The TMA-based process exhibits a measureable level of C incorporation (2-3%), while [C] in the AlCl3-based process was below detection limits due to halide chemistries utilized. Parasitic C in the TMA-based IL is projected to be a contributor to oxide defects resulting in degraded electrical performance as compared to the pure halide-based process. The impact of other factors such as deposition temperature and pulsing sequence were also studied, and the ALD growth mechanisms for these two processes are discussed in further detail. Ultimately, Al2O3-based materials and other commonly investigated high-k metal oxides appear limited in ability to meet the performance requirements for a robust III-V channel transistor, although incremental improvements have been demonstrated. As such, alternative ALD materials have been extensively explored for application to III-V channel materials. Recent development has resulted in demonstration of a low temperature thermal ALD process of a novel material which exhibits strong potential for application as IL in III-V channel devices. The IL material is also deposited using an ASM Pulsar® reactor, following S passivation and prior to deposition of HfO2 high-k bulk dielectric. Dit values <1E12, low dispersion (<1%) and hysteresis (<30 mV) values have been demonstrated. Current device performance equals previously published benchmark device metrics for InGaAs channel devices. We projected that device performance can be further improved via optimization of the in-situ passivation and ALD process parameters for the novel interface layer and bulk high-k.