High-k HfO2 Research Articles

Integration of perovskite Pb[Zr0.35Ti0.65]O3/HfO2 ferroelectric-dielectric composite film on Si substrate

PurposeThe purpose of this paper is to investigate the effect of high-k material HfO2 as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.Design/methodology/approachRF-sputtered Pb[Zr0.35Ti0.65]O3 or (PZT) and plasma-enhanced atomic layer deposited HfO2 films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO2 films, respectivelyFindingsElectrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm2 and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO2 buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.Originality/valueThe MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO2) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

BEOL Compatible High-Capacitance MIMCAP Structure Using a Novel High k Material

We demonstrate a MIM capacitor structure using ZrO2 for the dielectric layer which exhibits a 25% capacitance increase (from ~43fF/mm2 to >55fF/mm2 for a ~55A film) with minimal leakage current increase compared to Hf based dielectrics, extending the usefulness of MIM on-chip decoupling capacitors. The MIM structure, suitable for BEOL processing is TiN/ZrO2/TiN combined with an anneal which is shown to improve the capacitance vs. leakage performance compared to doped and undoped HfO2 based control structures. GI-XRD measurements demonstrate that the capacitance increase corresponds with a phase transformation of the ZrO2 from amorphous to cubic phase, which is shown to have a dielectric constant (k) up to 35. Reliability models based on hard-breakdown (HBD) show that this structure exceeds the end-of-life targets.Servers and high-performance chips have historically relied on on-chip decoupling capacitors (decap) to reduce power supply noise in order to achieve 3 – 5.4 GHz operating frequency. Although packaging decap can be very effective at mitigating low and mid-frequency noise, on-chip decap, such as MIMCAP, is critical for mitigating mid and high-frequency noise. As Fig. 1 shows, an increase in on-chip decap can result in a significant performance benefit, due to their fast response time slowing the fastest droops, giving time for slower response elements to contribute. One method of achieving this increased decap is to increase the k of the material being used as the insulator in the MIMCAP. Following high-k gate dielectric technology, HfO2 and other Hf based dielectric stacks have been used for this layer successfully [1]. But there is a significant difference in the thermal budget that the dielectric is exposed to following the deposition between gate dielectric and MIMCAP applications. The gate dielectric, deposited prior to any metallization, will typically be exposed to a relatively high thermal budget compared to the insulator layer of a decoupling MIMCAP, which is usually placed between wiring levels in the back end of the line (BEOL) [2]. Since the thermal budget after deposition will affect the crystal structure of a material, and different crystal phases of the same material can have dramatically different dielectric constants [3], the actual dielectric constant of a particular high-k material may vary significantly depending on whether it is used as the gate dielectric or as the MIM insulator. In this work, we explore the use of a ZrO2 as the high- k layer for MIMCAP applications and show that its low crystallization temperature enables it to achieve a significantly higher k value compared to HfO2 when processed under BEOL compatible thermal conditions.Fig. 2 shows the development of the high-k phase of a 55A ZrO2 film as the anneal temperature is increased. The peaks at 35, 42 and 52 are the signature of the bottom TiN electrode and do not change with anneals; but the peaks at 30.2 and 50.3 degrees, which are seen to develop as the anneal temperature increases, match with the 111 and 220 planes of the cubic phase of ZrO2. MIMCAPs built using similarly annealed ZrO2 layers as dielectrics exhibit an increase in capacitance as shown in Fig. 3a: there is a slight increase after anneal A, significantly more increase after anneal B, and additional moderate increases after C and D. No such capacitance increase is seen when Hf based dielectrics are used (Fig. 3b). The maximum capacitance is found to be ~56fF/um2 after anneal D compared to ~43fF/um2 for the unannealed device, an increase of more than 25%, while the leakage current remains virtually unchanged at 1V, and increases by <5x at 2V. Fig. 3c graphs the calculated value of k as a function of the thermal budget, confirming that the ZrO2 layer has the property of crystallizing to its high- k phase at temperatures relatively lower than is typical for HfO2. Thus, we can achieve high capacitance with a relatively thick high-k layer, keeping the leakage current low, all while maintaining compatibility with BEOL processing.[1] T. Ando et al., “CMOS Compatible MIM Decoupling Capacitor with Reliable Sub-nm EOT High-k Stacks for the 7nm Node and Beyond,” Tech. Dig. IEDM 2016, pp. 9.4.1 - 9.4.4.[2] K. Fischer et al., “Low-k Interconnect Stack with multi-layer Air Gap and Tri-Metal-Insulator-Metal Capacitors for 14-nm High Volume Manufacturing,” IEEE Interconnect Tech. Conf. 2015, 10.1109/IITC-MAM.2015.7325600.[3] X. Zhao and D. Vanderbilt, “First-principles Study of Electronic and Dielectric Properties of ZrO2 and HfO2” MRS Proceedings, 747. doi:10.1557/PROC-747-T5.2/N7.2. Figure 1

Interfacial Characterization and Transport Conduction Mechanisms in Al|HfO2|p-Ge Structures: Energy Band Diagram

Ge-based metal-oxide semiconductor structures exhibiting thin ALD-grown high-k dielectric HfO2 films were fabricated and characterized chemically, structurally, and electrically. X-ray photoelectron (XP) spectroscopy confirms the good stoichiometry of the ALD-grown HfO2 films. Furthermore, through the analysis of the XP spectra, the conduction and valence band offsets of HfO2|p-Ge were calculated to be equal to 1.8 ± 0.2 eV and 2.8 ± 0.2 eV, respectively. C(V) and G(V) analysis reveals structures with a well-defined MOS behavior with Dit values in the range of 1011 eV–1 cm–2 and a dielectric constant of HfO2 films of 20. The dominant carrier transport conduction mechanisms were studied through J(V) analysis, performed at both substrate and gate electron injection. Specifically, in the low voltage region (V 3.0 V) and high temperatures (>450 K). Applying Schottky’s emission model the energy barrier heights of HfO2|p-Ge and Al|HfO2 interfaces were evaluated equal to 1.7 ± 0.2 eV and 1.3 ± 0.2 eV, respectively. Combining the XPS and J(V) analysis results, the energy band diagram of Al|HfO2|p-Ge structures is constructed. The calculated values of conduction and valence band offsets via XPS and J(V) measurements are in very good agreement.

(Invited) Where Are the Best Insulators for 2D Field-Effect Transistors?

Two-dimensional (2D) semiconductors are very promising for applications in next-generation field-effect transistors (FETs) which could overcome scaling limitations of Si technologies and thus extend the life of Moore’s law. The success at achieving this ambitious goal will depend on the availability of compatible insulators which are always required to separate the gate from the channel. Ideally, these insulators should go along with 2D semiconductors as well as SiO2 goes with Si. However, the research community is mostly focused on 2D semiconductors while not paying enough attention to finding suitable insulators for 2D FETs. In order to shed some light on this problem, here we formulate general requirements for insulators in 2D FETs and discuss the potential of already used and promising materials.The scaling potential of 2D FETs can be fully exploited only if high quality insulators with an equivalent oxide thickness (EOT) below 1nm are available, as required for low subthreshold swings and reduced power consumption. This results in the following requirements for gate insulators: First, dielectric properties have to be good enough to maintain low tunnel and thermionic leakage currents to achieve high on/off current ratios. This implies high dielectric constants, wide band gaps and large band offsets with the channel material. Second, the insulator must form a well-defined interface with the channel, which is primarily required for a high mobility. Third, the number of active insulator defects within a few nanometers from the interface has to be low, in order to reduce charge trapping and thus maintain high stability of device operation. Finally, the insulators have to be electrically stable when scaled and survive electric fields of at least 10MV/cm.Most previously reported 2D FETs employ conventional oxides (e.g. SiO2, HfO2, Al2O3) known from Si technologies. High-k oxides HfO2 and Al2O3 appear to be the most promising, as they in principle satisfy the requirement on low leakage currents. However, they are amorphous when grown in thin layer, thus forming poor-quality interfaces with 2D channels, and contain numerous unavoidable insulator defects which lead to hysteresis and long-term drifts of the gate transfer characteristics. As a result, it appears to be unlikely that these materials can be considered promising for applications in future fully scalable 2D FETs.In the spirit of Si technologies, a possible alternative to conventional oxides could be oxidation of 2D semiconductors to form native oxides, such as MoO3 from MoS2. While this may improve the interface quality, native oxides are still amorphous and sometimes non-stoichiometric, which leads to high densities of insulator defects and limited electric strength. Thus, considerable research efforts are still required to understand their potential.Another possible solution is the use of layered 2D insulators. Their main advantage is their crystalline structure which leads to well-defined interface with 2D semiconductors and a low density of insulator defects. However, the most widely used 2D insulator is hexagonal boron nitride (hBN) which has a narrow bandgap (6eV) and a small dielectric constant (less than 5). This makes it difficult to maintain low gate leakage currents for hBN with sub-1nm EOT. Thus, alternative 2D insulators have to be urgently identified and characterized. Among these materials are mica, which outperforms hBN in terms of dielectric properties, and 2D oxide nanosheets. However, considerable processing advances are required to result in the demonstration of real devices.Finally, another interesting option would be the use of ionic crystals, such as epitaxial fluorides (e.g. CaF2, BaF2, and LaF3). Similar to 2D insulators, fluorides ideally contain a small number of defects and form well-defined interfaces with 2D semiconductors. Also, in contrast to hBN, they have good dielectric properties, e.g. a bandgap of 12.1 eV and a dielectric constant of 8.43 for CaF2. Recently, excellent performance of MoS2 FETs with 2nm thick epitaxial CaF2 (0.9nm EOT) has been achieved, which is currently impossible with any other insulator discussed above. Thus, further research on these insulators appears a very promising way for the development of scalable 2D FETs.In summary, the question about the most promising insulators for 2D FETs is still open. However, already now it is clear that successful integration of amorphous oxides into these devices appears problematic. Thus, it can be concluded that high-quality 2D FETs require crystalline insulators. These can be either layered 2D or ionic crystals with chemically inert surfaces, which generally address the fundamental limitations of oxides. Further research on these materials should target those which have the best dielectric properties and can be synthesized using fully scalable methods.

Atomic layer deposited 2D MoS2 atomic crystals: from material to circuit

Atomic layer deposition (ALD) can be used for wafer-scale synthesis of 2D materials. In this paper, a novel, reliable, secure, low-cost, and high-efficiency process for the fabrication of MoS2 is introduced and investigated. The resulting 2D materials show high carrier-mobility as well as excellent electrical uniformity. Using molybdenum pentachloride (MoCl5) and hexamethyldisilathiane (HMDST) as ALD precursors, thickness-controlled MoS2 films are uniformly deposited on a 50 mm sapphire and a 100 mm silica substrate. This is done with a high growth-rate (up to 0.90 A/cycle). Large-scale top-gated FET arrays are fabricated using the films, with a room-temperature mobility of 0.56 cm2/(V·s) and a high on/off current ratio of 106. Excellent electrical uniformity is observed in the whole sapphire wafer. Additionally, logical circuits, including inverters, NAND, AND, NOR, and OR gates, are realized successfully with a high-k HfO2 dielectric layer. Our inverters exhibit a fast response frequency of 50 Hz and a DC-voltage gain of 4 at VDD = 4 V. These results indicate that the new method has the potential to synthesize high quality MoS2 films on a large-scale, with hypo-toxicity and enhanced efficiency, which can facilitate a broader range of applications in the future.

Enhanced memory characteristics of charge trapping memory by employing graphene oxide quantum dots

In this study, graphene oxide quantum dots (GOQDs) are embedded in the charge trapping layer of high-k material HfO2 for nonvolatile memory applications. The fabricated devices exhibit a large memory window of ∼1.57 V under a ±3.5 V applied sweeping voltage and show only ∼13.1% of charge loss after a retention time of 1.2 × 104 s. This excellent performance is attributed to the quantum well formed in the charge trapping layer. Defect traps in the HfO2 film enhance the charge trapping efficiency and retention property of fabricated devices. This work implies that GOQDs embedded in high-k materials are promising for charge trapping memory applications.

Low-Voltage Hf-ZnO Thin Film Transistors With Ag Nanowires Gate Electrode and Their Application in Logic Circuit

The high performance Hf doped ZnO (Hf-ZnO) flexible thin film transistors (TFTs) were fabricated using Ag NWs as gate electrode and high-k HfO2 as dielectric. The field effect mobility of Hf-ZnO is 14.7 cm2/Vs, ${I} _{\mathrm{ on}}/{I} _{\mathrm{ off}}$ ratio is more than 106, and the subthreshold swing is about 0.26 V/dec. Furthermore, after 5000 bending cycles test, the TFTs with Ag NWs still maintain a superior performance, such as the high mobility of 12.6 cm2/Vs and the small subthreshold swing of 0.33 V/dec. The operating voltage of Hf-ZnO is only 5 V, showing the great potential of application in low-powered devices. We also fabricated the resistor-loaded inverter based on the flexible TFTs. The shift of input voltage is negligible with different supplied voltages, indicating the highly-stable property of the inverter. As a result, the low consumption optoelectronics provide great inspiration for researchers to construct the next generation high performance wearable and flexible devices.

Performance analysis of high-k materials as stern layer in ion-sensitive field effect transistor using commercial TCAD

High-k materials as a STERN Layer for Ion-Sensitive-Field-Effect-Transistor (ISFET) have improved ISFET sensitivity and stability. These materials decrease leakage current and increase capacitance of the ISFET gate toward highest current sensitivity. So far, many high-k materials have been utilized for ISFET, yet they were examined individually, or using numerical solutions rather than using integrated TCAD environment. Exploiting TCAD environment leads to extract ISFET equivalent circuit parameters and performs full analysis for both device and circuit. In this study we introduce a comprehensive investigation of different high-k material, Tio2, Ta2O5, ZrO2, Al2O3, HfO2 and Si3N4 as well as normal silicon dioxide and their effects on ISFET sensitivity and stability. This was implemented by developing commercial Silvaco TCAD rather than expensive real fabrication. The results confirm that employing high-k materials in ISFET outperform normal silicon dioxide in terms of sensitivity and stability. Further analysis revealed that Titanium dioxide showed the highest sensitivity followed by two groups HfO2, Ta2O5 and ZrO2, Al2O3 respectively. Another notable exception of Si3N4 that is less than other materials, but still have higher sensitivity than normal silicon dioxide. We believe that this study opens new directions for further analysis and optimization prior to the real cost-ineffective fabrication.

Effects of Microwave Annealing on High-k Dielectric HfO₂ Thin Films.

In this study, the effect of microwave annealing (MWA), which has been attracting considerable attention as a low-thermal-budget method, on the high-k materials required for next-generation ultrahigh-integration semiconductor devices is investigated. Metal-oxide-semiconductor (MOS) capacitor-structure devices are fabricated using HfO₂ films, which are typical high-k materials; post deposition annealing (PDA) is then performed by MWA and compared to conventional thermal annealing (CTA). The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the fabricated HfO₂ MOS capacitors are measured to evaluate the leakage current, time-zero dielectric breakdown (TZDB), time-dependent dielectric breakdown (TDDB), and frequency dispersion. Compared to the as-deposited state, the PDA-treated HfO₂ dielectric film is found to have reduced trap density, improved dielectric breakdown, frequency dispersion, and lifetime. In particular, the high-k HfO₂ thin films treated with MWA exhibit excellent surface properties, including a low root-mean square roughness (Rq) of 0.141 nm, thickness of 49.3 nm, and low inter face trap density (Dit) of 7.82 × 1012 cm-2eV-1 and electrical properties such as a high breakdown electric field (EBD) of 10 MV/cm, and high breakdown to charge (QBD) of 1,000 C/cm². As a result, the MWA-treated high-k HfO₂ thin films are smoother and denser than the CTA-treated thin films, and show better electrical properties and reliability, suggesting that the defects at Si the interface as well as in the high-k films are effectively removed.

(Invited) Characteristics of Several High-k Gate Insulators for GaN Power Device

Introduction Vertical GaN metal-oxide-semiconductor (MOS) devices on freestanding GaN substrates have been widely investigated as a means of reducing the dimensions of devices intended for applications associated with high power and high frequency [1]. Inserting a gate insulator in such as MOS structures has been found to result in low leakage currents and high breakdown strengths. Oxide (High-k) with a high dielectric constant (k)-value have been studied instead of SiO2 from the viewpoint of increasing the physical thickness. Numerous High-k gate insulators, including Al2O3, HfO2, Al2O3-HfO2 bilayers, AlSiOx and HfSiOx have been studied for use in MOS units [2, 3]. These films are typically fabricated using atomic layer deposition (ALD) because ALD has a big advantage of conformal film fabrication on three-dimensional structure, which is required when producing vertical GaN devices. To improve electrical properties of these gate insulators and GaN/insulator interface, annealing process was carried out after High-k deposition (post-deposition annealing: PDA) and post-metal deposition (post-metal deposition annealing: PMA). Actually, GaN capacitors with Al2O3 reduced significantly the interface state density (Dit) at GaN/Al2O3 interface by PMA at low temperarure ~ 300 °C [4]. On the other hand, Ga diffusion and additional electrical defects were also found to be easily introduced into GaN/High-k stack structure by PDA at a high temperarure above 700 °C. Here, we have an interesiting about how the PDA and PMA processes affect to characteristics of GaN devices with several High-k gate insulators. In this paper, we present influence of the PDA and PMA processes on characteristics of GaN capacitors with Al2O3, HfO2, and HfSiOx gate insulators. Experiment Pt-gated n-GaN MOS capacitors were fabricated as follows: Firstly, ~20-nm-thick High-k gate insulators such as Al2O3, HfO2, and HfO2/SiO2 laminate were deposited on n+-GaN/n-GaN epilayer by plasma-enhanced ALD at 300 °C. Next, PDA was carried out at 800 °C in N2. HfSiOx was formed from HfO2/SiO2 laminate after PDA. Finally, Pt gate electrode and Pt/Ti ohmic cntact were deposited to fabricate n-GaN/High-k/Pt MOS capacitors. PMA was performed at 300 °C in N2. Results and discussion The Al2O3 and HfO2 films had polycrystalline structure of g phase and monoclinic phase, respectively, while the HfSiOx film had an amorphous structure after PDA at 800 °C. The k values for the Al2O3, HfO2, and HfSiOx films which esgtimated from capacitance (C)-voltage (V) data were 8, 17.6, and 15.1, respectively. The Al2O3 capacitor exhibited a large frequency dispersion while the HfO2 and HfSiOx capacitors were negligible small, indicating that the charging state of the interface traps occur at GaN/Al2O3 interface. The frequency dispersion of the Al2O3 capacitor significantly decreases after PMA at 300 °C. To better understand the characteristics of the GaN/High-k interface, the Dit was also estimated using a conductance method. The Dit values of all capacitors before PMA at the energy level of Ec-E = 0.4 V was decreased in the following order: Al2O3 (5 × 1012 cm-2eV-1) > HfO2 (1.4 × 1012 cm-2eV-1) > HfSiOx (4 × 1011 cm-2eV-1). As expected from the C-V characteristics, the Al2O3 capacitor had a large Dit value due to the electron traps. From the leakage current density (J)-electric field (E) characteristics, The J values of the HfSiOx capacitor was significantly reduced compared to those of the Al2O3 and HfO2 capacitors. It is thought that the difference in the J properties between the HfSiOx and other Al2O3, HfO2 can be primarily attributed to the presence of amorphous or polycrystalline structures, because grain boundaries in polycrystalline structures can act current leakage paths. Considering the bias application for the same amount of charge accumulation at the interface, effective breakdown electric field (Ebd) values, which was estimated from the applied voltage divided by capacitance equivalent thickness, were 15, 14, and 35 MV/cm in Al2O3, HfO2, and HfSiOx capacitors, respectively. Summary We conclude that the HfSiOx film is an attractive material as gate insulator because of amorphous structure, higher k, relatively low Dit, and high effective Ebd. Acknowledgement The authors wish to thank Prof. T. Hashizume of Hokkaido University for helpful discussion. This work was supported in part by the MEXT Program for the Research and Development of Next-generation Semiconductors to Realize an Energy-saving Society.

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO₂

Coulomb scattering mechanism transition in 2D layered MoTe2: effect of high-κ passivation and Schottky barrier height

Clean interface and low contact resistance are crucial requirements in two-dimensional (2D) materials to preserve their intrinsic carrier mobility. However, atomically thin 2D materials are sensitive to undesired Coulomb scatterers such as surface/interface adsorbates, metal-to-semiconductor Schottky barrier (SB), and ionic charges in the gate oxides, which often limits the understanding of the charge scattering mechanism in 2D electronic systems. Here, we present the effects of hafnium dioxide (HfO2) high-κ passivation and SB height on the low-frequency (LF) noise characteristics of multilayer molybdenum ditelluride (MoTe2) transistors. The passivated HfO2 passivation layer significantly suppresses the surface reaction and enhances dielectric screening effect, resulting in an excess electron n-doping, zero hysteresis, and substantial improvement in carrier mobility. After the high-κ HfO2 passivation, the obtained LF noise data appropriately demonstrates the transition of the Coulomb scattering mechanism from the SB contact to the channel, revealing the significant SB noise contribution to the 1/f noise. The substantial excess LF noise in the subthreshold regime is mainly attributed to the excess metal-to-MoTe2 SB noise and is fully eliminated at the high drain bias regime. This study provides a clear insight into the origin of electronic signal perturbation in 2D electronic systems.

Effect of the interfacial (low-k SiO2 vs high-k Al2O3) dielectrics on the electrical performance of a-ITZO TFT

In this work, the effect of an interfacial low-k dielectric layer such as SiO2 was suggested along with the effect of an interfacial high-k dielectric layer such as Al2O3 on the electrical characteristics and then the electrical properties of the a-ITZO TFT such as the equivalent oxide thickness (EOT) of gate dielectric, gate capacitance per unit area ( $${C_{\text{i}}}$$ ), on-current ( $${I_{{\text{on}}}}$$ ), on–off current ( $${I_{{\text{on}}}}/{I_{{\text{off}}}}$$ ) ratio and field-effect mobility ( $${\mu _{{\text{FE}}}}$$ ) of the a-ITZO TFT. The main purpose of this study is to conduct a comparative study to highlight the impact of the interfacial high-k dielectrics such as Al2O3, compared to low-k SiO2, the existing between the a-ITZO active layer and high-k HfO2 layer in a-ITZO TFT based on the double-layered dielectric. Therefore, the several analyses were implemented through numerical simulation of the device by the Silvaco TCAD Atlas software that was used to carry out a detailed numerical analysis for investigating the relationship between different types of the interfacial (low-k and high-k)dielectric oxides and the performance of a-ITZO TFT. The results showed that TFT based on the double-layered dielectric (Al2O3/HfO2) with a physical thickness ( $${\text{PT}}=30\,{\text{nm}}$$ ) it can provide good electrical properties ( $${\text{EOT}}=6.33\,{\text{nm}}$$ , $${C_{\text{i}}}=5.45 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=1.61 \times {10^{ - 5}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=1.56 \times {10^9}$$ and $${\mu _{{\text{FE}}}}=24.11\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ) better than the properties provided by TFT based on the double-layered dielectric (SiO2/HfO2) for the same physical thickness ( $${\text{EOT}}=12.23\,{\text{nm}}$$ , $${{\text{C}}_{\text{i}}}=2.82 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=8.54 \times {10^{ - 6}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=8.27 \times {10^8}$$ and $${\mu _{{\text{FE}}}}=29.31\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ). However, we cannot neglect the fundamental role of the interfacial low-k SiO2 layer between the channel and the high-k dielectric, which has some beneficial qualities with regard to the carrier mobility in the transistor channel. In addition, although there is a difference in the value of leakage between the two devices, its effect is very poor on the performance of the device and its reliability, especially for low gate tensions.

(Invited) High Performance Amorphous In-W-Zn-O Thin Film Transistor with Ultra-Thin Active Channel for Low Voltage Operation

Amorphous indium tungsten zinc oxide (a-IWZO) ultra-thin film TFTs (UTFTs) have been successfully fabricated and demonstrated in this work. Tungsten oxide (WO3)-doped indium zinc oxide was developed because WO3 doping can form stable semiconducting films with various carrier mobilities and carrier concentration. The novel IWZO UTFTs with high-κ HfO2 gate insulator exhibit superior potential for the power-saving applications of flat panel displays (FPDs), flexible electronics, and large scale integration (LSI) technologies owing to its outstanding characteristics of low threshold voltage ~ -0.072 V, high mobility ~ 23.8 cm2/V-s, excellent subthreshold swing ~ 72.6 mV/dec., low voltage operation (low power consumption), high electrical reliability, and small hysteresis.

(Invited) High Performance Amorphous In-W-Zn-O Thin Film Transistor with Ultra-Thin Active Channel for Low Voltage Operation

Amorphous indium tungsten zinc oxide (a-IWZO) ultra-thin film TFTs (UTFTs) have been successfully fabricated and demonstrated in this work. Tungsten oxide (WO3)-doped indium zinc oxide was developed because WO3 doping can form stable semiconducting films with various carrier mobilities and carrier concentration. The novel IWZO UTFTs with high-κ HfO2 gate insulator exhibit superior potential for the power-saving applications of flat panel displays (FPDs), flexible electronics, and large scale integration (LSI) technologies, owing to its outstanding characteristics of low threshold voltage ~ -0.072 V, high mobility ~ 23.8 cm2/V-s, excellent subthreshold swing ~ 72.6 mV/dec., low voltage operation (low power consumption), high electrical reliability, and small hysteresis.

C-V and J-V investigation of HfO2/Al2O3 bilayer dielectrics MOSCAPs on (100) β-Ga2O3

In this letter, MOS capacitors with bilayer dielectrics consisted of large bandgap Al2O3 and high-k HfO2 in different stacking order on n-type doped (100) β-Ga2O3 are investigated through C − V and J − V measurement. The C − V measurement results reveal that incoming HfO2 makes both bilayer structures attain an increasing dielectric constant, which means a better gate control ability in transistors comparing with single Al2O3. Additionally, the interface state density extracted by high-low frequency capacitance method suggests that Al2O3/(100)β-Ga2O3 with no treatment shows a comparative Dit value (8.0 × 1012 cm-2eV-1 to 2.2 × 1011 cm-2eV-1) with HfO2/(100)β-Ga2O3 (8.4 × 1012 cm-2eV-1 to 1.0 × 1011 cm-2eV-1) in energy range of 0.2 to 0.9 eV. Furthermore, HfO2/Al2O3/Ga2O3 showing a bigger forward breakdown voltage of 11.0 V than 7.8 V of Al2O3/HfO2/Ga2O3 demonstrates that inserted larger bandgap Al2O3 insulator between Ga2O3 semiconductor and high-k HfO2 dielectric can prevent gate leakage current more effectively. Accordingly, the HfO2/Al2O3/Ga2O3 can enhance gate control ability with an acceptable gate breakdown voltage and become an alternative choice in the design of the gate structure for Ga2O3 MOSFETs.

Enhancement of SSE-LED Light Emission By Embedding CdS in Zr-Doped HfO2 High-K Film

White light emission from the solid-state incandescent light emitting device (SSI-LED) has been reported and studied [1-4]. This kind of device is made of a metal-oxide-semiconductor (MOS) structure composed of a thin high-k dielectric film on the p-type Si substrate [1-4]. Nano-sized conductive paths are formed from the dielectric breakdown process. Light is emitted from the passage of the current through the conductive paths according to the blackbody emission principle [4]. Since the complete device is made with IC-compatible materials and processes, among many possible application, it is a potential light source for the on-chip optical interconnect [5]. The light emission efficiency of the SSI-LED can be enhanced by embedding a layer of nc-ZnO, nc-CdSe, WOx, etc. into the high-k dielectric [1,4,6]. In this paper, authors investigated the light emission enhancement phenomenon of the CdS embedded Zr-doped HfO2 (ZrHfO) high-k film dielectric. The ZrHfO/CdS/ZrHfO tri-layer was sputter deposited on a p-type Si <100> (1015 cm-3) wafer by one pump down without breaking the vacuum. The ZrHfO films were deposited from a ZrHf (12/88 wt. %) target under Ar/O2 (1:1) at 5 mTorr and 60 W, i.e., 2 min for the bottom layer and 10 min for the top layer. The CdS layer was deposited from a CdS target in Ar at 5 mTorr and 60 W for 3 min. The sample was annealed at 900°C in N2 for 3 min. Then, the ITO film was deposited on the high-k stack and etched into gate electrodes. The complete device was finished after depositing an Al layer on the back of the wafer followed by annealing at 300°C for 5 min in H2/N2. For the comparison purpose, a control sample, i.e., without the embedded CdS layer in the ZrHfO film, was prepared. Light emission patterns and spectra of the SSI-LED were measured at different gate voltages (Vg ’s). Figure 1 shows the top-view light emission patterns of the control and CdS embedded devices stressed at Vg = -50 V. Discrete bright dots are uniformly distributed across the gate electrode region. Each dot corresponds to a conductive path in the dielectric layer. The CdS embedded sample contains more dots than the control sample does. It was reported that the breakdown strength of the high-k stack decreased markedly with the including of the CdS layer because of the introducing of additional defects [7]. Thus, the CdS embedded sample is much easier to form conductive paths through the high-k thin film under the same Vg stress. Figure 2 shows the light emission spectra graph of the control and CdS embedded samples stressed at Vg = -50 V. Both spectra cover the same wavelength range including the visible and some of the near IR wavelengths. The shape and the peak wavelength, i.e., near 700 nm, of the emission spectrum are little influenced by the existing of the CdS layer. Therefore, the light emission principle in the two device are the same, i.e., thermal excitation of conductive paths. The CdS embedded SSI-LED has a much higher light intensity than the control SSI-LED has, which is consistent with the result of Fig. 1. The more nano-resistors are formed, the stronger light is emitted from the SSI-LED. Based on the spectra in Fig. 2, the CIE color coordinates, color correlated temperature (CCT), and color rendering index (CRI) values were calculated and listed in Table 1. The CdS embedded sample has slightly higher CCT and CRI Ra values than the control sample has, which is due to the higher local temperature in the former. The leakage current of the CdS embedded device is larger than that of the control sample. In summary, the embedding of CdS into the ZrHfO high-k dielectric enhanced the light emission properties of the SSI-LED through increases of the number of conductive paths and the leakage current in the structure. [1] Y. Kuo et al, APL, 102, 031117 (2013). [2] Y. Kuo et al, ESSL, 2, Q59 (2013). [3] Y. Kuo et al, SSE, 89, 120 (2013). [4] C.-C. Lin et al, APL, 106, 121107 (2015). [5] S. Zhang et al, ECS JSS, 6 (4), Q39, 2017. [6] S. Zhang et al, ECST, 66 (4), 195 (2015). [7] S. Zhang et al, IEEE TDMR, 16 (4), 561 (2016). Figure 1

Enhancement of SSI-LED Light Emission by Embedding CdS in the Zr-Doped HfO2 High-k Film

Light emission improvement of the solid state incandescent light emitting devices by embedding CdS into the Zr-doped HfO2 high-k dielectric has been studied. Compared with the capacitor with the Zr-doped HfO2 gate dielectric, the CdS embedded sample have: 1) higher defect densities in bulk and interface layers, 2) a smaller breakdown strength, 3) a larger leakage current, 4) more light emission dots, and 5) a higher light emission intensity. The spectrum shape and color of the emitted light were influenced by the inclusion of CdS in the high-k stack. The light emission efficiency was also enhanced. The improvement might be caused by the change of the nano-resistor composition. In summary, the embedding of CdS influences the high-k stack’s physical properties, which affects the formation of nano-resistors and the device’s light emission characteristics.

Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V−1 s−1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec−1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson’s equation and Young’s approximation. Based on this electric field expression, tunneling current is obtained by using Kane’s model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.