High-k Gate Dielectric Stacks Research Articles

Arsenic penetration behavior and electrical characteristics of As-doped n+ polycrystalline-silicon/high-k gate dielectric (HfO2 and Al2O3) films on Si (100) substrate

Arsenic (As)-doped polycrystalline-silicon gate/HfO2, HfO2–Al2O3, or Al2O3–HfO2–Al2O3/p-type Si (100) metal–oxide–semiconductor capacitors were fabricated using an atomic-layer-deposition technique to investigate the degree of As penetration and the electrical properties of various high-k gate dielectric stacks. The HfO2–Al2O3 stack film showed the highest resistance to As diffusion due to the presence of a rather thick amorphous interface layer. A flatband voltage shift of 100 mV, a leakage current density of −1.07×10−9 A/cm2 at −1 V, a hysteresis voltage <60 mV and excellent reliability characteristics were obtained from this capacitor stack due to the lowest As penetration, less generation of the interface state density, and the lowest surface roughness. Thin Al2O3 capping did not improve the As-diffusion barrier properties due to its island-like surface morphology.

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si/sub 3/N/sub 4//SiO/sub 2/, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement.