High-k Gate Dielectric Stacks Research Articles

A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks

Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO2/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.

Ultralow-Power Synaptic Transistor Based on Wafer-Scale MoS2 Thin Film for Neuromorphic Application

In the next-generation computing framework, synaptic devices modulated using analogue weight storage are expected with capability of performing neuromorphic computing tasks. Recently, 2D transition metal dichalcogenides (TMDCs) based solid-state devices have demonstrated excellent electrical performance showing great potential in nanoscale synaptic electronics. In this letter, artificial synaptic transistors are proposed and fabricated on the atomic layer deposited 2D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thin film with an integrated high-k dielectric gate stack. The synapse cells can simulate fundamental synaptic functions similar to those of biological synapses, such as long-term potentiation and depression. Moreover, the ultralow power consumption shows that the proposed synapse is more efficient than most three-terminal synaptic transistors. We also emulate a multi-synapse network to demonstrate intrinsic heterogeneity in biological brain. The experimental results have validated the feasibility of synaptic devices based on 2D TMDCs and have contributed a promising approach to the development of the next-generation brain-like neuromorphic systems.

Improvising the Switching Ratio through Low-k / High-k Spacer and Dielectric Gate Stack in 3D FinFET - a Simulation Perspective

This paper extensively studies the spacer technology, including low-k/high-k, single/dual dielectrics on the device performances focusing on the leakage current. The tactical use of a spacer, introduction of a low bandgap material as a pocket on the source side along with the incorporation of gate dielectrics helped in improving the switching ratio effectively. A systematic comparison is made in between the conventional symmetrical single low-k spacer 3D FinFET and the proposed optimized 3D FinFET. Various device architectures are evaluated by showing significant improvements in on current (Ion) and off state leakage (Ioff), leading to a high switching ratio (Ion/Ioff) and the subthreshold slope (SS). An Ion/Ioff of value 1 × 106 indicates sufficient electrostatics to control over the channel, and our study results in ~8 time of this value. These parameters are obtained after the appropriate selection of low-k & high-k spacer length on both sides of the source and drain. The use of SiGe material near the source side to modulate carrier mobility and incorporating high-k gate dielectric to suppress leakage.

Implementation of Synaptic Device Using Various High-k Gate Dielectric Stacks.

We investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based fieldeffect transistor (FET)-type memory device. An Al₂O₃/HfO₂/Si₃N₄/SiO₂ gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si₃N₄ and HfO₂ layers are designed to charge trap layer for synaptic device. The mechanism of STP and LTP operation is analyzed by considering the device response to the potentiation and depression pulses and retention measurement of the memory functionality. To investigate the STP operation, paired pulse facilitation (PPF) measurement is performed. The retention characteristic is also studied to validate the LTP property of the device. By investigating a device with an Al₂O₃/HfO₂/Si₃N₄ stack as a control device, it is shown that the Al₂O₃/HfO₂/Si₃N₄/SiO₂ stack device is suitable for a synaptic device in neuromorphic systems.

(Invited) Dielectric Science on Today's Devices

The trends of various high-k gate dielectrics deposited on silicon or germanium is reviewed for logic and memory devices. Initially, Zr and low percentage of Al incorporation into HfO2-based high-k dielectrics gate stack on silicon through different process conditions were outlined. Subsequently, high-k gate stack deposition process on Ge was evaluated to form a stable Ge/high-k interface. We have also looked at the high-k gate dielectric stacks in a MIM capacitor for possible applications in memory and AI hardware.

Investigation of Positive Bias Temperature Instability Characteristics of Fully Depleted Silicon on Insulator Tunneling Field Effect Transistor with High-k Dielectric Gate Stacks.

The positive bias temperature instability (PBTI) characteristics of fully depleted silicon on insulator (FD-SOI) tunneling field effect transistor (TFET) are investigated in comparison with those of metal oxide semiconductor field effect transistor (MOSFET) fabricated with the same technology process. Unlike some of the previously reported studies, in which the PBTI lifetime of TFET is much longer than that of MOSFET, in this study, the PBTI lifetime of TFET is found to be shorter than that of MOSFET. This result is very interesting, because degradation of electrical parameters of TFET is mainly affected by local traps near the source junction rather than global traps in the channel region. Large degradation of the electrical parameters of TFET due to PBTI stress would result from large fluctuation of the vertical electric field caused by traps near the source junction. This electric field fluctuation near the local region in TFET has more impact on electrical parameter degradation than channel conductivity fluctuation in MOSFET. Therefore, to improve the reliability characteristics of TFET, evaluation of PBTI characteristics and improvement of the quality of gate oxide near the source junction are essential.

Charge trapping effect in HfO2-based high-k gate dielectric stacks after heavy ion irradiation: The role of oxygen vacancy

The charge trapping effect of HfO2 gate stacks under heavy ion irradiation was evaluated via capacitance-voltage (C-V) measurement and transmission electron microscopy (TEM). Ion irradiation introduced oxygen vacancies into the HfO2 dielectric layer, which located primarily at the interface between HfO2 and Si. The oxygen vacancies act as trapping centers dominating the degradation of device performance after irradiation. The role of the traps on charge trapping in HfO2 gate stacks and the trapped charge stability (i.e. detrapping process) as a function of time were also investigated in this work. The mechanism of how MOS capacitors are affected by irradiation provides a good foundation for future space application of HfO2 gate stacks based integrated circuits.

Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.

Atomic Layer Deposition in the Production of a Gate HkMG Stack Structure with a Minimum Topological Size of 32 nm

The plasma-enhanced atomic layer deposition (PEALD) of a High-K Dielectric and Metal Gate (HkMG) stack for MIS transistors, including the subgate HfO2 (2–4 nm) dielectric layer, the ultrathin metallic stabilizing hafnium nitride HfN (1–3 nm) layer, and the basic metallic gate layer from tantalum nitride ТаN (10–20 nm), on silicon plates with a diameter of 200 mm is studied. The spectral ellipsometry method is applied to measure the homogeneity of the deposited film thickness. The dielectric constant of the dielectric in the stack, the leak current, and the breakdown voltage are examined. The four-probe method is used to study the specific electric resistance of tantalum nitride deposited by the atomic layer deposition ALD method. The film thickness homogeneity as a function of the ALD process parameters is examined. The specific resistance of the metallic TaN layer as a function of the composition and parameters of the plasma discharge are studied.

Improved thermal stability and electrical properties of atomic layer deposited HfO2/AlN high-k gate dielectric stacks on GaAs

The thermal stability and electrical properties of atomic layer deposited HfO2/AlN high-k gate dielectric stacks on GaAs were investigated. Compared to HfO2/Al2O3 gate dielectric, significant improvements in interfacial quality as well as electrical characteristics after postdeposition annealing are confirmed by constructing HfO2/AlN dielectric stacks. The chemical states were carefully explored by the x-ray photoelectron spectroscopy, which indicates the AlN layers effectively prevent from the formation of defective native oxides at elevated temperatures. In addition, it is found that NH3 plasma during AlN plasma-enhanced atomic layer deposition also has the self-cleaning effect as Al(CH3)3 in removing native oxides. The passivating AlN layers suppress the formation of interfacial oxide and trap charge, leading to the decrease of capacitance equivalent thickness after annealing. Moreover, HfO2/AlN/GaAs sample has a much lower leakage current density of 2.23 × 10−4 A/cm2 than HfO2/Al2O3/GaAs sample of 2.58 × 10−2 A/cm2. For the HfO2/AlN/GaAs sample annealed at 500 °C, it has a lowest interface trap density value of 2.11 × 1011 eV−1 cm−2. These results indicate that adopting HfO2/AlN dielectric stacks may be a promising approach for the realization of high quality GaAs-based transistor devices.

Post Deposition Annealing Temperature Effect on White-Light Emitting of WOx Thin Film Stack on Si

Post Deposition Annealing Temperature Effect on White-Light Emitting of WOx Thin Film Stack on Si

Nonvolatile memories based on AlOx embedded ZrHfO high-k gate dielectric

ABSTRACTMOS capacitors with the ZrHfO/AlOx/ZrHfO high-k gate dielectric stack were prepared and characterized for memory functions. The device prefers to trap holes, i.e., under the negative gate voltage, rather than electrons, i.e., under the positive voltage. The hole-trapping process is time and voltage dependent. The weakly trapped holes are quickly released upon the remove of the stress voltage. However, more than 30% of the originally trapped holes can be retained in the device after 10 years. The AlOx embedded ZrHfO high-k stack is a suitable gate dielectric structure for nonvolatile memories.

Enhanced leakage current properties of HfO2/GaN gate dielectric stack by introducing an ultrathin buffer layer

The band alignments of HfO2/GaN, HfO2/SiO2/GaN and HfO2/Al2O3/GaN gate dielectric stacks were comparatively investigated by using X-ray photoelectron spectroscopy. It was observed that the introduction of an ultrathin buffer layer film (SiO2 or Al2O3) in HfO2/GaN stack can make the band alignments more symmetrical with larger barrier height as identified by the valence band offsets and electron energy loss spectrum measurements. At room temperature, the leakage current density as function of temperature is 4.1 × 10−6, 3 × 10−7 and 9.8 × 10−8 A cm−2 at the bias of 1 V for the HfO2/GaN, HfO2/Al2O3/GaN and HfO2/SiO2/GaN gate dielectric stacks, correspondingly. With temperature increase from room temperature to 300 °C, the HfO2/SiO2/GaN gate dielectric stack exhibits lowest lower leakage current density than that of others. The HfO2/GaN high-k gate dielectric stack with an ultrathin SiO2 buffer layer appears to be a promising candidate for future GaN based high temperature metal-oxide-semiconductor (MOS) devices applications.

CdSe Embedded ZrHfO Gate Dielectric Nonvolatile Memories – Charge Trapping and Breakdown Studies

MOS capacitors composed of nc-CdSe embedded ZrHfO high-k gate dielectric stacks were fabricated and investigated on the charge trapping and breakdown mechanisms. The interface layer between the high-k film and Si wafer was transformed to a more SiO2-like HfSixOy group after the inclusion of nc-CdSe layer. The frequency-dependent conductance-voltage measurement result shows that part of the trapped charges were loosely trapped at the nc-CdSe/ZrHfO interface and easily tunneled back to the Si substrate under low frequency measurement condition. Compared with the control sample, the nc-CdSe embedded sample has a larger leakage current and a higher breakdown voltage due to the formation of new leakage paths and a larger physical thickness. The trapped charges can be retained in the nc-CdSe site after the breakdown of the high-k film.

Backside medium energy ion scattering study of the lanthanum diffusion in advanced gate stacks for the 32 nm node

The insertion of a La2O3 capping layer in high-k gate dielectric stacks is a solution for tuning the threshold voltage in nMOSFETs devices. We have investigated TiN/ LaOx/HfSiON/SiON on Si(001) gate stacks by medium energy ion scattering to determine the La in-depth distribution and highlight the impact of spike-annealing after the complete deposition sequence. A dedicated method of preparation combining both mechanical and chemical thinning of the silicon substrate is applied prior to backside analysis. Results show that lanthanum is the main diffusing element after annealing.

Analysis of Charge-Pumping Data for Identification of Dielectric Defects

We introduce a data analysis methodology for multifrequency charge-pumping (CP) measurements, which allows extracting both spatial and energy profiles of the CP-active traps in the gate dielectrics along with the defect energy characteristics. The analysis is based on the charge trapping/detrapping model accounting for carriers tunneling between the substrate and the oxide traps and multiphonon-assisted structural trap relaxation associated with charge carrier localization in the trap. Comparison of the spatial and energy trap distribution profiles obtained from CP data collected on a set of high-k dielectric gate stacks of different thicknesses facilitate the calibration of the model parameters. Extraction of the bulk trap characteristics, including trap ionization and relaxation energies, extends the utility of the CP technique from quantifying defect density toward identifying the nature of defects in the dielectric.

Effect of the Interfacial SiO2 Layer on High-k Gate Stacks

Interfacial oxide (IL) /high-k (HK) gate dielectric stack is widely used in 45nm logic technology and beyond nodes. Interfacial oxide, which is buffer layer between silicon substrate and HK dielectric, is a crucial factor to control Silicon/IL, IL/high-k interface charge and high-k film quality. In this work, atom layer deposition (ALD) Hf based HK film is deposited on two classes of IL by thermal oxidation (process A or B) and chemical oxidation (process C or D), respectively. XPS is used to characterize the film bonding energy, while non contact CV and spectroscopic ellipsometry (SE) are used to characterize the interface trap. The electric properties of the film stacks are characterized by C-V and I-V curves. The results reveal that interface trap of chemical oxide film has positive surface voltage and less dense SiOx, as compared with that of thermal oxide. With the same interfacial oxide thickness and HK deposition process, the chemical oxide/HK stack got 3.4A thick EOT, which is about two orders lower leakage than that of thermal oxide/HfO2. It can be explained by the fact that chemical oxide had plenty of O-H bonds, which is good for ALD Hf based HK film nucleation and growth and resulted in good film quality. However, due to the high Si/chemical oxide interfacial charge, the chemical oxide/HfO2 dielectric stack has a disadvantage of the larger C-V hysteresis.

Nonvolatile memory MOS capacitors made of CdSe embedded ZrHfO high-k gate dielectric

ABSTRACTMOS capacitor composed of nc-CdSe embedded ZrHfO high-k gate dielectric stack was fabricated and characterized for nonvolatile memory functions. Detailed material and electrical properties have been investigated. With a large charge trapping capability, this kind of device can trap electrons or holes depending on the polarity and magnitude of the applied gate voltage. For the same stress time, the device trapped more holes than electrons under the same magnitude of gate voltage but different polarity. The negative differential resistance peak was observed at the room temperature due to the Coulomb blockade effect. The charge trapping mechanism was delineated with the constant voltage stress test. After 10 years of storage, about 56% of trapped charges still remain in the device.

Flicker noise in n-channel nanoscale tri-gate fin-shaped field-effect transistors

In n-channel nanoscale tri-gate fin-shaped field-effect transistors with high-k gate dielectric stack, the 1/f noise is investigated, ascribed to the carrier number fluctuations with correlated mobility fluctuations. The overall results show that the gate dielectric trap density is uniform in both top-gate and side-gates and the product Ω=αscμeffCox of the Coulomb scattering coefficient αsc, the effective carrier mobility μeff and the gate oxide capacitance per unit area Cox increase with decreasing the fin thickness due to enhancement of side-gates interface roughness effects.

Variable charge many-body interatomic potentials

Abstract