High Gate Count Research Articles

A new realization scheme for dynamic PFSCL style

In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the issue by proposing a scheme which modifies the structure of a D-PFSCL gate. The modified gate exhibits AND/OR functionality and is used to realize various functions. Simulations have been carried out by implementing various functions and comparing their performance with the existing schemes at 1 GHz. The results of performance comparison with existing schemes indicates significant reuduction in gate count resulting in overall performance improvement.

High-level parameterizable area estimation modeling for ASIC designs

Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.

Delayed Single-Tap Frequency-Domain Chromatic-Dispersion Compensation

A long-haul transmission of 100 Gb/s without optical chromatic-dispersion (CD) compensation provides a range of benefits regarding cost effectiveness, power budget, and nonlinearity tolerance. The channel memory is largely dominated by CD in this case with an intersymbol-interference spread of more than 100 symbol durations. An efficient implementation of digital CD compensation is feasible by frequency-domain (FD) filtering. Still the large size of the Fourier transform requires a high gate-count and a large chip size. We propose a new FD filtering on the basis of a nonmaximally decimated discrete Fourier transform filter bank with a trivial prototype filter and a delayed single-tap equalizer per sub-band. This method, which can be regarded as an extension to the popular overlap-save method, allows us to increase the CD tolerance drastically. At the same time, the implementation complexity is not altered apart from adding simple memory elements realizing sub-band delays. With this technique, the uncompensated trans-Pacific transmission becomes feasible with the digital CD compensation.

Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizing

The authors are concerned with the optimisation of combinational logic circuits. The competing factors, active area and delay time, are considered in the optimisation. The total active area is assumed to be a linear function of the gate sizes. There is a critical path whose delay time, the longest delay time of the circuit, depends on the sizes of the individual gates. This path will change many times during the optimisation. The optimisation process is used to produce the trade-off curve. The proposed methodology is based on the optimisation of the circuit critical path. This is a gate sizing problem on those paths that define the delay time of a circuit. Given a drive size for all the gates of the circuit, the trade-off curve contains design space points of minimum delay time and active area. A variable-sized subset of the Boolean network is optimised. Only the gates in the circuit critical path are optimised. The gates in the Boolean network which are not in the critical path do not need to be optimised. An efficient method is proposed for updating the critical path as the trade-off curve is obtained. Performance comparison and results were obtained over the set of MCNC two-level and combinational multilevel benchmark circuits. The proposed methodology produces trade-off curves, in relatively large circuits, with a great reduction in number of variables and run-time compared with the original full problem. In the proposed method, the number of variables is reduced by a factor of up to 7.3 times relative to the original full problem. The run-time behaviour is excellent, with an improvement between 1.5 and 32.5 times less CPU time compared with computation of the full Boolean network. With a higher gate count of the circuit, there are greater improvements in both run-time and number of variables.

A general-purpose VME module

A general-purpose Versa Module Europa (VME) module has been developed for trigger and DAQ application. It takes advantage of the flexibility of field programmable gate arrays (FPGAs) and the modularity of personality cards. It can perform different functions without hardware modification simply by changing the design of the firmware in the FPGA. Higher gate-count FPGAs can also be used for more complex logic applications. The personality card is mainly used for adapting TTL to various level standards at the front panel. A personality card, featuring a 12-bit DAC and analog switch that generates calibration pulses, has also been designed. An example of FPGA program for a "4-channel 16-bit scaler" is also presented in this paper. The concept of a general-purpose VME module can also be extended to CAMAC, cPCI (compact peripheral component interconnect), or other modular standards. Several logic functions can be combined in one module, which is especially useful for trigger and DAQ control of a small experiment.

Reliability measurement of microprocessors based on functional testing

Growing density and high gate count of todays VLSI-circuits impose strong limitations on classical methods to determine the reliability of these circuits /1,2,3,4/. In order to overcome this problem and to include all effects which are due to the functionality of a complex circuit and all parasitic phenomena given by timing, technology etc. /5/,a method to measure reliability of microprocessors on a functional basis is described. The instruction set of the device is used as description. Applying stimuli and comparison of responses is done by a functional self-test program. A small test equipment is used for control of the self-testing procedure and the setting of parameters.