High-frequency Jitter Tolerance Research Articles

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE

A digital clock/data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) and a calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1 mm2. For a channel loss of -10.31dB at 10GHz and a 20Gb/s PRBS of 27-1, the measured bit error rate is less than 10-12. By the proposed calibration circuit, the measured high-frequency jitter tolerance is improved. The measured convergence time of the calibration circuit is less than 5μs. The power of this CDR circuit is 55.4mW at 20 Gb/s, and the calculated energy efficiency is 2.77pJ/b.

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with <10−12 bit-error rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm2 in a 28-nm CMOS technology.

An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits

This article presents the theoretical analyses and experimental results about jitter tolerance for delay-locked loop (DLL)-based clock and data recovery (CDR), which is generally used in an embedded clock serial link. From the proposed S-domain model, we prove that DLL-based CDR has superior low-frequency jitter tolerance than PLL-based CDR, whereas, assuming the ideal case, high-frequency jitter tolerance of DLL-based CDR is only a half of that of PLL-based CDR. In addition, the jitter tolerance characteristics of both PLL- and DLL-based CDRs are analyzed in a practical environment. Finally, the consistency of analysis is verified from measurement results using 2.7-Gb/s enhanced reduced-voltage differential signaling (eRVDS) receiver.

A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance

A 5-Gb/s digital clock/data recovery (DCDR) circuit with spread-spectrum clocking (SSC) capability and enhanced high-frequency jitter tolerance (JTOL) is presented. To track input data with both the frequency offset and the SSC, an integral gain controller is used to adjust an integral gain of the digital loop filter. It enhances the high-frequency JTOL. This DCDR circuit is fabricated in 40nm CMOS process. Its active area is 0.022mm2 and the power consumption is 9.9mW from a 1 V supply. With a 5-Gb/s PRBS of 27-1, the measured rms jitter of the retimed data is 9.47ps. For input data with the frequency offset of ±300ppm and SSC of -5000ppm, the measured minimum high-frequency JTOL is equal to 0.55 UIpp by using the proposed integral gain controller with a bit error rate (BER) $ .

Referenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique

A referenceless single-loop clock and data recovery (CDR) circuit with a half-rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle-slip in the half-rate linear PD and its relationship with the frequency acquisition are described in detail. The single-loop CDR consists of a conventional phase-tracking loop and a frequency-tracking unit, referred to as the cycle-slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak-to-peak jitter of the recovered clock are and , respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as . The CDR occupies and consumes 26 mW at 8 Gb/s from a 1.0 V supply.

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in $5~\mu$ s

A 16 Gb/s 1-tap Infinite impulse response (IIR) + 1-tap discrete-time (DT) decision feedback equalizer (DFE) with integrated clock recovery and adaptation is demonstrated in 28 nm FD-SOI CMOS. Using a CMOS phase rotator, 0.7 unit interval (UI) high-frequency jitter tolerance is achieved when operating mesochronously, and over 0.4 UI operating plesiochronously. The half-rate architecture includes a novel 2:1 multiplexer to reduce delay in the IIR feedback path. With a 28 dB loss channel, a BER below $10^{-12}$ is measured over a 0.32 UI timing window with a TX swing of 0.8 Vpp-diff. Using a 2 Vpp-diff TX swing, a 30 dB loss channel has a measured BER below $10^{-12}$ over a 0.3 UI timing window. A novel edge-based algorithm adapts both IIR and DT equalizer coefficients using the same high-speed circuitry and signals required for clock recovery. The algorithm utilizes all transitions to inform the adaptation of all equalizer coefficients, thereby providing faster convergence than previously-reported algorithms which await specific patterns. Moreover, the adaptation freezes automatically unless a diverse set of data patterns is received, thereby making the algorithm robust in the presence of poorly-conditioned data. The adaptive DFE converges within $5~\mu \text{s}$ .

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UI $_{\mathrm { {pp}}}$ at 100 MHz with $ BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UI $_{\mathrm { {pp}}}$ at 300 MHz with $ BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm $^{\mathrm { {2}}}$ in a 0.13- $\mu \text{m}$ CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.

A 3x blind ADC-based CDR for a 20 dB loss channel

This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3x the baud rate. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our test chip fabricated in Fujitsu's 65 nm CMOS show a high frequency jitter tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60 FR4 channel.

4×, 3‐level, blind ADC‐based receiver

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of <10 − 12 at 5 Gbit/s with a high-frequency jitter tolerance of 0.39 and 0.31 UIpp for a 9.3 and a 12.9 dB FR4 channel, respectively. The entire receiver consumes 63 and 86 mW for the respective channels.

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5–11.5 Gb/s Serial Links

This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5–11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A common programmable gain amplifier (PGA) with programmable peaking is followed by ADC-based and slicer-based paths. The ADC-based path employs a low-power, 6-bit 10 Gs/s, 4X time-interleaved, low BER rectified flash 10 Gs/s ADC that is digitally calibrated to compensate for offset, gain, and phase mismatches between the interleaved channels. The ADC-based receiver with transmitter can compensate for up to a 34 dB insertion loss at 5 GHz Nyquist frequency for a copper backplane channel (10GBASE-KR). The ADC-based receiver can achieve greater than 6 dB margin for three 10GBASE-LRM stressors and dynamic channels. The ADC Figure of Merit (FoM) is a 0.59 pJ/conversion-step for a 5 GHz input at a 10.3125 GHz clock rate. The slicer-based path uses a continuous-time linear equalizer (CTLE) after high linear PGA to provide 10 dB total equalization at 5 GHz Nyquist frequency for 10GBASE-SR application. Its measured input sensitivity of 30 mVppd and high-frequency jitter tolerance of 0.35 UIpp with 0.7 UIpp total input jitter well exceed specifications in the standard. The receiver AFE occupies 0.82 mm 2 and consumes 195 mW for ADC path and 55 mW for slicer path in a 40 nm standard CMOS process.

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Blind Baud-Rate ADC-Based CDR

This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made possible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller–Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency jitter tolerance of 0.19 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{UI}_{\rm PP}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm \hbox{300 ppm}$</tex></formula> of frequency offset.

An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital quadricorrelator frequency detector (M-DQFD) incorporated into an LC-based VCO coarse tuning adjustment. M-DQFD eliminates the dead-zone problem associated with high dispersion and low SNR links. Fabricated in 65-nm CMOS process, the transceiver complies with stringent OC-192 jitter requirements. With a 400- μs acquisition time, the receiver achieves a high-frequency jitter tolerance of 0.58UIpp at 10-mVppd input sensitivity. The transmitter output exhibits a random jitter of 205fsrms. The transceiver occupies 0.97 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 125 mA at 1.0-V supply voltage.

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> RJ, 0.8 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> DJ, and a ±0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20-27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> input sensitivity and a 0.7-UI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> RJ, and 2 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 214 mW.

Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs

An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18- μm CMOS process, and a bit error rate of less than 10-12 was achieved for a data rate up to 5.8 Gb/s using a 231 - 1 pseudorandom binary-sequence input.

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order $\Delta\Sigma$ Modulator in 90-nm CMOS

A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advantages of a digital CDR such as low power consumption, small area, fast locking time, and low-jitter recovery clock because no internal VCO is needed. The CDR tracking bandwidth is 20 MHz and high-frequency jitter tolerance is 0.42 UIpp at 10-12 BER. Power consumption of LPD is 2.6 mW while the entire receiver consumes 65 mW.

A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10-12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 215 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ulpp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ulpp by applying PRBS data with a pattern length of 231 - 1.

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

A hybrid CDR is presented that embeds a 5 blind-oversampling CDR within a conventional phase-tracking CDR. This hybrid CDR has a jitter tolerance that is the product of the individual jitter tolerances. In this implementation, the jitter tolerance of a phase-tracking CDR alone is increased by a factor of 32 at frequencies below its loop filter's bandwidth, while maintaining the high-frequency jitter tolerance of a 5x blind-oversampling CDR. Measured data from a 0.11 mum CMOS test chip at 2.4 Gb/s confirm a 200 UI peak-to-peak jitter tolerance for a 200 kHz jitter. The test chip operates from 1.9 Gb/s to 3.5 Gb/s with a BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> , consuming 115 mW at 2.4 Gb/s.