High Electric Field Stress Research Articles

Physical and Electrical Properties of Yttrium Oxide Gate Dielectrics on Si Substrate with NH3 Plasma Treatment

We report on the physical properties and electrical characteristics of gate oxides grown on silicon substrates with plasma treatment by reactive radio-frequency sputtering. The interfacial chemistry of the high-k gate dielectric has been investigated on nitrided and un-nitrided Si using X-ray photoelectron spectroscopy. We found that the gate film having -based interface layer is very effective in reducing equivalent oxide thickness and leakage current as well as improving film qualities. This -nitrided layer is suggested to minimize interfacial formation by limiting the amount of Si available to interact with the layer. These gate dielectrics exhibit excellent frequency dependence and weak temperature dependence of leakage current. They also show negligible charge trapping at high electric field stress.

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

A complete study of the defects created in the gate oxide and at the gate oxide/substrate interface of metal–oxide–semiconductor transistors with thick gate oxide ( t ox > 10 nm) during high electric field stress, and the mechanisms responsible for these defects creation have been given. In addition, some results of positive/negative high electric field stress with constant gate voltage of commercial n-channel power metal–oxide–semiconductor transistors with thick gate oxide of 100 nm, have been explained using this study.

Effect of deep levels and interface states on the minority carrier lifetime control of trench-IGBTs by electron irradiation

The relationship between the minority carrier lifetime and bulk defects and between this lifetime and the interface states due to 2 MeV electron irradiation were investigated using deep-level transient spectroscopy (DLTS) and the charge separation technique, respectively. There seems to be a correlation between the change in lifetime and the interface traps generated due to electron irradiation. For the same level of interface trap density after a fluence of 1×10 14 e/cm 2 electron irradiation due to Fowler–Nordheim (FN) high electric field stress, the lifetime did not changed. Due to the creation of a deeper state, which is probably a defect including V 2 and H with increasing electron fluence, the lifetime decreases further. It is thought that the Si–H bonds at the Si–SiO 2 interface are broken and dissociated hydrogen is introduced in the silicon bulk during the electron irradiation.

Electrical stresses on ultra-thin gate oxide SOI MOSFETs after irradiation

We present the first experimental data about the wear-out of a 0.1 /spl mu/m partially depleted SOI CMOS technology after heavy ion irradiation. We show that accelerated life tests based on high electric fields yield significant differences between irradiated and nonirradiated devices, even though no or only minor changes are visible in the characteristics of the devices after irradiation. First, the time to breakdown of the front gate oxide is significantly lower in the irradiated samples. The fresh devices experienced breakdown after 5-8/spl middot/10/sup 22/ electrons/cm/sup 2/ were injected across the oxide during high field electrical stress. In the irradiated oxide, the breakdown was reached at much lower injected charge values, between 0.5/spl middot/10/sup 22/ electrons/cm/sup 2/ and 1.5-1/spl middot/10/sup 22/ electrons/cm/sup 2/ depending on the ion fluences. This translates into a lifetime reduction of 10%-20% of its initial value. Furthermore, the degradation kinetics of the threshold voltage and transconductance peak are strongly affected by ion strikes. In particular, a sudden shift of the threshold voltage and an acceleration in the degradation of the transconductance peak were observed upon the application of an electrical stress, which have no correspondence in nonirradiated devices. An acceleration in the degradation of the parasitic back transistor was observed as well. These phenomena were interpreted in terms of latent damage left by the irradiation in the oxides that make up SOI devices.

Fowler–Nordheim high electric field stress of power VDMOSFETs

The analysis of defect generations in SiO 2 and at SiO 2/Si interface during positive/negative high electric field stress of commercial n-channel power VDMOSFETs has been given. Some additional experiments containing the gate bias switching have helped in these defects nature investigations. The combined application of midgap subthreshold technique and charge pumping technique have represented very useful tool for the switching trap behavior revealing. The fixed trap density (Δ N ft) and switching trap density (Δ N st) in two power VDMOSFET types during Fowler–Nordheim injections have shown different behaviors.

Defect behaviors in n-channel power VDMOSFETs during HEFS and thermal post-HEFS annealing

The results of positive/negative Fowler–Nordheim high electric field stress and thermal post-high electric field stress annealing of commercial n-channel power VDMOSFETs have been presented. They have shown that gate bias sign has an influence on the fixed trap behavior during high electric field stress, but has no influence on any defect type behavior during thermal post-high electrical field stress annealing. In addition, slow switching traps have different behavior, but fast switching traps have the same behavior during thermal post-high electrical field stress annealing and thermal post-irradiation annealing.

Effects of high-field electrical stress on the conduction properties of ultrathin La2O3 films

Electron transport in high-field stressed metal-insulator-silicon devices with ultrathin (<5nm) lanthanum oxide layers is investigated. We show that the leakage current flowing through the structure prior to degradation is direct and Fowler-Nordheim tunneling conduction, while that after stress exhibits diode-like behavior with series and parallel resistances. In this latter case, a closed-form expression for the current–voltage characteristic, based on the Lambert W function, is presented. Current evolution from one regime to the other during constant voltage stress takes place by means of discrete current steps of nearly identical magnitude, which would be indicative of the occurrence of multiple dielectric breakdowns across the insulating layer.

Electron trap distribution in thin oxide after high-field stress

The centroid of neutral electron trap distribution in 80 Å SiO2 film after high-field electrical stress is determined using trap-filling measurements that can eliminate the contributions from trapped holes and interface trapped charges—complications that introduce ambiguity in previous studies. The centroid is found to be roughly half way between the midpoint of the oxide and the injecting electrode, implying an extremely nonuniform distribution. Such a highly nonuniform distribution is at odds with the assumption used in most oxide breakdown models. The impact of a highly nonuniform neutral trap distribution on thin oxide reliability projection could be important.

A comparison of ionizing radiation and high field stress effects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors

n -channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (VDMOSFET) devices were subjected to a high electric field stress or to a x-ray radiation. The current-voltage and capacitance-voltage measurements show that the channel-side interface and the drain-side interface are affected differently in the case of high electric field stress, whereas the interfaces are nearly uniformly affected in the case of x-ray radiation. This paper also shows that for the gated diode structure of VDMOSFET, the direct-current current-voltage technique measures only the drain-side interface; the subthreshold current-voltage technique measures only the channel-side interface; and the capacitance-voltage technique measures both interfaces simultaneously and clearly distinguishes the two interfaces. The capacitance-voltage technique is suggested to be a good quantitative method to examine both interface regions by a single measurement.

Finite Element Modeling of Polarization Rotation Around an Elongated Elliptic Cavity

Electromechanical loading of piezoelectric devices with high electric field and mechanical stress concentrations near electrode and crack tips may lead to a localized inhomogeneous polarization switching response which is responsible for device degradation. We present an approximate constitutive law for polarization rotation of fully poled materials in load cases which do not initiate depolarization of the material. In other words, the local poling direction is changed but the material remains poled to saturation. The structure of the constitutive law resembles incremental plasticity theory: The “yield surface” is postulated, based on an energy criterion for 90°-switching of the randomly oriented crystallites in a material point, and the energy barrier of polarization switching corresponds to the yield stress. The constitutive model is implemented into the finite element code PSU and validated for the plane sample problem of an elongated elliptic cavity in a ferroelectric material. Some implications for crack shielding models are discussed.

Relation between dielectric and mechanical nonlinear behaviours in PZT piezoelectric ceramics

Elastic and dielectric coefficients of PZT piezoceramics are perturbed by applying high electric field or high mechanical stress. In this work, a procedure is described in order to compare non-linear dielectric and elastic behaviour, by using suitable quantities. Qualitative differences are observed between soft and hard materials. But, for a given material, dielectric and mechanic behaviours are very similar, as well as the losses of both kinds. This fact can be understood by assuming that non-linearity is produced by interaction between domain walls and defects, and that 180° walls are negligible in front of non-180 walls. Some facts must be taken into account in order to compare both behaviours, as the non-linear model, the domain wall orientation distribution, or the non uniformity of the fields. This allows to relate the non linear behaviour with the distribution function, that defines the material state, or to understand the non-linearity produced at the overtones.

Gate-oxide grown on the sidewalls and base of a U-shaped Si trench: effects of the oxide and oxide/Si interface condition on the properties of vertical MOS devices

We report on the SiO 2/Si interface condition and on its high electric field stress reliability in U-shaped trench gated metal-oxide-silicon (MOS) structures. The interface state density measured is ∼10 11 eV −1 cm −2, and using deep level transient spectroscopy the P b center is found to be the dominant interface defect. The degradation induced by electrical stressing is examined using changes in the charge pumping current in a U-trench-gated transistor. It is shown that the SiO 2/Si interface at the bottom corners of the trench is the weakest region in the MOS structure.

Characterization of the effects of applied electric fields on fracture toughness and cyclicelectric field induced fatigue crack growth for piezoceramic PIC 151

The influence of applied electric field on fracture toughness and cyclic electricfield induced fatigue crack growth behaviour was characterized for an actuatorpiezoelectric ceramic under the combined loading of a high electric field and amechanical stress. Results show that there exists a strong anisotropic effect on fracturetoughness and electric field induced fatigue crack growth in polarized PZT. Itis found that the apparent fracture toughness in the orientation parallel to thepolarization direction is much higher than that in the transverse orientation. Under apositive electric field, increasing the electric field intensity reduces the fracturetoughness in the transverse orientation but enhances that in the parallel orientation.However, the reverse is true under a negative electric field. A sphere cavity model indielectrics was employed to characterize the effect of the external applied electricfield on the evolution of cracking in an indentation. The results also show thatlow electric field intensity does not result in fatigue crack growth in PZT. For arelatively high applied electric field, the cracks initially grow quickly and then arearrested. This result is very significant for the long-term durability of PZT actuators.

Oxide film growth on Fe(111) and scanning tunneling microscopy induced high electric field stress in Fe 2O 3/Fe(111)

Oxidation of Fe(111) at 300 and 500 K was studied using Auger electron spectroscopy, low energy electron diffraction and scanning tunneling microscopy (STM) under UHV conditions. Oxidation of the Fe(111) surface at oxygen partial pressures of 1–5×10 −7 Torr resulted in the formation of Fe 2O 3 and Fe 3O 4 at 300 K. At 500 K, however, the predominant oxide phase was Fe 3O 4. STM images showed that the Fe(111) surface was uniformly covered with 5–15 nm wide oxide islands at room temperature oxidation, while oxidation at 500 K resulted in the formation of very large oxide islands (100–300 nm in width) interspersed with patches of uncovered substrate. High electric field stressing studies were carried out via STM under UHV conditions by increasing the bias voltage between the sample and the STM tip under constant current mode on iron oxide formed at both temperatures. Dielectric breakdown of the iron oxide formed at 300 K was induced after applying a high electric field. A critical bias voltage of 3.8±0.5 V was required to induce breakdown of iron oxide formed at 300 K at varying field strengths. No reproducible result was obtained from the high field stress studies of the iron oxide formed at 500 K.

Comparison between post-irradiation annealing and post-high electric field stress annealing of n-channel power VDMOSFETs

The behavior of the defects created in the gate oxide and at the Si/SiO 2 interface of n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) by irradiation and positive high electric field stress have been investigated. Interface traps exhibit the same behavior after both types of stress, while there are significant differences in post-stress responses of the charge trapped in the oxide, consisting of fixed and switching component.

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements

High field electrical stress effects on the mid-gap interface trap density ( D it0) and geometric mean capture cross sections ( σ 0) in n-MOSFETs have been studied using the pulsed interface probing method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross section values caused by the Fowler–Nordheim (F–N) electrical stress. The decrease of mid-gap trap cross sections following the F–N tunneling injection is found. Our works also provide further insight into the influence of electrical stress on mid-gap interface trap generation in n-MOSFETs without the assumption of the constant capture cross section value during F–N stresses.

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.

Highly accelerated lifetesting of base-metal-electrode ceramic chip capacitors

The ever-growing price of precious metals has promoted the widespread use of nickel and copper in the internal electrodes and end terminations of multilayer ceramic capacitors (MLCCs). While these base metal electrode (BME) capacitors are less expensive than capacitors made with palladium and silver/palladium, their unique production process produces an identifiable wear-out mechanism. Highly accelerated lifetesting is used to evaluate the reliability of BME MLCCs within reasonable timeframes by using high electric field stress and high temperature. The results of this testing are fit to a well known reliability model and then the model is used to predict device reliability under maximum rated conditions for these capacitors. Median life, t 50, is found to be in excess of 1000 years at maximum rated conditions.

Local electrical characteristics of ultra-thin SiO2 films formed on Si([formula omitted]) surfaces

We have investigated the dielectric degradation of 0.6-nm-thick silicon oxide films formed on Si(001) substrates by measuring local current–voltage (I–V) characteristics, using current sensing atomic force microscopy (AFM). It is found that the step edges are more conductive than the terraces on the oxide surface. In the local I–V characteristics, the mechanism of carrier transportation changes from electron direct tunneling to electron Fowler–Nordheim tunneling at a sample voltage of −4.2 V. This result suggests that the 0.6-nm-thick oxide film explicitly has the same band structure in the conduction band as that of bulk SiO2. Furthermore, experimental results reveal that neutral traps contributing to electron tunneling and positive charges are created in the oxide film under a high electric field stress given by a Pt-coated AFM cantilever. It is considered that the region where only the neutral trap exists corresponds to metastable states of leakage current path. On the other hand, the region where both the neutral and positive traps are present contains stable leakage sites.

Charge centers induced in thermal SiO2 films by high electric field stress at 80 K

Charge centers induced in wet and dry SiO2 films by high electric field stress [Fowler–Nordheim (FN) stress] at 80 K were characterized. The gate current of wet oxides was found to increase steeply during the FN-stress application at 80 K. In contrast, the gate current of dry oxides increased little. The thermally stimulated current of the oxides stressed by a high electric field and that of oxides irradiated with vacuum-ultraviolet light were measured. The measurements revealed one negative charge center (tr-1) and three positive charge centers (tr-2–tr-4) in the temperature range of 80–350 K. Their activation energies were estimated to be 0.26 eV (tr-1), 0.50 eV (tr-2), 0.60 eV (tr-3), and 0.86 eV (tr-4). The wet oxides were found to have a higher density of charge centers than the dry oxides. In particular, positive charge center tr-3 was characteristic of the wet oxides. The steep increase in the gate current of the wet oxides during the application of FN stress is attributed to tr-3. This center appears to be related to H+.