High-efficiency Inverse class-F Research Articles

A High-Efficiency Inverse Class-F GaN MMIC Power Amplifier With Compact Output Matching Network

This brief presents a high-efficiency inverse Class-F (Class-F-1) monolithic microwave integrated circuit (MMIC) power amplifier (PA) fabricated with 0.25-lm GaN-on-Si technology. The design is based on a compact output matching network (COMN), which consists of a harmonic control circuit (HCC), an L-section matching circuit and a bias line. In order to reduce the circuit area that make it suitable for monolithic integration, the HCC uses only three transmission lines to achieve the second and third harmonic control. In addition, the conventional quarter-wave bias line is replaced with a shorter, proper one. The proposed COMN simplifies the matching network while realizing Class-F-1 operation, which improves efficiency, output power and reduce chip size. The maximum power added efficiency of 64.5% is achieved at 3.0 GHz, with an output power of 38.4 dBm and a power gain of 10.3 dB.

An Analytic Design Approach to Inverse Class-F RF Power Amplifiers

The design of high efficiency inverse class-F (class-F-1) radio frequency (RF) power amplifiers includes extensive measurements to characterize the RF power device by means of the empirical load-pull test setup. This paper presents an alternative characterization approach based on evaluating the load impedances analytically at the desired harmonic frequencies for a high electron mobility transistor (HEMT) in terms of the internal and package elements of the active device. It additionally provides a method for extracting the parasitic elements of the power device as well as determining the optimum load-line resistance using the transistor manufacturer’s large signal model. A new topology for the output matching circuit is also proposed with its synthetic procedure to present the appropriate harmonic load impedances. To verify this methodology, a 900 MHz inverse class-F power amplifier circuit was designed and its performance was tested with the aid of the Keysight ADS software. The simulation results showed an output power of 38 dBm, a power gain of about 13 dB, DC-to-RF efficiency greater than 87%, and an acceptable level of linearity for both GSM and CDMA modulated signals.

High-Efficiency Low Voltage Inverse Class-F Power Amplifier Design Based on Harmonic Control Network Analysis

A high-efficiency inverse Class-F (Class-F−1) power amplifier (PA) with a low voltage pHEMT is presented in this paper. The design process is based on a novel harmonic control network (HCN), consisting of a bias circuit (BC) and a low pass filter (LPF). The goal is reducing the impact of fundamental frequency reflection on DC supply, elimination of harmonics, improvement of power added efficiency (PAE), shaping the voltage and current waveforms along with enhancing the performance of the PA. The simulation is performed based on the harmonic balance analysis in order of 9. The implemented Class-F−1 PA is simulated and measured at 2.4 GHz. The maximum measured PAE of 76% and the drain efficiency of 82% are achieved, with a low drain voltage of 3 V and 11.2 dB gain under a 16 dBm input power. The proposed PA is fabricated and measurement results validated the simulations.

A High-Efficiency Inverse Class-F Microwave Rectifier for Wireless Power Transmission

A high-efficiency inverse class-F microwave rectifier for wireless power transmission is described in this letter. The proposed inverse class-F harmonic termination network is realized by connecting a $\lambda /12$ open-ended transmission line in parallel with the diode cathode, and a $\lambda /8$ short-ended transmission line in series with the diode anode. This structure yields a compact layout, and measurement results have demonstrated a peak conversion efficiency of 80.4% for an input power of 13 dBm at 2.35 GHz, and an efficiency larger than 60% within the bandwidth 2.25–3 GHz and for a wide range of output loads.

Simplified First-Pass Design of High-Efficiency Class-F−1 Power Amplifiers Based on Second-Harmonic Minima

This paper investigates the source and implication of efficiency minima that is typically observed during the second-harmonic load–pull of transistor amplifiers. The study starts with the theoretical derivation of time-domain voltage and current waveforms as a function of conduction angle ( $\alpha$ ) at the second-harmonic efficiency minima, where the output power and drain efficiency (DE) are at minimum. Thereafter, this paper unfolds a systematic re-engineering approach that is developed to recover the performance degradation and to exploit the region of efficiency minima in favor of design and implementation of high-efficiency inverse class-F power amplifiers (PAs). Interestingly, the inferences drawn from the in-depth analysis are shown to provide a simplified first-pass design approach that guarantees inverse class-F PA operation without an a priori knowledge of device parasitic elements. Theoretical postulations and simulation results are experimentally validated using an on-wafer active harmonic load–pull and a prototype design using 1.95-mm NXP gallium nitride die at a frequency of 2.6 GHz. The designed PA delivers an output power of 40 dBm with DE of 76% and gain of 12 dB at 3-dB gain compression. The measurement results confirm the theoretical framework reported in this paper.

Envelope Tracking Line-up Design Considerations with High Efficiency Linearizable Inverse Class-F Driver Amplifier

In this paper, co mprehensive design considerations for mult i-stage envelope tracking power amp lifier line-up design with a 10W GaN HEMT switch mode driver amp lifierwas presented to realized optimu m overall power added efficiency.Crest factor reduction algorith m and non-linear switch mode driver design for efficiency and linearization were studied. Also, a high efficiency inverse class-F amplifier was imp lemented with efficiency as 44.8% for LTE 20M Hz signaland characterized to provethe concept of applying linearizable inverse class-F amp lifierenvelope tracking driver purpose.

High-efficiency inverse class-F power amplifier using 3/4 spiral symmetric defected ground structure

In this article, the development of a high-efficiency power amplifier (PA) with the inverse class-F configuration and a novel 3/4 spiral defected ground structure (DGS) is presented. The proposed DGS structure has improved rejection characteristic and its resonance frequencies are more convenient to adjust than conventional symmetric and asymmetric spiral structure. The electromagnetic-simulated result shows that the proposed circuit has improved harmonic control performance with simplified structure and less return loss than the conventional microstrip harmonic control circuit. The 3/4 spiral harmonics control circuit (HCC) can be modeled by three parallel RLC resonators. Using the proposed structure a high-performance harmonic control circuit is designed for implementing an inverse class-F PA. For comparison, two inverse class-F PAs operating at 2.4 GHz have been implemented by the microstrip HCC and the proposed HCC, respectively. According to the experiment results, the size of the proposed inverse class-F PA is reduced by 20%, the power-added efficiency and the gain are increased by 4.8% and 1.5 dB, respectively.