High Drain Voltage Research Articles

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the ON-resistance (RON) is observed. At stress times at which RON almost reaches its constant level, an increase of the drain leakage in OFF state (VDS=−60V, VGS=0V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25nm gate oxide thickness, the threshold voltage of 5nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.

Anomalous drain‐induced barrier lowering effect of thin‐film transistors due to capacitive coupling voltage of light‐shield metal

The anomalous drain-induced barrier lowering (DIBL) effect of long-channel thin-film transistors (TFTs) with a light shield (LS) is investigated by two-dimensional (2D) device simulation. In long-channel TFTs with a LS, which is long enough to neglect the DIBL effect and the floating body effect, a decrease of threshold voltage (V th) was observed at high drain voltages. The V th lowering is due to the large potential of the LS induced by the high drain voltage, which lowers the height of the source potential barrier. It is found that the LS-induced DIBL effect can be larger as the length of the LS increases or the thickness of the buried oxide decreases.

OFF-state degradation and correlated gate dielectric breakdown in high voltage drain extended transistors: A review

High voltage transistors exhibit unique degradation modes that cannot always be explained based on classical degradation mechanisms. In this paper, we use the specific example of OFF-state degradation in high voltage drain extended transistors to develop a generalized degradation model that can be extended to a wide range of device geometries (DeMOS, LDMOS, CMOS) and bias conditions (OFF-state, sub-threshold, ON-state). We show that hot carriers generated from impact ionization of leakage current components are responsible for OFF-state degradation by breaking interfacial and bulk SiO bonds. The resultant degradation is shown to be universal and the kinetics of SiO bond breaking is explained based on a bond-dispersion model. The generalized “bottom-up” model also explains the correlated gate dielectric breakdown and higher Weibull slopes at OFF-state conditions which are not anticipated based on classical hot carrier models. Our approach unifies hot carrier degradation results from various laboratories across the world within a common conceptual framework.

Hot Hole-Induced Device Degradation by Drain Junction Reverse Current

We studied device degradation by hot hole under drain junction reverse voltage stress with n-type metal-oxide- semiconductor field effect transistors (N-MOSFETs). The drain current generated under high drain voltage in the off-state are the drain junction reverse current and gate-induced drain leakage (GIDL) current. Therefore, we should judge that carrier injection mechanism into the gate in the off-state is due to drain junction reverse current or due to GIDL current. For our devices, drain junction reverse current was more dominant than GIDL current under specific drain voltage, and hot holes generated in the drain junction depletion region during drain junction reverse voltage stress were injected into the gate by vertical electric field, which then leads to device degradation by trapped charges. In this paper, we studied characteristic of hole injection and device degradation by drain junction reverse current.

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.

Metal-Semiconductor Barrier Modulation for High Photoresponse in Transition Metal Dichalcogenide Field Effect Transistors

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

Optimization of Bias Schemes for Long-Term Endurable 1T-DRAM Through the Use of the Biristor Mode Operation

The long-term endurance characteristics are investigated for MOSFET-based capacitorless one-transistor DRAM (1T-DRAM) under the conventional versus biristor mode. Based on the experimental results and on a supporting simulation study, it was found that the MOSFET-based 1T-DRAM, when enabled by a biristor mode, is preferred for long-term endurance compared with MOSFET-based 1T-DRAM when operated in a conventional mode. Although a high drain voltage is required in the biristor mode for programming, improved endurance characteristics are observed. The simulation study showed that this feature is achieved by the suppression of hot-hole-induced degradation, which arises from the absence of a gate use at the dynamic cell. Thus, this letter provides a new type of device architecture as well as a novel and innovative operational method pertaining to conventional 1T-DRAM to mitigate the problem of limited endurance.

고항복전압 MHEMT 전력소자 설계

This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.

Improved Vertical Isolation for Normally-Off High Voltage GaN-HFETs on n-SiC Substrates

Argon implantation of n-type SiC substrates prior to epitaxial growth of AlGaN/GaN HFETs stacks is used to decrease the vertical leakage to the conductive substrate. Normally-off p-GaN gate transistors with AlGaN-buffer and with iron-doped GaN-buffer were analyzed. The device OFF-state drain leakage was reduced for high drain voltages and the maximum breakdown strength was increased from 520 to 880 V for iron-doped GaN-buffer devices. Static device characteristics and the dynamic ON-state resistance of devices fabricated on pre-implanted SiC substrates are not degraded. High Resolution X-ray Diffraction (HRXRD) analysis confirms in coincidence that the GaN buffer defect density is not increased. Substrate implantation is thus beneficial for low-leakage high-voltage GaN devices on n-type SiC substrates.

Enhanced Radiation Sensitivity in Short-Channel Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors

The total ionizing dose effects of partially depleted silicon-on-insulator (SOI) transistors in a 0.13 μm technology are studied by 60Co γ-ray irradiation. Radiation enhanced drain-induced barrier lowering (DIBL) under different bias conditions is related to the parasitic bipolar in the SOI transistor and oxide trapped charge in the buried oxide, and it is experimentally observed for short channel transistors. The enhanced DIBL effect manifests as the DIBL parameter increases with total dose. Body doping concentration is a key factor affecting the total ionizing dose effect of the transistor. The low body doping transistor exhibits not only significant front gate threshold voltage shift as a result of the coupling effect, but also great off-state leakage at high drain voltage due to the enhanced DIBL effect.

High-Temperature Operation of Diamond Junction Field-Effect Transistors With Lateral p-n Junctions

High-temperature performance of diamond junction field-effect transistors (JFETs) with lateral p-n junctions is demonstrated. Diamond JFETs fabricated by n-type selective growth can be operated at 723 K, and show very low leakage currents of ~ 10-13 A and high ON/OFF ratios . Specific on-resistance decreases from 52.2 mΩ·cm2 at 300 K to 1.4 mΩ·cm2 at 723 K. At high temperatures, the device shows steep subthreshold swings very close to the theoretical limit. The low leakage currents are maintained even at a high drain voltage of -100 V. These excellent properties at high temperatures and high voltage show that diamond JFETs can work in harsh environments.

A semi-analytical, two-dimensional model for AlGaN/GaN high-electron-mobility-transistor Schottky currents at high reverse voltages

A semi-analytical model is derived for the reverse Schottky gate current in AlGaN-GaN high-electron-mobility-transistors (HEMTs) in off-state at high drain voltage. At elevated drain voltages, the depletion of the two-dimensional electron gas (2-DEG) not only exists directly underneath the gate contact but also extends from the gate towards the drain. This increases the electric fields at the gate edge on the drain side, which causes an increase in the gate leakage current. In this paper, a new method is proposed to calculate the electric fields at the gate edge using conformal mapping of the charge configuration in the device. This method also allows calculation of the influence of charges trapped at the interface between the semiconductor and the passivation layer next to the gate. It is shown that direct tunneling is the dominant current mechanism at high drain voltages, such that the current becomes insensitive to temperature variation. Interface charges next to the gate exert a large influence on the high voltage leakage current. It is argued that temperature variations of the high voltage leakage current are caused by temperature dependent changes in trapped charge.

Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain

The programming characteristics of gate-all-around silicon-oxide-nitride-oxide silicon (SONOS) nonvolatile memories are presented using NiSi/poly-Si nanowires (SiNW) Schottky barrier (SB) heterojunctions. The non-uniform thermal stress distribution on SiNW channels due to joule heating affected the carrier transport behavior. Under a high drain voltage, impact ionization was found as a large lateral field enhances carrier velocity. As gate voltage (Vg) increased, the difference in the drain current within a range of various temperature conditions can be mitigated because a high gate field lowers the SB height of a NiSi source/SiNW/NiSi drain junction to ensure efficient hot-carrier generation. By applying the Fowler-Nordheim programming voltage to the SONOS nanowire memory, the SB height (Φn = 0.34 eV) could be reduced by image force; thus, hot electrons could be injected from SB source/drain electrodes into the SiN storage node. To compare both SiNW and Si nanocrystal SONOS devices, the SB SiNW SONOS device was characterized experimentally to propose a wider threshold-voltage window, exhibiting efficient programming characteristics.

Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)

The work-function variation (WFV) effects of tunneling field-effect transistors (TFETs) are discussed for the first time. According to the 3-D device simulation results, TFETs are less immune to the WFV than metal–oxide–semiconductor FETs (MOSFETs) in terms of subthreshold swing <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(S)$</tex></formula> and threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm th})$</tex></formula> . TFETs show <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\sim}{1.4}\times$</tex></formula> larger <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$V_{\rm th}$</tex></formula> standard deviation <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\sigma V_{\rm th})$</tex> </formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\sim}{4.6}\times$</tex></formula> larger <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S$</tex></formula> standard deviation <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\sigma S)$</tex></formula> than MOSFETs at high drain voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm D})$</tex></formula> . It is because TFET characteristics are mainly determined by WF values of metal grains near to the source region where band-to-band tunneling occurs.

2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design

Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance.

Investigation of tow-step electrical degradation behavior in a-InGaZnO thin-film transistors with Sm2O3 gate dielectrics

We investigate the electrical stress-induced instability in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with Sm2O3 gate dielectrics. Tow-step electrical degradation behavior in Sm2O3 a-IGZO TFT devices was found under high gate and drain voltage stress during 1000 s. A typical small positive shift followed by an unusual negative shift of threshold voltage is characterized in our TFT devices. We believe that the positive shift of the threshold voltage is due to charge trapping in the gate dielectric and/or at the channel/dielectric interfaces, while the negative shift of threshold voltage can be attributed to the generation of extra electrons from oxygen vacancies in the a-IGZO channel. We suggested that the amount of oxygen vacancies and the quality of the high-κ gate dielectric probably affect the degradation behavior of a-IGZO TFT devices.

Investigations of Hot-carrier-induced Degradation for 700 V n-LDMOS Transistor Under Different Stress Conditions

The hot-carrier reliability of a 700 V n-LDMOS transistor under different stress conditions is investigated in detail. For the high drain voltage (Vds) condition, the degradation of the saturate drain current (Idsat) is different from the on-resistance (Ron) degradation for the change of the dominated degradation mechanism. Moreover, the serious Ron degradation has identical variation tendency with substrate current (Isub) because the maximum impact ionization occurs at the surface of the drift region. However, for the high gate voltage (Vgs) condition, the most important degradation is the threshold voltage (Vth). We found that the Vth degradation has an exponential relationship with Vgs. In addition, it is also observed that the thick field oxide results in strong and rapid recovery of the Ron degradation.

Electron mobility in the linear region of an AlGaN/AlN/GaN heterostructure field-effect transistor

We simulate the current—voltage (I—V) characteristics of AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with different gate lengths using the quasi-two-dimensional (quasi-2D) model. The calculation results obtained using the modified mobility model are found to accord well with the experimental data. By analyzing the variation of the electron mobility for the two-dimensional electron gas (2DEG) with the electric field in the linear region of the AlGaN/AlN/GaN HFET I—V output characteristics, it is found that the polarization Coulomb field scattering still plays an important role in the electron mobility of AlGaN/AlN/GaN HFETs at the higher drain voltage and channel electric field. As drain voltage and channel electric field increase, the 2DEG density reduces and the polarization Coulomb field scattering increases, as a result, the 2DEG electron mobility decreases.

Electrical and Electroluminescence Characteristics of AlGaN/GaN High Electron Mobility Transistors Operated in Sustainable Breakdown Conditions

This paper reports on an extensive analysis of the electrical and optical properties of GaN-based high electron mobility transistors (HEMTs) biased in a non-destructive breakdown regime. By means of a number of measurements carried out with varying voltage and temperature conditions, we show that: (i) HEMTs can reach a sustainable breakdown condition, when they are biased in current-controlled mode, with a gate voltage smaller than the pinch-off voltage; (ii) when biased in sustainable breakdown, HEMTs can emit a weak luminescence signal, localized in proximity of the drain edge; (iii) the breakdown voltage (BDV) is strongly dependent on temperature. Through a careful investigation of the drain, source and gate current components, we demonstrate that breakdown originates from two different mechanisms, depending on the gate voltage: for gate voltages close to the pinch-off, breakdown current originates from the space charge injection of electrons from the source to the drain. On the other hand, for more negative gate voltages, breakdown current originates from the injection of electrons from the gate. Finally, the analysis of the temperature dependence of the breakdown current confirms that two different mechanisms significantly contribute to current conduction at high drain voltage levels.

“Y function” method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction

In this work, we extend the “Y function” method to the saturation regime of MOSFET operation. This allowed us for the first time to extract a low charge apparent mobility up to high drain voltage and consequently the saturation velocity without the need of source drain series resistance correction. The method has successfully been applied to silicon (Si) and germanium (Ge) bulk technologies and the nonconvergence of linear mobility and saturation velocity improvement is highlighted.