High-density Nonvolatile Memory Research Articles

Nanoelectromechanical torsion switch of low operation voltage for nonvolatile memory application

Nanoelectromechanical torsion switches are fabricated by using focused ion beam milling on silicon-on-insulator substrate. The device layer thickness of the substrate is 220 nm. A 9 μm long and 1.5 μm wide suspended silicon cantilever is mechanically connected to peripheral silicon device layer via a silicon torsion spring with the length of 2.4 μm and width of 530 nm. After hydrofluoric-acid vapor releasing, the silicon cantilever shows downward deflection. The pull-in voltage is about 5.5 V and the ratio of current measured at the ON/OFF states is over 1000. Moreover, the simulated data of pull-in voltage of torsion switch is in agreement with the experimental result, which will contribute to design of an optimal nanoelectromechanical torsion switch with a driven voltage as low as 1.2 V. According to the preliminary results, this torsion switch with low driven voltage has a great potential for high density non-volatile memory application.

Resistive Switching Multistate Nonvolatile Memory Effects in a Single Cobalt Oxide Nanowire

A multistate nonvolatile memory operated at sublithographic scale has been strongly desired since other nonvolatile memories have confronted the fundamental size limits owing to their working principles. Resistive switching (RS) in metal-oxide-metal junctions, so-called ReRAM, is promising for next generation high-density nonvolatile memory. Self-assembled oxide nanowire-based RS offers an attractive solution not only to reduce the device size beyond the limitation of current lithographic length scales but also to extract the underlying nanoscale RS mechanisms. Here we demonstrate the multistate bipolar RS of a single Co(3)O(4) nanowire (10 nm scale) with the endurance up to 10(8). In addition, we succeeded to extract a voltage-induced nanoscale RS mechanism rather than current-induced RS. These findings would open up opportunities to explore not only for the intrinsic nanoscale RS mechanisms with the ultimate size limit but also for next generation multistate three-dimensional ReRAM.

Resistance-dependent amplitude of random telegraph-signal noise in resistive switching memories

Resistive-switching memory (RRAM) is attracting a considerable interest for the development of high-density nonvolatile memories. However, several scaling and reliability issues still affect the development path of RRAM. This work addresses random telegraph-signal noise (RTN) of the RRAM current, potentially affecting the memory stability. We show a clear resistance dependence of the RTN amplitude, and we propose a physical model describing the interaction of the localized current with a fluctuating defect. By estimating the diameter of the conductive filament, the model quantitatively accounts for the observed RTN amplitude, thus allowing for an analytical prediction of state stability in RRAMs.

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy) xO y for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10 19 cm −3 doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10 11 cm −2 and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy) x O y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10 −7 A/cm 2. We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.

Si-nanoclusters embedded into epitaxial rare earth oxides: Potential candidate for nonvolatile memory applications

Using an unconventional approach, single crystalline Si-nanoclusters (Si-NCs) with uniform size and higher density were embedded into epitaxial rare earth oxide with two-dimensional spatial arrangements at a defined distance from the substrate using solid source molecular beam epitaxy (MBE) technique. The incorporated Si-NCs with average size of 5 nm and density of 2 × 10 12 cm −2 exhibit charge storage capacity with promising retention (∼10 7 s) and endurance (10 5 write/erase cycles) characteristics. The Pt/Gd 2O 3 (Si-NC)/Si (MOS) basic memory cells with embedded Si-nanoclusters display large programming window (∼1.5–2 V) and fast writing speed. With such properties demonstrated, we believe that the Si-NCs embedded in epitaxial Gd 2O 3 could be potential candidate for high density nonvolatile memory devices in the future.

High-Performance High-$k$$\hbox{Y}_{2}\hbox{O}_{3}$ SONOS-Type Flash Memory

In this paper, we propose a novel high-k Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> poly-Si-oxide-nitride-oxide-silicon (SONOS)-type flash memory. The structural and morphological features of Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> films were studied using atomic force microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy. These high-k Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> SONOS-type memories exhibited large threshold voltage shifting (memory window of 1.9-4.33 V), almost negligible read and gate disturb (threshold voltage shift of ~2-mV operation at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 3 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 4 V and ~4-mV operation at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =8 V, respectively), excellent data retention (charge loss of ~4% measured time up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s and at room temperature, expected ~22% charge loss for ten years at 125degC), and superior endurance characteristics (program/erase cycles up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) because of the higher probability for trapping charge carriers. These Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> films appear to be a very promising charge trapping layer for high-density two-bit nonvolatile flash memory applications.

Study of a Spin Torque Transfer MRAM with Perpendicular Magnetization TMR Elements as a High Density Non-volatile Memory

not Available.

NEMS switch with 30 nm-thick beam and 20 nm-thick air-gap for high density non-volatile memory applications

We developed two types of titanium nitride (TiN) based nanoelectromechanical systems (NEMS) switches with the smallest dimensions ever made by typical “top-down” complementary metal–oxide–semiconductor (CMOS) fabrication technology. NEMS cantilever switch (NCLS) and NEMS clamp switch (NCS) with 30 nm-thick TiN beam and 20 nm-thick air-gap were successfully fabricated and electrically characterized. The fabricated NCLS showed ideal on/off current characteristics with an essentially zero off current, a sub-threshold slope of less than 3 mV/decade, and an on/off current ratio over 10 5 in air ambient. Also, the NCLS exhibited an endurance of over several hundred of switching cycles under dc and ac bias conditions in air ambient. Suspended beam memory (SBM) cell array structure was suggested for high density non-volatile memory applications.

Ultramultiple-level storage in TiN∕SbTeN double-layer cell for high-density nonvolatile memory

We report a phase-change nonvolatile memory (NVM) concept based on a TiN∕SbTeN (N-doped Sb2Te3) double-layer structure, which can be used for ultramultiple-level storage (UMLS). SbTeN shows a gradual resistivity drop and good phase stability with increasing annealing temperature, a characteristic which makes it suitable for UMLS applications. We demonstrate that the number of distinguishable resistance levels can readily reach 16 and even higher. These levels in this study result from the initial threshold switching and the subsequent current-controlled crystallization induced by Joule heating. The latter allows the creation of many distinct levels, thus, enabling the low-cost ultrahigh-density NVM.

Luminescence readout of nanoparticle phase state

We report that the phase state of bistable gallium nanoparticles, controlled by optical or electron beam excitations, can be identified via measurements of their cathodoluminescent emission, thus offering an innovative conceptual basis for the development of high density nonvolatile phase-change memories. Changes of up to 20% in visible emission intensity are observed following low-fluence optical or electron beam induced phase switching in a monolayer of 60nm particles.

Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory

A memory cell consisting of a Pt/VO2/Pt switch element and a Pt/NiO/Pt memory element connected in series. By applying a voltage higher than Vth of 0.6 V, the switch element reaches the on state and the cell can be accessed. Since reset and set voltages are higher than Vth, information can be written by simply applying an appropriate voltage to a selected cell. By applying a voltage lower than Vth to the other cells, we can keep the other cells in the off state and prevent interference between the selected cell and the others.

Nucleation and growth mechanism of ferroelectric domain-wall motion

The motion of domain walls is critical to many applications involving ferroelectric materials, such as fast high-density non-volatile random access memory. In memories of this sort, storing a data bit means increasing the size of one polar region at the expense of another, and hence the movement of a domain wall separating these regions. Experimental measurements of domain growth rates in the well-established ferroelectrics PbTiO3 and BaTiO3 have been performed, but the development of new materials has been hampered by a lack of microscopic understanding of how domain walls move. Despite some success in interpreting domain-wall motion in terms of classical nucleation and growth models, these models were formulated without insight from first-principles-based calculations, and they portray a picture of a large, triangular nucleus that leads to unrealistically large depolarization and nucleation energies. Here we use atomistic molecular dynamics and coarse-grained Monte Carlo simulations to analyse these processes, and demonstrate that the prevailing models are incorrect. Our multi-scale simulations reproduce experimental domain growth rates in PbTiO3 and reveal small, square critical nuclei with a diffuse interface. A simple analytic model is also proposed, relating bulk polarization and gradient energies to wall nucleation and growth, and thus rationalizing all experimental rate measurements in PbTiO3 and BaTiO3.

Decrease in switching voltage fluctuation of Pt∕NiOx∕Pt structure by process control

Resistance change random access memory devices using NiOx films with resistance switching properties have immense potential for high-density nonvolatile memory exceeding currently used flash memory. The only critical failure of a NiOx film is to write wrong information due to large fluctuations of switching voltages during successive resistance switching operations. The authors show that failure-free NiOx film can be grown directly on Pt electrode just by process control. Intensive analyses show that the superior resistance switching behaviors of their simple Pt∕NiOx∕Pt structure may result from a very thin Ni–Pt layer self-formed at the bottom interface during deposition of NiOx.

Charge trapping characteristics of atomic-layer-deposited HfO2 films with Al2O3 as a blocking oxide for high-density non-volatile memory device applications

Charge trapping characteristics of high-relative permittivity (high-κ) HfO2 films with Al2O3 as a blocking oxide in p-Si/SiO2/HfO2/Al2O3/metal memory structures have been investigated. All high-κ films have been grown by atomic layer deposition. A transmission electron microscope image shows that the HfO2 film is polycrystalline, while the Al2O3 film is partially crystalline after a high temperature annealing treatment at 1000 °C for 10 s in N2 ambient. A well-behaved counter-clockwise capacitance–voltage hysteresis has been observed for all memory capacitors. A large memory window of ∼7.4 V and a high charge trapping density of ∼1.1 × 1013 cm−2 have been observed for high-κ HfO2 charge trapping memory capacitors. The memory window and charge trapping density can be increased with increasing thickness of the HfO2 film. The charge loss can be decreased using a thick trapping layer or thick tunnelling oxide. A high work function metal gate electrode shows low charge loss and large memory window after 10 years of retention. High-κ HfO2 memory devices with high-κ Al2O3 as a blocking oxide and a high work function metal gate can be used in future high-density non-volatile memory device applications.

Anticipating technological breakthroughs: Using bibliographic coupling to explore the nanotubes paradigm

There is general consensus that the field of nanotechnology will be very important in the future. An open question is, however, which technological approaches or paradigms will be important in the field. The paper assumes that the carbon nanotube will be a key element of an emerging technological paradigm in nanotechnology. This study employs a bibliometric method — bibliographic coupling — to identify important nanotubes-related ‘leitbilder’ — a concept meaning ‘guiding images’ that provide a basis for different professions and disciplines to work in the same direction. Until recently, bibliographic coupling has been applied rarely for purposes of research evaluation, not to mention technology foresight. Our case study seems to suggest that bibliographic coupling is particularly suitable for anticipating technological breakthroughs. Bibliographic coupling analysis of recent nanotube-related patents focused our attention to recent patents owned by Nantero Inc. Nantero’s main focus is the development of NRAM — a high-density nonvolatile random access memory. The NRAM leitbild seems to be an important emerging leitbild. It connects technical opportunities and promising applications relating to the memories in devices such as cell phones, MP3 players, digital cameras, as well as applications in networking arena.

Reproducible Resistance Switching in Ni/NiO/Ni Trilayer

AbstractThe resistance random access memory is attracting much attention as a high-density and high-speed non-volatile memory, having large resistance switching ration and good affinity with the conventional CMOS technologies. We demonstrate the resistance switching in the NiO thin film without using Pt electrode.

Introduction to the special issue on Nanoscale Ferroelectrics

As ferroelectrics-based devices are entering the realm of nanoscale dimensions, it is expected that properties of ferroelectrics will start exhibiting a pronounced size effect due to high surface-to-volume ratio, increased effect of local nonstoichiometry and interfaces, polarization fluctuations, etc. This poses serious problems to the development of nanoscale ferroelectric-based devices, such as high-density non-volatile memories, photonic and electrooptic devices, piezoelectric sensors an da ctuators, smart systems, and probe-based storage devices. Apparently, advances in understanding the nanoscale ferroelectric phenomena have not been following the progress in deposition and nanofabrication techniques at a sufficiently high pace. Research on various aspects of nanoscale ferroelectric phenomena is receiving great attention from scientific community. Hundreds of papers are published every year in different journals devoted to physics, chemistry, materials science, microelectronics, etc. In this Special Issue, to provide an overview of the current status in nanoscale ferroelectric research, the editors are bringing together review papers on subjects ranging from processing of ferroelectric nanoislands to theoretical analysis of the switching of polarization in confined geometries to realspace characterization of ferroelectric structures. Several papers in this Special Issue are devoted to fabrication of ferroelectric nanostructures using sol-gel method that allows forming isolated nanoislands where the properties of ferroelectrics can be investigated as a function of their size. Modeling of the nanostructures including domain switching and stress-mediated effects is also presented. Recent progress in an understanding of dielectric anomaly in ultrathin capacitors is discussed. Development in characterizing domain configurations in 3-D shape-constrained ferroelectrics fabricated by ion etching is also presented. The current status of Piezoresponse Force Microscopy (PFM) as a reliable tool for probing nanoscopic ferroelectric structures is overviewed in this Issue. Further insights into highorder frequency and geometry effects in PFM are presented as well.

Polymer memory device based on conjugated polymer and gold nanoparticles

Electrical bistability is demonstrated in a polymer memory device with an active layer consisting of conjugated poly(3-hexylthiophene) and gold nanoparticles capped with 1-dodecanethiol sandwiched between two metal electrodes. The device was fabricated through a simple solution processing technique and exhibited a remarkable electrical bistable behavior. Above a threshold voltage the pristine device, which was in a low conductivity state, exhibited an increase in conductivity by more than three orders of magnitude. The device could be returned to the low conductivity state by applying a voltage in the reverse direction. The electronic transition is attributed to an electric-field-induced charge transfer between the two components in the system. The conduction mechanism changed from a charge-injection-controlled current in the low conductivity state to a charge-transport-controlled current in the high conductivity state. In the high conductivity state the conduction was dominated by a field-enhanced thermal excitation of trapped charges at room temperature, while it is dominated by charge tunneling at low temperatures. The device exhibited excellent stability in both the conductivity states and could be cycled between the two states for numerous times. The device exhibits tremendous potential for its application as fast, stable, low-cost, high storage density nonvolatile electronic memory.

Science and technology of thin films and interfacial layers in ferroelectric and high-dielectric constant heterostructures and application to devices

The fabrication of the next generation of complex oxide thin film-based micro and nanoscale devices, such as, for example, low and high density nonvolatile ferroelectric random access memories (FeRAMS), high-dielectric constant (K) high-frequency devices, and the next generation of complimentary metal oxide semiconductor (CMOS) nanoscale devices based on high-K dielectrics, require understanding and control of film growth and interface processes as well as development of materials integration strategies with atomic scale control. In recent years, we developed and applied a unique combination of integrated film synthesis / in situ characterization and ex situ analytical techniques capable of providing information about thin film surface and interface processes at the atomic scale as required for the development of the devices mentioned above. These techniques are also useful for establishing composition-microstructure-property relationships critical for the integration of oxide thin films with semiconductor device platforms for the development of a whole new generation of micro and nanodevices based on film technologies beyond semiconductors and specifically silicon. Our recent work has been focused on developing diffusion barrier layers and heterostructured bottom electrodes that play a critical role in high-density FeRAM integration. We demonstrated that TiAl layers can be used as a material with a double diffusion barrier/bottom electrode functionality for integration of ferroelectric capacitors CMOS devices for fabrication of FeRAMs. We also demonstrated that control of interfaces is critical to the integration of high-K dielectric films with appropriate substrates for the fabrication of high-performance high-frequency devices, and here again a diffusion barrier such as the TiAl layer developed by our group is critical for such integration. These studies revealed that when properly oxidized, nanoscale thick amorphous Ti-Al-O layers exhibit properties that make them strong candidates for application as gate dielectric in the next generation of nanoscale CMOS devices. We discuss here results from systematic studies designed to understand film growth and interface processes and their effect on materials integrations and composition-microstructure-property relationships and oxidation processes using sputter-deposition in conjunction with complementary in situ atomic layer-resolution mass spectroscopy of recoil ion (MSRI) and surface sensitive x-ray photoelectron spectroscopy (XPS) and ex situ transmission electron microscopy and electrical characterization. The unique combination of films synthesis and in situ/ex situ analytical techniques provides a powerful platform for the fundamental and applied materials science needed for the development of the next generation of multifunctional micro and nanoscale devices. A common theme in this article is the science and technology a TiAl layer that exhibit multifunctional characteristics as diffusion barrier and bottom electrode for integration of ferroelectric and high-dielectric constant (K) thing films with appropriate platform substrates for FeRAMs and high-frequency devices, and as a promising high-K dielectric layer for the next generation of nanoscale CMOS gates, flash memories, and other micro and nanodevices that require high-K layers in the device architecture.