HfO2 Gate Dielectrics Research Articles

Modification of band alignments and optimization of electrical properties of InGaZnO MOS capacitors with high-k HfOxNy gate dielectrics

High-k HfOxNy and HfO2 have been applied to amorphous InGaZnO (a-IGZO) metal–oxide–semiconductor (MOS) capacitors as high-k gate dielectrics by using radio-frequency sputtering at room temperature. Effects of nitrogen incorporation on the optical band gap, band alignment and electrical properties of HfOxNy/IGZO/Si gate stacks have been systematically investigated by spectroscopic ellipsometry (SE), UV–vis spectroscopy, x-ray photoemission spectroscopy (XPS) and electrical measurements. Experimental results have confirmed the successful incorporation of nitrogen into HfO2 films and reduction in band gap with the incorporation of nitrogen for HfOxNy thin films. Reduction in valence band offset and increase in conduction band offset have been observed for HfOxNy/IGZO gate stack. Electrical properties measurements for a-IGZO MOS capacitors based on HfOxNy gate dielectrics have indicated that nitrogen incorporation leads to the improved interface quality, increased dielectric constant, reduced hysteresis voltage, and decreased leakage current density. Meanwhile, the leakage current mechanism under gate injection for MOS capacitors based on HfO2 and HfOxNy high-k gate dielectrics has been investigated systematically.

ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment

The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance–voltage (C–V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm−2 eV−1 and 4 × 1012 cm−2 eV−1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C–V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.

Fundamental Limits on the Subthreshold Slope in Schottky Source/Drain Black Phosphorus Field-Effect Transistors.

The effect of thickness, temperature, and source-drain bias voltage, V(DS), on the subthreshold slope, SS, and off-state properties of black phosphorus (BP) field-effect transistors is reported. Locally back-gated p-MOSFETs with thin HfO2 gate dielectrics were analyzed using exfoliated BP layers ranging in thickness from ∼4 to 14 nm. SS was found to degrade with increasing V(DS) and to a greater extent in thicker flakes. In one of the thinnest devices, SS values as low as 126 mV/decade were achieved at V(DS) = -0.1 V, and the devices displayed record performance at V(DS) = -1.0 V with SS = 161 mV/decade and on-to-off current ratio of 2.84 × 10(3) within a 1 V gate bias window. A one-dimensional transport model has been utilized to extract the band gap, interface state density, and the work function of the metal contacts. The model shows that SS degradation in BP MOSFETs occurs due to the ambipolar turn on of the carriers injected at the drain before the onset of purely thermionic-limited transport at the source. The model is further utilized to provide design guidelines for achieving ideal SS and meet off-state leakage targets, and it is found that band edge work functions and thin flakes are required for ideal operation at high V(DS). This work represents a comprehensive analysis of the fundamental performance limitations of Schottky-contacted BP MOSFETs under realistic operating conditions.

TCAD performance analysis of high-K dielectrics for gate all around InAs nanowire transistor considering scaling of gate dielectric thickness

Gate dielectric thickness is an important parameter in designing nanowire FETs. In this letter, the performance potential of SiO2, ZrO2, HfO2 and La2O3 gate dielectrics for InAs based gate all-around nanowire transistor has been reported based on TCAD analysis. The results demonstrate that La2O3 can replace SiO2, ZrO2, HfO2 owing to its high current driving capability (44% increase), high mobility, low leakage current, high transconductance, high switching speed (~25μs), excellent charge density, better sub-threshold slope (~60mV/decade), reduced DIBL (~10.4%) and also the effective oxide thickness of La2O3 is found to be 0.13nm.

Impact Of Oxygen Diffusion On The Performance Of HfO2/GaAs Metal-oxide-semiconductor Field-effect-transistors

In the current work, electrical performance of n-channel GaAs MOSFETs with HfO2 gate dielectrics has been investigated by considering the impact of oxygen diffusion from gate dielectric layer. Initially, the HfO2/GaAs MOS capacitors are fabricated and its relevant process recipe has been simulated. The key parameters are extracted from both the experimental and simulated results to calibrate the simulator. The extracted parameters are subsequently fed into the simulator to investigate electrical performance of n-channel GaAs MOSFETs with varying gate lengths. The elemental diffusion of oxygen at HfO2/GaAs interface has also been incorporated since oxygen naturally diffuses into the GaAs layer during deposition and annealing steps and thereby alters the effective doping concentration in the channel. The diffused oxygen has been observed to improve electrical performance parameters such as transconductance and threshold voltage, however, degrades DIBL of the HfO2/GaAs MOSFET devices. Copyright © 2016 VBRI Press.

On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film

Internet-of-Things (IoT) technologies require a new energy-efficient transistor which operates at ultralow voltage and ultralow power for sensor node devices employing energy-harvesting techniques as power supply. In this paper, a practical device design guideline for low voltage operation of steep-slope negative-capacitance field-effect-transistors (NCFETs) operating at sub-0.2V supply voltage is investigated regarding operation speed, material requirement and energy efficiency in the case of ferroelectric HfO2 gate insulator, which is the material fully compatible to Complementary Metal-Oxide-Semiconductor (CMOS) process technologies. A physics-based numerical simulator was built to design NCFETs with the use of experimental HfO2 material parameters by modeling the ferroelectric gate insulator and FET channel simultaneously. The simulator revealed that NCFETs with ferroelectric HfO2 gate insulator enable hysteresis-free operation by setting appropriate operation point with a few nm thick gate insulator. It also revealed that, if the finite response time of spontaneous polarization of the ferroelectric gate insulator is 10-100psec, 1-10MHz operation speed can be achieved with negligible hysteresis. Finally, by optimizing material parameters and tuning negative capacitance, 2.5 times higher energy efficiency can be achieved by NCFET than by conventional MOSFETs. Thus, NCFET is expected to be a new CMOS technology platform for ultralow power IoT.

Microstructure, optical, electrical properties, and leakage current transport mechanism of sol–gel-processed high-k HfO2 gate dielectrics

Deposition of high-k HfO2 gate dielectric films on n-type Si and quartz substrates by sol–gel spin-on coating technique has been performed and the structural, optical and electrical characteristics as a function of annealing temperature have been investigated. The structural and optical properties of HfO2 thin films related to annealing temperature are investigated by X-ray diffraction (XRD), ultraviolet–visible spectroscopy (UV–vis), and spectroscopic ellipsometry (SE). Results indicate that the monoclinic form of HfO2 appears when temperature rises through and above 500°C. The reduction in band gap is observed with the increase of annealing temperature. Moreover, the increase of refractive index (n) and density and the decrease of the extinction coefficient with the increase of annealing temperature are obtained by SE measurements. Additionally, the electrical properties based on Al/Si/HfO2/Al capacitor are analyzed by means of the high frequency capacitance–voltage (C–V) and the leakage current density–voltage (J–V) characteristics. And the leakage current conduction mechanisms as functions of annealing temperatures are also discussed.

Editors' Choice Communication—A (001) β-Ga2O3 MOSFET with +2.9 V Threshold Voltage and HfO2 Gate Dielectric

An MOS transistor fabricated on (001) β-Ga2O3 exfoliated from a commercial (−201) β-Ga2O3 substrate is reported. A maximum drain current of 11.1 mA/mm was measured, and a non-destructive breakdown was reached around 80 V in the off state. Threshold voltage of +2.9 V was extracted at 0.1 V drain bias, and peak transconductance of 0.18 mS/mm was measured at VDS = 1 V, corresponding to a field effect mobility of 0.17 cm2/Vs. Hall effect and electron spin resonance data suggested that electron conductivity was due primarily to O vacancy donors (VO+) with an estimated density of 2.3 × 1017 (±50%) cm−3.

Microstructure, wettability, optical and electrical properties of HfO2 thin films: Effect of oxygen partial pressure

The effect of oxygen partial pressure on the microstructure, wettability, optical and electrical properties of sputtering-derived HfO2 thin films has been systematically investigated by using x-ray diffraction (XRD), fourier transform infrared spectroscopy (FTIR), scanning electron microscope (SEM), atomic force microscope (AFM), UV–visible spectroscopy (UV–Vis), spectroscopy ellipsometry (SE), and electrical measurements. XRD results have shown that the HfO2 thin films are all polycrystalline with monoclinic phase. Based on analysis from FTIR, a strong absorption peak centered at 1105 cm−1 has been detected, indicating the formation of the interfacial layer. Reduction in particle size and decrease in root mean square (RMS) roughness of the HfO2 thin films have been detected by SEM and AFM measurements with the increase in oxygen partial pressure. Meanwhile, the contact angle decreases and the wettability increases with increasing the oxygen partial pressure. Combined with UV–vis and SE, the optical function of HfO2 thin films as functions of oxygen partial pressure has been determined. By means of electrical measurements, evolution of electrical performance of MOS capacitor based on HfO2 gate dielectrics related with oxygen partial pressure has been investigated systematically.

High-mobility BaSnO3 thin-film transistor with HfO2 gate insulator

Thin-film transistors have been fabricated using La-doped BaSnO3 as n-type channels and (In,Sn)2O3 as source, drain, and gate electrodes. HfO2 was grown as gate insulators by atomic layer deposition. The field-effect mobility, Ion/Ioff ratio, and subthreshold swing of the device are 24.9 cm2 V−1 s−1, 6.0 × 106, and 0.42 V dec−1, respectively. The interface trap density, evaluated to be higher than 1013 cm−2 eV−1, was found to be slightly lower than that of the thin-film transistor with an Al2O3 gate insulator. We attribute the much smaller subthreshold swing values to the higher dielectric constant of HfO2.

Detailed analysis of oxide related charges and metal-oxide barriers in terrace etched Al2O3 and HfO2 on AlGaN/GaN heterostructure capacitors

In this work, we present the terrace etching technique to obtain excessive thickness series of atomic layer deposition (ALD) grown Al2O3 and HfO2 on GaN-cap/AlGaN/GaN heterostructures allowing for the detailed study of oxide charge distribution and its impact of the metal-insulator-semiconductor high electron mobility transistor (MISHEMT) threshold voltage. By modeling the experimental plot of threshold voltage versus oxide thickness on the basis of experimentally determined two-dimensional electron gas charge density in AlGaN/GaN MISHEMTs, we separated the interface and bulk charge components and determined the oxide-metal barrier height for the investigated gate dielectrics. In both Al2O3 and HfO2 gate dielectrics, the oxide charges are mainly located at the oxide/GaN interface. Determining the interface trap charges from comparison of the pulsed capacitance-voltage (CV) technique with very fast voltage sweep to the modulation type CV method with slow DC voltage ramp, we extracted positive fixed charges of NOx=2.7×1012 cm−2 for Al2O3 and NOx=7.8×1012 cm−2 for HfO2. We found a strong Vth shift of opposite direction for both high-k materials, corresponding to negatively charged up trap states at the HfO2/GaN interface and positively charged up trap states at the Al2O3/GaN interface. The evaluation of the metal-oxide barrier height in dependence of the metal work function followed the trend of the Schottky model, whereas HfO2 showed less Fermi level pinning compared to Al2O3 indicating the presence of an increased number of interface states in Al2O3 on GaN.

Modulation of charge trapping and current-conduction mechanism of TiO2-doped HfO2 gate dielectrics based MOS capacitors by annealing temperature

Current conduction mechanisms of Hf1−xTixO2-gated metal–oxide–semiconductor (MOS) capacitors depending on various post-annealing temperature (PDA) have been investigated. The sample subjected to 400 °C annealing exhibits superior performance with negligible hysteresis memory window shift (ΔVfb = 0.005 V) and lowest gate leakage current density (5.4 × 10−5 A/cm−2 at Vg = 2 V). In addition, evolution of density of interface traps (Dit), border charger density (Not) and oxide charge density (Qox) as a function of annealing temperature were investigated in details. Detailed electrical measurements reveal that the dominant current conduction behaviors are Poole–Frankel (P–F) emission in the region of low electric fields and Schottky Emission (SE) in the region of high electric fields for gate injection. For substrate injection, however, is mainly via Ohm's conduction, Schottky emission (SE) conduction mechanism serves in low applied field in the samples, respectively.

Deposition temperature dependent optical and electrical properties of ALD HfO2 gate dielectrics pretreated with tetrakisethylmethylamino hafnium

The effect of deposition temperature on the growth rate, band gap energy and electrical properties of HfO2 thin film deposited by atomic layer deposition (ALD) has been investigated. By means of characterization of spectroscopy ellipsometry and ultraviolet–visible spectroscopy, the growth rate and optical constant of ALD-derived HfO2 gate dielectrics are determined precisely. The deposition temperature dependent electrical properties of HfO2 films were determined by capacitance–voltage (C–V) and leakage current density–voltage (J–V) measurements. The leakage current mechanism for different deposition temperature has been discussed systematically. As a result, the optimized deposition temperature has been obtained to achieve HfO2 thin film with high quality.

Low-Voltage a-InGaZnO Thin-Film Transistors With Anodized Thin HfO<sub>2</sub> Gate Dielectric

Low-voltage amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with thin HfO2 gate dielectric grown by anodic oxidation (anodization) method are investigated. The morphological and electrical properties of the anodized thin HfO2 film are studied. It is shown that the as-grown HfO2 film with an equivalent oxide thickness of 3.8 nm has a low leakage current density of $3.6 \times 10^{-8}$ A/cm $^{2}$ at 1 MV/cm and high dielectric constant of $\sim 21.$ The room-temperature fabricated a-IGZO TFTs with the anodized HfO2 gate dielectrics exhibit a low threshold voltage of −0.15 ± 0.08 V, small subthreshold swing value of 109 ± 4 mV/decade, reasonable saturation mobility of 8.1 ± 0.2 cm $^{2}$ /Vs, and an ON/OFF current ratio exceeding $1 \times 10^{7}$ .

Structural and electrical properties of Nb/NbNx gates on HfO2 gate dielectrics

This study demonstrates that the nitrogen content of NbNx (0≤x≤0.45) films influences material and electrical properties of Nb/NbNx gate electrodes. With the increase in nitrogen content of NbNx films, the crystal phase changes from body-centered cubic Nb phase to cubic δ-NbN phase, accompanied by an apparent morphological change. The crystallinity of NbNx films decreases and the resistivity increases as the N2 partial flow rate increases. The effective work function of Nb/NbNx gate stacks ranges from 3.83 to 4.17eV for NbNx films deposited at various N2 partial flow rates.

Electrical characteristics of ALD La2O3 capping layers using different lanthanum precursors in MOS devices with ALD HfO2, HfSiOx, and HfSiON gate dielectrics

We have investigated the electrical characteristics – flat band voltage (VFB) shift, equivalent oxide thickness (EOT) scaling and charge trapping – of atomic layer deposition (ALD) La2O3 capped high-k gate dielectrics (HfO2, HfSiOx, and HfSiON) in the metal-oxide-semiconductor (MOS) device structure, where two different lanthanum precursors – ① lanthanum formamidinate, La(fAMD)3, and ② lanthanum betadiketonate, La(thd)3, – were used for ALD capping layer. Regardless of precursors, La2O3 capping layer on the ALD high-k films leads to negative VFB shift and thinner EOT as increasing capping thickness. However, more shift and further EOT scaling are observed with La2O3 thin film using La(fAMD)3. In addition, La2O3 capping layer using La(fAMD)3 precursor shows lower interface state density (Dit) and stronger immunity against charge trapping than La2O3 capping layer with La(thd)3 precursor. Similar trends are attained with Si containing HfO2 – HfSiOx and HfSiON, but amount of VFB shift and EOT reduction is smaller than that of HfO2-based device, resulting from suppressed La-diffusion due to stronger Si–O bonds as well as nitrogen blocking in the dielectrics.

Black Phosphorus p-MOSFETs With 7-nm HfO2Gate Dielectric and Low Contact Resistance

We report record contact resistance and transconductance in locally back-gated black phosphorus p-MOSFETs with 7-nm thick HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectrics. Devices with effective gate lengths, L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , from 0.55 to 0.17 μm were characterized and shown to have contact resistance values as low as 1.14 ± 0.05 Q-mm. In addition, devices with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> = 0.17 μm displayed extrinsic transconductance exceeding 250 μS/μm and ON-state current approaching 300 μA/μm.

Self‐aligned normally‐off metal–oxide–semiconductor n++GaN/InAlN/GaN high electron mobility transistors

Self‐aligned normally‐off n++GaN/InAlN/AlN/GaN MOS HEMTs with a recessed gate show scalable threshold voltage between 1.3 to 3.7 V, which increases with the gate oxide thickness. Al2O3 or HfO2 gate insulators were grown by ALD at 100 °C so that one photoresist mask could be used for the gate recessing, ALD and metal lift‐off. A low density of the barrier surface donors ∼1 × 1013 cm−2 stems from the low thermal budged during the HEMT processing and explains the threshold voltage behaviour. Maximal IDS reaches ∼0.4 A/mm despite 2‐μm gate length and 8‐μm source‐to‐gate distance invariant to the threshold voltage. It is shown that for the present device Al2O3 provides better gate insulation than HfO2, however, the latter may be more appropriate for highly scaled short gate‐length HEMTs. Schematic picture of the self‐aligned InAlN/GaN MOS HEMT.

AlGaN/GaN MOS-HEMTs-on-Si employing sputtered TaN-based electrodes and HfO2 gate insulator

We report on a low specific on-resistance (Ron,sp) of 3.58mΩ-cm2 and a high breakdown voltage of 1.4kV in a CMOS-compatible AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT). The MOS-HEMT is on a Si substrate and uses TaN electrodes and a HfO2-gate insulator. The sputtered TaN – a substitute for Au that has low resistivity, high work function, and thermal stability – was applied at room temperature to the gate, source, and drain. In order to obtain a low Ron,sp and high breakdown voltage, sputtering power and post-annealing temperature were optimized by measuring the characteristics of TaN. Using optimized conditions, a sputtering power of 50W, and an annealing temperature of 880°C, we successfully achieved a high on/off current ratio of 6×109 for the proposed AlGaN/GaN MOS-HEMT at a gate–drain distance of 10μm. These results indicate that the TaN process is a promising technique for power-switching GaN devices with CMOS compatibility.

Top-Gated Indium–Zinc–Oxide Thin-Film Transistors With In Situ Al2O3/HfO2 Gate Oxide

We report on top-gated indium-zinc-oxide (IZO) thin-film transistors (TFTs) with a 3-nm layer of aluminum between the IZO active layer and high-k HfO 2 gate insulator. A series of anneals at 300°C was used to convert the Al metal into Al 2 O 3 , resulting in high-performance top-gated TFTs. The 8-h-annealed TFT with Al layer has a threshold voltage |V T | <; 0.5 V, an ON/OFF ratio of 1 × 10 7 , a subthreshold slope (SS) of 0.14 V/decade, and a saturation mobility μs ~115 cm 2/ V · s in devices with L G = 50μm gate length. For smaller devices with L G = 5 μm, the threshold voltage and SS are similar, but the ON/OFF ratio and mobility are lower. Cross-sectional TEM images and C-V G characteristics with little hysteresis confirm that the thin Al layer, converted in situ into Al 2 O 3 , can protect the IZO channel during processing and produce a good high-k gate-stack.