Heterojunction Tunnel FET Research Articles

(Invited) Complementary III-V Heterojunction Tunnel FETs Monolithically Integrated on Silicon

Conventional scaling is hampered by the inability to further reduce operating voltages. The main reason for this is the limitation on the subthreshold swing of a MOSFET which determines the abruptness of the on-off transition. This is an inherent limitation of the MOSFET device physics and cannot be remedied by the introduction of novel materials or architectures, but remains an underlying physical limitation. A number of devices have been proposed to overcome this limitation, of those, the most promising in a CMOS setting remains the tunnel FET (TFET). Within the past decade, initial euphoria regarding TFET properties were replaced by more realistic hopes as more thorough simulations brought a deeper understanding of device limitations and opportunities. In this respect it became clear that careful device design and a stringent control of defects is required to realize the promise of TFETs experimentally. Very recently experimental tunnel FETs showing sub-thermionic swing over a significant current range were demonstrated, showing that it is possible to beat CMOS performance. However, technologically heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this talk we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development.

(Invited) Complementary III-V Heterojunction Tunnel FETs Monolithically Integrated on Silicon

The tunnel FET (TFET) is considered as one of the most promising devices for ultra-low power operation, and it is clear that heterojunction devices are required to achieve simultaneously steep slope and high on-current (Ion). However, technologically, heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this paper we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development. In particular we will focus on the role of defects on device performance.

Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression

The optimized non-uniform channel thickness design for type-II and -III GaAs1−xSbx/In1−yGayAs heterojunction tunnel FETs (TFETs) is proposed for improving on currents (Ion) and suppressing ambipolar leakage. Quantum confinement induced bandgap widening as a function of channel thickness (Tch) is considered. For non-uniform Tch TFETs, the thick source/channel junction thickness (Ts) with small bandgap maintains small tunneling barrier and high Ion, while the thin drain/channel junction thickness (Td) with large bandgap reduces the ambipolar leakage. With the same Ioff, type-II non-uniform TFET exhibits 4 times higher Ion (238 µA/µm) than the type-II uniform TFET, and type-III non-uniform TFET shows 63% improvement in Ion (538 µA/µm) compared with the type-III uniform TFET. The optimized non-uniform type-II TFET (GaAs0.4Sb0.6/In0.65Ga0.35As) is designed with Ts ≥ 9 nm and Td = 4–5 nm, and the optimized non-uniform type-III (GaAs0.1Sb0.9/InAs) TFET is designed with Ts = 8–9 nm and Td = 4–5 nm. The Ioff of non-uniform Tch TFETs can be further suppressed as Td scales down to below 3 nm. However, Ion degradation is observed for non-uniform Tch TFETs with thin Td ≤ 3 nm due to extra energy barrier. The Ioff of type-III non-uniform TFETs can be further reduced by using gate-to-drain underlap design. Compared with the conventional TFETs with uniform Tch, the non-uniform Tch TFETs exhibit significant improvement in subthreshold swing, which benefits ultra-low power applications.

Effects of annealing gas and drain doping concentration on electrical properties of Ge-source/Si-channel heterojunction tunneling FETs

Improvement in the performance of Ge-source/Si-channel heterojunction tunneling FETs (TFETs) with high on-current/off-current (Ion/Ioff) ratio and steep subthreshold swing (SS) is demonstrated. In this paper, we experimentally examine the effects of gas ambient [N2 and forming gas (4% H2/N2)] and a doping concentration in the drain regions on the electrical characteristics of Ge/Si heterojunction TFETs. The minimum SS (SSmin) of 70.9 mV/dec and the large Ion/Ioff ratio of 1.4 × 107 are realized by postmetallization annealing in forming gas. Also, the steep SSmin and averaged SS (SSavr) values of 64.2 and 78.4 mV/dec, respectively, are obtained in low drain doping concentration. This improvement is attributable to the reduction in interface state density (Dit) in the channel region and to the low leakage current in the drain region.

GaAsSb/InGaAs heterojunction tunnel field-effect transistors with a heterogeneous channel

This study presents a new structure to improve off-state current and ambipolar conduction in GaAsSb/InGaAs heterojunction tunnel field-effect transistors (HTFET). A GaAsSb/InGaAs heterogeneous channel was proposed to form p-GaAsSb/i-InGaAs junction at the source side and i-GaAsSb/n-InGaAs junction at the drain side. In the off-state bias condition, the band offsets of GaAsSb/InGaAs in the channel can prevent electrons tunneling to the drain side to reduce the leakage current and ambipolar conduction. Through simulation, heterogeneous channel HTFETs demonstrate that the off-state current can be reduced by four orders of magnitude and still demonstrate a high on-state current compared with GaAsSb/InGaAs HTFETs. As a result, the proposed heterogeneous channel HTFET exhibits suppressed ambipolar conduction even when the drain doping is as high as 1 × 1019 cm−3.

2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

A continuous 2-D analytical drain current model of double-gate (DG) heterojunction tunnel field-effect transistors (HJTFETs) with a SiO2/HfO2 stacked gate-oxide structures has been presented in this paper. The surface potential model has been developed by considering the effect of accumulation/inversion charges and depletion region at source/channel and drain/channel junctions. The electric field-dependent band-to-band tunneling generation rate has been derived from the surface potential model. The tangent line approximation method has been used to calculate the drain current of DG HJTFETs. The developed model is valid for all regions (subthreshold to strong accumulation/inversion region) of operation. The model has been developed for Si/Ge hetero and Si homojunction-based tunnel field-effect transistor devices. The model is also applicable for other structures such as III–V materials-based InAs/GaSb DG HJTFET and silicon-on-insulator-based HJTFET. The analytical model results are validated by 2-D ATLAS simulation data.

Bandgap Engineering and Strain Effects of Core–Shell Tunneling Field-Effect Transistors

DC characteristics of n-type SiGe heterojunction nanowire tunneling field-effect transistors (TFETs) adopting a core–shell structure are investigated using 3-D numerical simulation. Different mole fractions between the core and the shell regions induce strain effects along the nanowire, which modulate the energy bandgap and thus the dc performance of the devices. The SiGe core–shell TFETs with greater mole fractions in the core regions increase the drive currents greatly by both Ge content and strain effects which decrease the tunneling length and increase the band-to-band (BTB) generation rate according to Kane’s nonlocal tunneling model. In addition, tensile (compressive) strains for the shell (core) regions as well as shear strains reduce the energy bandgap according to the deformation potential theory, decreasing the subthreshold swing as well as increasing the BTB generation rate. Compared to all other Si/Ge heterojunction TFETs, the proposed SiGe core–shell TFETs are superior with high drive currents and on/off-current ratios.

Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET

This paper presents the comparative study on linearity and analog/radio frequency presentation of an III–V staggered hetero-junction nanowire (NW) TFET with Si and InAs based NW TFET of same dimension. The device parameter of analog/RF performance for low power application such as transconductance (gm), output resistance (RO), intrinsic gain (gmR0), cut-off frequency (fT), maximum frequency of oscillation (fmax), gain bandwidth product (GBW), VIP2, VIP3 as well as 1-dB compression point has been explored. There is a better improvement in analog/radio frequency presentation obtained from heterojunction NW TFET over Si and InAs TFET. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, higher GBW better linearity performance as compared to Si and InAs TFET.

A U-Gate InGaAs/GaAsSb Heterojunction TFET of Tunneling Normal to the Gate With Separate Control Over ON- and OFF-State Current

A U-gate vertical tunneling field-effect transistor (TFET) of band-to-band tunneling (BTBT) normal to the gate at low operation voltages is proposed and investigated by TCAD simulation. In this structure, drive current and OFF-state leakage current can be separately controlled by the insertion of a spacer layer between the channel and drain layers. The dominant mechanisms for drive current and OFF-state leakage are BTBT and source-to-drain tunneling (SDT), respectively. A modified structure of side gates and a hetero-spacer enables high-performance InGaAs/GaAsSb heterojunction TFETs with low OFF-state leakage. Drive current as high as 520 $\mu \text{A}/\mu \text{m}$ with an $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 107 at an overdrive voltage of 0.3 V was achieved in an InGaAs/GaAsSb heterojunction TFET of a small effective bandgap (0.02 eV). Furthermore, this U-gate TFET structure is fully compatible to VLSI technology without any complicated fabrication steps.

A temperature‐dependent surface potential‐based algorithm for extraction of threshold voltage in homojunction TFETs

AbstractIn this paper, we propose an algorithm to extract threshold voltage in homojunction tunnel field effect transistors (TFETs). Single gate TFET and double gate TFET are the geometries which are considered for verification of the method. Firstly, a generalized model of surface potential based on 2D Poisson equation for homojunction TFETs is developed. Secondly, the algorithm involves a number of geometrical operations on surface potential plots, which are performed computationally. From the plots of surface potential and the geometrical constructions, a parameter, range_point, is defined through mathematical formulations. The threshold voltage is determined by subjecting the range_point to a set of constraints which are found to be same for both the devices. The validity of the algorithm is confirmed by considering different parameters like drain voltage, gate oxide thickness, and temperature for both low‐k and high‐k gate dielectric materials in TFETs. The temperature variation is validated for a heterojunction TFET too using the same generalized model of surface potential.

Effects of impurity and composition profiles on electrical characteristics of GaAsSb/InGaAs hetero-junction vertical tunnel field effect transistors

We fabricated and characterized GaAs0.51Sb0.49/In0.53Ga0.47As hetero-junction vertical tunnel field effect transistors (TFETs) on InP substrates in order to examine the effects of the structural characteristics of GaAsSb/InGaAs hetero-structures on the electrical properties of the TFETs. The operation of the fabricated GaAs0.51Sb0.49/In0.53Ga0.47As TFET was confirmed with the ION/IOFF ratio of ∼102 over VG swing of 1.25 V at 297 K. This ION/IOFF ratio was improved up to ∼104 at 20 K, thanks to the suppression of the leakage current in the source junction. The secondary ion mass spectrometry analyses for the present hetero-structures have revealed that the concentration of the p-type dopant (Be) atoms, doped in the GaAsSb source regions, decreases in the InGaAs channel regions at an inverse slope of ∼11 nm/dec. Also, the scanning transmission electron microscope-energy dispersive X-ray spectroscopy has shown that group III and V compositions change abruptly in a region within 10 nm from the interface between the Be-doped GaAsSb source and the undoped InGaAs channel. We performed the 2-dimensional device simulation based on the device structure and the experimentally obtained composition and impurity profiles, and we found that the composition profile had little effect on the S.S. values. The device simulation also revealed that both the optimization of the concentration and the profile of the p-type doping of GaAsSb, and thinning of the effective oxide thickness (EOT) of the gate stacks could effectively improve the inherent S.S. values of the present GaAs0.51Sb0.49/In0.53Ga0.47As hetero-junction vertical TFETs. When 1.0 nm EOT and NA = 1 × 1020 cm−3 are used under the present impurity abruptness, S.S. < 40 mV/dec. can be achieved for the vertical GaAsSb/InGaAs TFETs, which is promising for an ultralow power switching device.

Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing

In this letter, a novel graded-channel heterojunction tunnel field-effect transistor (GCH-TFET) is proposed and studied by simulation. The novel TFET adopts a near broken-gap heterojunction at the source/channel interface to enhance the tunnel efficiency. Besides, it employs a graded component channel which works as an electron barrier to block up the leakage current at the OFF-state and can be removed with the increased gate voltage at the ON-state for high ON/OFF-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio. Such graded channel also allows a sudden turn-on of band-to-band tunneling, resulting in a reduced sub-threshold swing (SS) compared with conventional heterojunction TFETs. The GCH-TFET demonstrates an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of more than seven decades with I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> up to 225 μA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.3 V, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> more than two decades lower than a near broken-gap heterojunction TFET and SS lower than 30 mV/decade for more than five decades, exhibiting excellent potential for ultra-low power applications.

Quantum confinement modulation on the performance of nanometer thin body GaSb/InAs tunnel field-effect transistors

In this paper, we have presented an atomistic quantum simulation study to investigate the device performances of GaSb/InAs heterojunction tunnel field-effect transistors (TFETs) with nanometer body thicknesses. It is revealed that the thin junction induced quantum confinement effect results in a heterojunction type transition from type-III to type-II as the junction thickness reduces, which can be used as an effective modulation of the TFET device performance. It is found that as the channel thickness decreases, both the ON current and OFF current of the device decrease significantly due to the quantum confinement induced effective band gap enlargement. In addition, the OFF current of the heterojunction GaSb/InAs TFET is always larger than that of the homojunction InAs TFET, which is possibly caused by the GaSb/InAs interfacial state assisted tunneling. It is also revealed that the subthreshold swing of the heterojunction TFET does not change much as the channel thickness is reduced.

A Multiscale Modeling of Triple-Heterojunction Tunneling FETs

A high performance triple-heterojunction (3HJ) design has been previously proposed for tunneling FETs (TFETs). Compared with single heterojunction (HJ) TFETs, the 3HJ TFETs have both shorter tunneling distance and two transmission resonances that significantly improve the ON-state current ($I_{\rm{ON}}$). Coherent quantum transport simulation predicts, that $I_{\rm{ON}}=460\rm{\mu A/\mu m}$ can be achieved at gate length $Lg=15\rm{nm}$, supply voltage $V_{\rm{DD}}=0.3\rm{V}$, and OFF-state current $I_{\rm{OFF}}=1\rm{nA/\mu m}$. However, strong electron-phonon and electron-electron scattering in the heavily doped leads implies, that the 3HJ devices operate far from the ideal coherent limit. In this study, such scattering effects are assessed by a newly developed multiscale transport model, which combines the ballistic non-equilibrium Green's function method for the channel and the drift-diffusion scattering method for the leads. Simulation results show that the thermalizing scattering in the leads both degrades the 3HJ TFET's subthreshold swing through scattering induced leakage and reduces the turn-on current through the access resistance. Assuming bulk scattering rates and carrier mobilities, the $I_{\rm{ON}}$ is dropped from $460\rm{\mu A/\mu m}$ down to $254\rm{\mu A/\mu m}$, which is still much larger than the single HJ TFET case.

GaAsSb/InGaAs tunnel field effect transistor with a pocket layer

This work proposes a new GaAs0.51Sb0.49/In0.53Ga0.47As heterojunction tunnel field effect transistor (HTFET) with a 6-nm In0.7Ga0.3As layer (pocket) between the source and channel. Compared with InGaAs homojunction TFETs, the proposed HTFET has a steeper subthreshold swing at a higher drain current, owing to its lower source-to-channel tunnel barrier height. It has a maximum on-state current of 11.98μA/μm at room temperature, which is more than ten times the on-state current obtained from an InGaAs homojunction TFET.

Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure

A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson’s equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

Investigation of GaAsBi/GaAsN Type-II Staggered Heterojunction TFETs with the Analytical Model

We investigate GaAs 1-x Bi x /GaAs 1-y N y type-II staggered heterojunction tunneling field-effect transistors (TFETs) with the analytical model. GaAs 1-x Bi x /GaAs 1-y N y exhibits a remarkable type-II band lineup and the effective bandgap ${E} _{{{G,{\mathrm{ eff}}}}}$ at interface is significantly reduced with the increasing of bismuth (Bi) and nitrogen (N) compositions. Theoretical characterization shows that the band-to-band tunneling probability and current of TFETs are boosted with the decreasing of ${E} _{{{G,\text {eff}}}}$ at the GaAs 1-x Bi x /GaAs 1-y N y staggered tunnel-ing junction by increasing Bi and N compositions. It is demonstrated by the analytical calculation that GaAs 1-x Bi x /GaAs 1-y N y heterostructure is a potential candidate for high-performance TFET.

TFET‐based well capacity adjustment in active pixel sensor for enhanced high dynamic range

A tunnel field-effect transistor (TFET)-based pixel circuit for well capacity adjustment that does not require subthreshold operation on the part of the reset transistor is presented. In CMOS, this subthreshold operation leads to temporal noise, distortion and fixed pattern noise, becoming a primary limiting performance factor. In the proposed circuit, the asymmetric conduction associated with TFETs is exploited. This property, arising from the inherent physical structure of the device, provides the selective well adjustments during photo-integration which are demanded for achieving high dynamic range. A GaN-based heterojunction TFET has been designed according to the specific requirements for this application.

Scalable GaSb/InAs Tunnel FETs With Nonuniform Body Thickness

GaSb/InAs heterojunction tunnel field-effect transistors are strong candidates in building future low-power integrated circuits, as they could provide both steep subthreshold swing and large ON-state current ($I_{\rm{ON}}$). However, at short channel lengths they suffer from large tunneling leakage originating from the small band gap and small effective masses of the InAs channel. As proposed in this article, this problem can be significantly mitigated by reducing the channel thickness meanwhile retaining a thick source-channel tunnel junction, thus forming a design with a non-uniform body thickness. Because of the quantum confinement, the thin InAs channel offers a large band gap and large effective masses, reducing the ambipolar and source-to-drain tunneling leakage at OFF state. The thick GaSb/InAs tunnel junction, instead, offers a low tunnel barrier and small effective masses, allowing a large tunnel probability at ON state. In addition, the confinement induced band discontinuity enhances the tunnel electric field and creates a resonant state, further improving $I_{\rm{ON}}$. Atomistic quantum transport simulations show that ballistic $I_{\rm{ON}}=284$A/m is obtained at 15nm channel length, $I_{\rm{OFF}}=1\times10^{-3}$A/m, and $V_{\rm{DD}}=0.3$V. While with uniform body thickness, the largest achievable $I_{\rm{ON}}$ is only 25A/m. Simulations also indicate that this design is scalable to sub-10nm channel length.

Analysis of Ge-Si Heterojunction Nanowire Tunnel FET: Impact of Tunneling Window of Band-to-Band Tunneling Model

Tunnel FET (TFET) has potential applications in the next generation ultra-low power transistor to substitute the conventional FETs. It can offer very steep inverse subthreshold swing slope to maintain a low leakage current, thus it can be very essential for limiting power consumption in MOSFETs. The carriers in TFET transport from source to channel by the band-to-band tunneling (BTBT) mechanisms. To realize high saturation currents of TFET, it critically depends on the transmission probability, TWKB. In indirect semiconductor, such as Si and Ge, the BTBT model is very crucial for designing and predicting the device performance. In this paper, we employed the nonlocal BTBT model applied to three-dimensional Ge-Si heterojunction TFET with gate length 10 nm compare with Si TFET by including quantum effects simulation. The results show that the Ge-Si TFET outperforms Si TFET because of the lower bandgap and larger tunneling windows. BTBT generation rates of Ge-Si TFET are higher than Si TFET in the on-state condition. The highest BTBT generation rates are located in the source and channel junction and its peaks close to the gate dielectric.