Heterojunction Field Effect Transistors Research Articles

Theoretical investigation of high-voltage superjunction GaN-based vertical hetero-junction field effect transistor with ununiformly doped buffer to suppress charge imbalance effect

A superjunction GaN-based vertical heterojunction field effect transistor with ununiformly doped buffer (UDSJ-VHFET) is proposed in this paper. In contrast to the conventional superjunction vertical heterojunction field effect transistor (SJ-VHFET), the doping density of n-pillar increases linearly from top to bottom, while the p-pillar is split into three regions: linearly doped top region, uniformly doped middle region and linearly doped bottom region. The ununiform doping profile suppresses the increase of electric field peak due to the imbalanced charge and smooths the electric field distribution, thus leads to an increase of the breakdown voltage (Vbr) under charge imbalance condition. Simulation results show that with the doping dose of p-pillar 40% lower (higher) than that of the n-pillar, the Vbr and on-state resistance (Ron) of the proposed device are 6863 V and 4.25 mΩ cm2 (5751 V and 4.32 mΩ cm2), comparing with 3205 V and 4.03 mΩ cm2 (2175 V and 4.10 mΩ cm2) for the conventional SJ-VHFET. Additionally, the proposed device shows a Vbr of 12280 V and Ron of 4.29 mΩ cm2 under charge balance condition, comparing with 12874 V and 4.07 mΩ cm2 for the conventional SJ-VHFET.

Al0.75Ga0.25N/Al0.6Ga0.4N heterojunction field effect transistor with fT of 40 GHz

An Al0.75Ga0.25N/Al0.6Ga0.4N heterostructure field effect transistor with graded MBE-regrown contacts is designed, grown, and fabricated on AlN/sapphire substrate. Maximum drain current density (ID,max) of 460 mA mm−1 was obtained on transistors with gate length of 130 nm. The small signal measurement shows current/power gain cutoff frequency (fT/fmax) of 40 GHz/58 GHz, respectively. Parasitic resistance is found to be a significant factor limiting the frequency performance of the devices. The high frequency performance of devices with high Al concentration AlGaN channel demonstrate potential for high power and high frequency applications.

Mobility enhancement in recessed-gate AlGaN/GaN MOS-HFETs using an AlON gate insulator

We demonstrated the advantage of aluminum oxynitride (AlON) gate insulator in enhancing the performance of recessed-gate AlGaN/GaN-based metal–oxide–semiconductor heterojunction field-effect transistors (MOS-HFETs) fabricated with reactive ion etching. The AlON deposition on the recessed-gate structures was found to mitigate the damage of recess etching on the GaN and AlGaN surfaces, enabling a simple gate recess process in the device fabrication. Consequently, a high field-effect mobility of 259 cm2 V−1 s−1, together with normally off operation, was achieved for the recessed-gate AlGaN/GaN MOS-HFETs with the AlON gate insulator. Temperature dependence of the transconductance of the fabricated devices revealed that carrier transport in the channel was mostly dominated by phonon scattering, indicating excellent interface quality between the AlON insulator and the recess-etched AlGaN surfaces.

Realization of high-power dimmable GaN-based LEDs by hybrid integration with AlGaN/GaN HFETs

We successfully demonstrated high-power dimmable GaN-based vertical injection LEDs (VI-LEDs) by integration with AlGaN/GaN-based heterojunction field-effect transistors (HFETs) using a flip-chip bonding technique. The high-power dimmable GaN-based VI-LEDs on AlGaN/GaN HFETs emitted no light in the off-state of the HFETs and operated normally in the on-state of the HFETs. Furthermore, the light-output power (LOP), forward current, and maximum electroluminescence (EL) intensity were efficiently modulated with the gate-to-source voltage (VGS) of the HFETs. The temperature rose by less than 20 °C when the devices were operated with a VGS of −3 V and supply voltage (VDD) of 10 V. These results suggest that the high-power dimmable GaN-based VI-LEDs can be fabricated through hybrid integration with AlGaN/GaN HFETs, and the devices could be applied to novel applications such as visible light communication (VLC) and adaptive headlights for vehicles.

Theoretical Investigation of High-Voltage Self-Charge-Balanced Superjunction AlGaN/GaN Heterojunction Field Effect Transistors with Nanoscale Polarization-Doped AlGaN Layer

Theoretical Investigation of High-Voltage Self-Charge-Balanced Superjunction AlGaN/GaN Heterojunction Field Effect Transistors with Nanoscale Polarization-Doped AlGaN Layer

Investigation of post-annealing effects for normally-off GaN metal-oxide semiconductor heterojunction field-effect transistors with thin AlN barrier layer

The effects of post-annealing processes for normally-off GaN metal-oxide semiconductor heterojunction field-effect transistors (MOS-HFETs) with a thin AlN barrier layer are investigated. These annealing processes are post-deposition annealing (PDA) after oxide deposition, post-metallization annealing (PMA) after gate metallization, and positive-bias annealing (PBA) after wafer processes. PMA and PBA are effective in enhancing the drain current density and threshold voltage shift. The most effective method is PBA and the obtained threshold voltage and drain current density are +3.0 V and 0.7 A mm−1, respectively. This is attributed to improvements in interfacial trap states which is confirmed by an investigation of the frequency dependence of capacitance–voltage characteristics.

AlGaN polarization-doped field effect transistor with compositionally graded channel from Al0.6Ga0.4N to AlN

Polarization-doped field effect transistors (PolFETs) were realized with an unintentionally doped AlxGa1-xN channel layer graded over Al compositions 0.60 ≤ x ≤ 1.0 with a maximum current density of 188 mA/mm (+10 V gate-to-source bias) and an on-resistance of 85 mΩ mm. The average mobility in the PolFET channel was estimated to be 320 cm2/V s, which exceeds that of previous AlGaN metal-semiconductor field effect transistors (MESFETs) and heterojunction field effect transistors (HFETs) of similar Al composition. The breakdown voltage was greater than 620 V, indicating an average critical electric field of >210 V/μm, which is substantially better than ∼100 V/μm that is typically achieved in GaN HFETs. These findings demonstrate that Al-rich PolFETs are attractive alternatives to MESFETs and HFETs for achieving simultaneously high channel electron density and mobility in high voltage switches.

Effects of post-deposition annealing in O2 on threshold voltage of Al2O3/AlGaN/GaN MOS heterojunction field-effect transistors

In this paper, we investigated the effects of the post-deposition annealing (PDA) on the threshold voltage (Vth) of AlGaN/GaN MOS heterojunction field-effect transistors with atomic-layer-deposited Al2O3 using H2O vapor or oxygen plasma as the oxidant. By PDA, the Vth shifts positively with the Vth variations depending on the oxidants. The capacitance–voltage measurements reveal that the Vth variation is attributed to the differences in the initial fixed charge density in the Al2O3 or/and the Al2O3/AlGaN for both oxidants.

Physics-Based 2-D Analytical Model for Field-Plate Engineering of AlGaN/GaN Power HFET

A physics-based 2-D analytical model is developed for AlGaN/GaN heterojunction field-effect transistor (HFET) to optimize the field-plate (FP) design for electric-field (E-field) engineering. The model reveals the impact of critical device parameters such as FP length, passivation dielectric, and dielectric thickness on the electric potential and E-field distribution in AlGaN/GaN HFET. With this model, a minimum FP length as well as the optimal dielectric thickness for different passivation dielectrics can be obtained to achieve a uniform E-field distribution and simultaneously at the minimized cost of parasitic capacitance. By taking the edge effect of both the gate and FP into account, the calculated results exhibit good agreement with numerical simulation. The developed model is of the great potential of high-voltage AlGaN/GaN HFET design for power switching applications.

Electrical Stability and Flicker Noise of Thin-Film Heterojunction FETs on Poly-Si Substrates

Electrical stability and flicker (1/f) noise of thin-film heterojunction field-effect transistors (HJFETs) comprised of hydrogenated amorphous Si (a-Si:H) gate and hydrogenated crystalline Si (c-Si:H) source and drain regions on small-grain poly-Si substrates are investigated and benchmarked against conventional thin-film transistors (TFTs). Despite the low growth temperature of a-Si:H and c-Si:H (~200°C), HJFETs are found to have higher stability and lower flicker noise than conventional TFTs. These results may be attributed partly to the device structure and partly to the high-quality gate heterojunction of the HJFETs.

A Low-Power Thin-Film Si Heterojunction FET Noise Amplifier for Generation of True Random Numbers

A low-power noise amplifier is implemented with thin-film Si heterojunction field-effect transistors (HJFETs) and its suitability for generation of true random numbers is investigated. The HJFETs are operated at near subthreshold to obtain a large output resistance and therefore a high intrinsic gain at a low operation power. It is found that the noise output of a proof-of-concept 4-stage amplifier with a voltage gain of ~5000, bandwidth of ~1 KHz, power consumption of ~100 nW, and a dc-blocking output capacitance of 250 pF is suitable for generation of statistically true random numbers at a rate of 100 bit/s without requiring post-processing. The described technique may find application in emerging technologies, such as large-area, flexible, and/or wearable devices that benefit from enhanced security and low-power computing.

Asymmetric gated Ge-Si<SUB align="right">0.7Ge<SUB align="right">0.3 nHTFET and pHTFET for steep subthreshold characteristics

The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si0.7Ge0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si0.7Ge0.3 HTFET has steep subthreshold characteristic, low DIBL with high ION/IOFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The ION/IOFF current ratio greater than 108 is achieved for gate length of 15 nm in nHTFET having Pt/HfO2 as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.

Asymmetric Gated Ge-Si0.7Ge0.3 nHTFET and pHTFET for Steep Subthreshold Characteristics

The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si0.7Ge0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si0.7Ge0.3 HTFET has steep subthreshold characteristic, low DIBL with high ION/IOFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The ION/IOFF current ratio greater than 108 is achieved for gate length of 15 nm in nHTFET having Pt/HfO2 as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.

Reliability studies on biaxially tensile strained-Si channel p-MOSFETs

An integrated technology computer aided simulation framework is used for the first time to predict the reliability (degradation) of substrate-induced strained-Si channel heterojunction field effect transistors on relaxed Silicon-Germanium buffer layer with ultra-thin SiO2 and high-k gate stacks. State-of-the-art four-state nonradiative multiphonon model is used for the degradation studies. Single defects and trap studies have been taken up on devices subjected to negative voltage stressing at an elevated temperature. Threshold voltage shift (due to charge capture and emission processes) in virtually fabricated devices has been studied in detail. For the first time, non radiative multiphonon model is used to explain the degradation mechanisms (oxide defects dominating the partial recovery of threshold voltage after stressing) in strained-Si channel heterojunction field effect transistors. It is shown that degradation in strained-Si channel device on relaxed-SiGe buffer is more compared to its Si-channel counterpart.

Efficient Atomistic Simulation of Heterostructure Field-Effect Transistors

In this paper, atomistic-level quantum mechanical simulations are performed for nanoscale field-effect transistors (FETs) with lateral or vertical heterojunction, within the non-equilibrium Green’s function formalism. For efficient simulation of such heterostructure FETs, a novel approach is developed where the Green’s functions are calculated by complementarily using the two algorithms of the recursive Green’s function and the $R$ -matrix. The $R$ -matrix algorithm is extended to seamlessly combine the two methods on the open system and an algorithm for the electron correlation function based on the extended $R$ -matrix algorithm is also developed. The proposed method significantly reduces simulation time, making rigorous atomistic simulations of heterojunction FETs possible. As an application, device simulations are performed for the germanane/InSe vertical tunneling FET (VTFET) modeled through the first-principles density functional theory. Our simulation results reveal that the germanane/InSe VTFET is a promising candidate for future low power applications.

Evaluation of Pulsed I–V Analysis as Validation Tool of Nonlinear RF Models of GaN-Based HFETs

This paper evaluates the applicability of pulsed I – V measurements as a tool for accurately extracting nonlinear gallium nitride (GaN)-based heterojunction field-effect transistor (HFET) models. Two wafers with the identical layer structure but different growth conditions have been investigated. A series of I – V measurements was performed under dc and pulsed conditions demonstrating a dramatic difference in the kink effect and current collapse (knee walkout) suggesting different trapping behaviors. However, when radio frequency (RF) I – V waveform measurements, utilizing active harmonic load–pull, were used to study the impact of these traps on the RF performance, both wafers gave good overall RF performance with no significant difference observed. This absence of correlation between pulsed I – V measurement results and RF performance raises a question about the applicability of pulsed I – V measurements alone as a tool for extracting nonlinear device models in the case of GaN HFETs.

Why and How New Japan Radio Has Continued GaAs RFIC Manufacturing in Japan; Introduction of Unique Proven Technology Based on Hetero-Junction FET Process

We describe the history of New Japan Radio Co. Ltd., (NJR) and our continuing presence in the business of manufacturing gallium arsenide radio frequency (GaAs RF) front-end devices. We also explain how our company survived and prospered despite the changing markets. We compare NJR strategies with those of competing RF integrated circuit (RFIC) manufacturers in Japan and briefly describe the hetero-junction field-effect transistor technology, which plays a key role in the success of NJR's RFIC business. We present some of the manufacturing and performance data to show how we improved the wafer process. These unique underlying technologies have enabled the implementation of unique circuit types, which are rarely seen in conventional GaAs ICs.

Operation Mechanism of a MoS₂/BP Heterojunction FET.

The electrical characteristics and operation mechanism of a molybdenum disulfide/black phosphorus (MoS2/BP) heterojunction device are investigated herein. Even though this device showed a high on-off ratio of over 1 × 107, with a lower subthreshold swing of ~54 mV/dec and a 1fA level off current, its operating mechanism is closer to a junction field-effect transistor (FET) than a tunneling FET. The off-current of this device is governed by the depletion region in the BP layer, and the band-to-band tunneling current does not contribute to the rapid turn-on and extremely low off-current.

Analysis of drain current saturation behaviour in GaN polarisation super junction HFETs

The magnitude of saturation current in a power device significantly impacts its short-circuit capability. In conjunction with the unprecedented miniaturisation that gallium nitride (GaN) offers, there is a compelling rationale to examine this critical parameter in GaN transistors for thermally stable and reliable power converter applications. This study presents a comprehensive analysis of the physical behaviour that yields intrinsically low drain current saturation in GaN polarisation super junction heterojunction field-effect transistors (PSJ HFETs). The analysis in this work has been performed using electrical characterisation data of conventional and PSJ HFETs, supported by physics-based two-dimensional device simulations. Insight is gained on the differing device architecture-dependent mechanisms that determine the magnitude of drain current density in both types of devices when biased in the saturation region.

Polarity Control within One Monolayer at ZnO/GaN Heterointerface: (0001) Plane Inversion Domain Boundary.

In semiconductor heterojunction, polarity critically governs the physical properties, with an impact on electronic or optoelectronic devices through the presence of pyroelectric and piezoelectric fields at the active heteropolar interface. In the present work, the abrupt O-polar ZnO/Ga-polar GaN heterointerface was successfully achieved by using high O/Zn ratio flux during the ZnO nucleation growth. Atomic-resolution high-angle annular dark-field and bright-field transmission electron microscopy observation revealed that this polarity inversion confines within one monolayer by forming the (0001) plane inversion domain boundary (IDB) at the ZnO/GaN heterointerface. Through theoretical calculation and topology analysis, the geometry of this IDB was determined to possess an octahedral Ga atomic layer in the interface, with one O/N layer symmetrically bonded at the tetrahedral site. The computed electronic structure of all considered IDBs revealed a metallic character at the heterointerface. More interestingly, the presence of two-dimensional (2D) hole gas (2DHG) or 2D electron gas (2DEG) is uncovered by investigating the chemical bonding and charge transfer at the heterointerface. This work not only clarifies the polarity control and interfacial configuration of the O-polar ZnO/Ga-polar GaN heterojunction but, more importantly, also gives insight into their further application on heterojunction field-effect transistors as well as hybrid ZnO/GaN optoelectronic devices. Moreover, such polarity control at the monolayer scale might have practical implications for heterojunction devices based on other polar semiconductors.