Heterogeneous Processor Architectures Research Articles

Real-time range gate control of a satellite laser ranging system based the on heterogeneous processor architecture.

The range gate generator (RGG) is a key device in kilohertz (kHz) satellite laser ranging systems. The RGG at Changchun station is an integrated circuit composed of discrete components. Using this RGG at high repetition rates can result in the loss of data, and the low resolution of internal time can lead to inaccurate data points. In this paper, starting from the principle of noise suppression by range gate control, we propose a method of range gate control with high repetition rates, high accuracy, and strong universality, and we implement a RGG based on the heterogeneous system architecture of a field-programmable gate array plus a digital signal processor. The average of the intervals between the internal time of the embedded RGG and the external standard time is 48.268 ns, and the accuracy of the range gate time is less than 1.5 ns. The test results indicate that the embedded RGG can satisfy the demand for centimeter-level accuracy with satellite laser ranging. Compared with the original RGG at Changchun station, the embedded RGG has significantly improved time resolution, repetition rate of laser ranging, and system upgrade and maintenance. At present, Changchun station is carrying out a short-term stability test on the embedded RGG.

A novel graph-based approach for IoT botnet detection

The Internet of things (IoT) is the extension of Internet connectivity into physical devices and everyday objects. These IoT devices can communicate with others over the Internet and fully integrate into people’s daily life. In recent years, IoT devices still suffer from basic security vulnerabilities making them vulnerable to a variety of threats and malware, especially IoT botnets. Unlike common malware on desktop personal computer and Android, heterogeneous processor architecture issue on IoT devices brings various challenges for researchers. Many studies take advantages of well-known dynamic or static analysis for detecting and classifying botnet on IoT devices. However, almost studies yet cannot address the multi-architecture issue and consume vast computing resources for analyzing. In this paper, we propose a lightweight method for detecting IoT botnet, which based on extracting high-level features from function–call graphs, called PSI-Graph, for each executable file. This feature shows the effectiveness when dealing with the multi-architecture problem while avoiding the complexity of control flow graph analysis that is used by most of the existing methods. The experimental results show that the proposed method achieves an accuracy of 98.7%, with the dataset of 11,200 ELF files consisting of 7199 IoT botnet samples and 4001 benign samples. Additionally, a comparative study with other existing methods demonstrates that our approach delivers better outcome. Lastly, we make the source code of this work available to Github.

Case of ARM emulation optimization for offloading mechanisms in Mobile Cloud Computing

The Mobile Cloud Computing (MCC) paradigm depends on efficient offloading of computation from the resource constrained mobile device to the resource rich cloud server. The computational offloading is assisted by system virtualization, application virtualization, and process state migration. However, system and application virtualization techniques force unnecessary overhead on applications that require offloading to the cloud and applications that do not. Moreover, smartphones and cloud data centers are based on heterogeneous processor architectures, such as, ARM and x86. As a result, process migrated from a smartphone needs translation or emulation on the cloud server. Therefore, instruction emulation is a necessary criterion for a comprehensive MCC framework. In this paper, we evaluate the overhead of the system and application virtualization techniques and emulation frameworks that enable MCC offloading mechanisms. We find that the overhead of system and application virtualization can be as high as 4.51% and 55.18% respectively for the SciMark benchmark. Moreover, ARM to Intel device emulation overhead can be as high as 55.53%. We provide a proof of concept of emulation speedup by utilizing efficient Single Instruction, Multiple Data (SIMD) translations. We conclude that the overhead of virtualization and emulation techniques need to be reduced for efficient MCC offloading frameworks.

AUTOMATED NETWORK PROTOCOL EVALUATION – THE POTSDAM WIRELESS TESTBED

The Potsdam Wireless Testbed supports validation and evaluation of Wi-Fi radio stacks and wireless applications in environments with heterogeneous hardware. In contrast to simulators, wireless testbeds support the network stack validation with specific radio chipsets and radio signal propagations. Furthermore, wireless testbeds unburden programmers from manually updating software on nodes. Scheduled test-runs are executed automatically for a defined duration including compilation and deployment of the protocols and measurement scripts as well as collection of measurement results and log files. The testbed supports heterogeneous processor architectures and radio chipsets via internal cross compilation. The developer can overview the visualized results of its validation and therefore can focus on the code and the results. Next to the support of several device and processor architectures, the Potsdam Wireless Testbed is intended to support additional radio frequency ranges as well as mobile device.

On implementing motion-based Region of Interest detection on multi-core CELL

Region of Interest (ROI) detection is a well-studied problem in computer vision for applications such as video surveillance and vision-based robotics. ROI detection may be done using background subtraction schemes with change detection and background estimation. When the camera is not static, these schemes will be ineffective and hence there is a need for global motion estimation (GME) to compensate the camera motion. Robust GME algorithms often require high computation power, rendering them unsuitable for real-time, embedded vision applications. In this article, we use a multi-core processor platform – CELL, to meet the computational requirements of the ROI detection system and to explore the feasibility of potential usage of such heterogeneous processor architecture for vision applications. In particular, we analyze the algorithmic components of a typical GME-based ROI detection system and show how to make efficient use of the parallel and vector computation capabilities in the CELL cores for maximizing the gain on speed performance. We have also ported our system on a Sony PS3 system and promising results have been achieved. Based on the study, various design aspects and implementation challenges are discussed which are believed to be useful for future work in porting vision algorithms on multi-core architectures for real-time embedded applications.

ERI sorting for emerging processor architectures

Electron Repulsion Integrals (ERIs) are a common bottleneck in ab initio computational chemistry. It is known that sorted/reordered execution of ERIs results in efficient SIMD/vector processing. This paper shows that reconfigurable computing and heterogeneous processor architectures can also benefit from a deliberate ordering of ERI tasks. However, realizing these benefits as net speedup requires a very rapid sorting mechanism. This paper presents two such mechanisms. Included in this study are analytical, simulation-based, and experimental benchmarking approaches to consider five use cases for ERI sorting, i.e. SIMD processing, reconfigurable computing, limited address spaces, instruction cache exploitation, and data cache exploitation. Specific consideration is given to existing cache-based processors, FPGAs, and the Cell Broadband Engine processor. It is proposed that the analyses conducted in this work should be built upon to aid the development of software autotuners which will produce efficient ab initio computational chemistry codes for a variety of computer architectures.

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors

Clustering L0 buffers is effective for energy reduction in the instruction memory hierarchy of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. Especially in heterogeneous or data clustered VLIW processors, determining energy efficient scheduling is more constraining. This article proposes a realistic technique supported by a tool flow to explore operation shuffling for improving generation of L0 clusters. The tool flow explores assignment of operations for each cycle and generates various schedules. This approach makes it possible to reduce energy consumption for various processor architectures. However, the computational complexity is large because of the huge exploration space. Therefore, some heuristics are also developed, which reduce the size of the exploration space while the solution quality remains reasonable. Furthermore, we also propose a technique to support VLIW processors with multiple data clusters, which is essential to apply the methodology to real world processors. The experimental results indicate potential gains of up to 27.6% in energy in L0 buffers, through operation shuffling for heterogeneous processor architectures as well as a homogeneous architecture. Furthermore, the proposed heuristics drastically reduce the exploration search space by about 90%, while the results are comparable to full search, with average differences of less than 1%. The experimental results indicate that energy efficiency can be improved in most of the media benchmarks by the proposed methodology, where the average gain is around 10% in comparison with generating clusters without operation shuffling.

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

In this contribution the concept of functional- level power analysis (FLPA) for power estimation of programmable processors is extended in order to model embedded as well as heterogeneous processor architectures featuring different embedded processor cores. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like, e.g. processing unit, clock network, internal memory, etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional-level and instruction-level (FLPA/ILPA) model in order to achieve a good modeling accuracy. In order to show the applicability of this approach even a heterogeneous processor architecture (OMAP5912) featuring an ARM926EJ-S core and a C55x DSP core has been modeled using the hybrid FLPA/ILPA technique described before. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders or classical benchmark suits. Estimated power figures for the inspected tasks are compared to physically measured values for both inspected processor architectures. A resulting maximum estimation error of 9% for the ARM940T and less than 4% for the OMAP5912 is achieved.

A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>