Heterogeneous Multiprocessor Research Articles

Assigning real-time tasks on heterogeneous multiprocessors with two unrelated types of processors

Consider the problem of partitioned scheduling of an implicit-deadline sporadic task set on heterogeneous multiprocessors to meet all deadlines. Each processor is either of type-1 or type-2. We present a new algorithm, FF-3C, for this problem. FF-3C offers low time-complexity and provably good performance. Specifically, FF-3C offers (i) a time-complexity of O(n⋅max(m,logn)+m⋅logm), where n is the number of tasks and m is the number of processors and (ii) the guarantee that if a task set can be scheduled by an optimal partitioned-scheduling algorithm to meet all deadlines then FF-3C meets all deadlines as well if given processors at most \(\frac{1}{1-\alpha}\) times as fast (referred to as speed competitive ratio) and tasks are scheduled using EDF; where α is a property of the task set. The parameter α is in the range (0,0.5] and for each task, it holds that its utilization is no greater than α or greater than 1−α on each processor type. Thus, the speed competitive ratio of FF-3C can never exceed 2.We also present several extensions to FF-3C; these offer the same performance guarantee and time-complexity but with improved average-case performance. Via simulations, we compare the performance of our new algorithms and two state-of-the-art algorithms (and variations of the latter). We evaluate algorithms based on (i) running time and (ii) the necessary multiplication factor, i.e., the amount of extra speed of processors that the algorithm needs, for a given task set, so as to succeed, compared to an optimal task assignment algorithm. Overall, we observed that our new algorithms perform significantly better than the state-of-the-art. We also observed that our algorithms perform much better in practice, i.e., the necessary multiplication factor of the algorithms is much smaller than their speed competitive ratio. Finally, we also present a clustered version of the new algorithm.

Communication-aware Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems

Real-time streaming signal processing systems typically desire high throughput and low latency. Many such systems can be modeled as synchronous data flow graphs. In this paper, we address the problem of multi-objective mapping of SDF graphs onto heterogeneous multiprocessor platforms, where we account for the overhead of bus-based inter-processor communication. The primary contributions include (1) an integer linear programming (ILP) model that globally optimizes throughput, latency and cost; (2) low-complexity two-stage heuristics based on a combination of an evolutionary algorithm with an ILP to generate either a single sub-optimal mapping solution or a Pareto front for design space optimization. In our simulations, the proposed heuristic shows up to 12x run-time efficiency compared to the global ILP while maintaining a 10???6 optimality gap in throughput.

Performance evaluation of inter-processor communication for an embedded heterogeneous multi-core processor

Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP. This paper uses comprehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC performance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we improve the IPC performance of a voice over IP (VoIP) phone. Experimental results demonstrate that the GPP workload decreases significantly by 35% without sacrificing the functionalities and voice quality of the VoIP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.

Research on the Embedded Heterogeneous Multi-core Design Method for 100GbE Network Processor

We proposed a design method of heterogeneous multi-core processor on chip. In our design flow, we structured a computing model mapped onto the processor's micro architecture, and structured a work-load model mapped onto the system architecture. The design method of heterogeneous multi-core processor means that the core types, core numbers, and core interconnections varied along with the various applications. In other words, the multi-core architecture is application-specific. At last, a design of an embedded heterogeneous multi-core 100GbE network processor is used as an application example.

Platform and Mapping Methodology for Heterogeneous Multicore Processors

Heterogeneous multi-core processors are attracted by various type of applications from low-power media applications to high-performance computing due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks between different cores becomes a serious problem. This paper presents two key methodologies to solve the data transfer bottoleneck: memory allocation considering a addressing function constraint and task allocation based on algorithm transformation. Moreover, in order to help to explore accelerator architecture suitable for applications, this paper presents a platform based on FPGAs where circuity is reconfigured by users after fabrication.

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

Efficient and scalable scheduling for performance heterogeneous multicore systems

Performance heterogeneous multicore processors (HMP for brevity) consisting of multiple cores with the same instruction set but different performance characteristics (e.g., clock speed, issue width), are of great concern since they are able to deliver higher performance per watt and area for programs with diverse architectural requirements than comparable homogeneous ones. However, such power and area efficiencies of performance heterogeneous multicore systems can only be achieved when workloads are matched with cores according to both the properties of the workload and the features of the cores.Several heterogeneity-aware schedulers were proposed in the previous work. In terms of whether properties of workloads are obtained online or not, those scheduling algorithms can be categorized into two classes: online monitoring and offline profiling. The previous online monitoring approaches had to trace threads’ execution on all core types, which is impractical as the number of core types grows. Besides, to trace all core types threads have to be migrated among cores, which may cause load imbalance and degrade the performance. The existing offline profiling approaches profile programs with a given input set before really executing them and thus remove the overhead associated with the number of core types. However, offline profiling approaches do not account for phase changes of threads. Moreover, since the properties they have collected are based on the given input set, those offline profiling approaches are hard to adapt to various input sets and therefore will drastically affect the program performance.To address the above problems in the existing approaches, we propose a new technique, ASTPI (Average Stall Time Per Instruction), to measure the efficiencies of threads in using fast cores. We design, implement and evaluate a new online monitoring approach called ESHMP, which is based on the metric. Our evaluation in the Linux 2.6.21 operating system shows that ESHMP delivers scalability while adapting to a wide variety of applications. Also, our experiment results show that among HMP systems in which heterogeneity-aware schedulers are adopted and there are more than one LLC (Last Level Cache), the architecture where heterogeneous cores share LLCs gain better performance than the ones where homogeneous cores share LLCs.

Thread scheduling for heterogeneous multicore processors using phase identification

Heterogeneous multicore processors (HMPs) offer promise for significant efficiency improvement. Power-effcient cores can be paired with higher performance cores in an HMP to achieve a beneficial design in terms of both power and performance. However, such processors produce challenges in the effective mapping of threads to cores. An application could have very different behavior and performance when executing on cores of different types. The behavior of typical applications also vary with their phases of execution. Thus, the type of core providing the best performance for an application may depend on the current phase. In this work, we highlight the correlation between execution phases of an application and the performance of those phases on particular core types. We propose mechanisms that identify program phases, exploit the performance behavior of these phases to make effective scheduling decisions, and reuse the result of these scheduling decisions on future occurrences of the same program phases.

Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures

Scheduling periodic tasks onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an Integer Linear Programming (ILP) based framework that maps a given task set onto an Heterogeneous Multiprocessor System-on-Chip (HMPSoC) architecture. Our framework can be used with several objective functions; minimizing energy consumption, minimizing cost (i.e., the number of heterogeneous processors), and maximizing reliability of the system under performance constraints. We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to maximize reliability. We illustrate the effectiveness of our approach through several experiments, each with a different number of tasks to be scheduled. We also propose two heuristics based on Earliest Deadline First (EDF) algorithm for minimizing energy under performance and cost constraints. Our experiments on generated task sets show that ILP-based method reduces the energy consumption up to 62% percent against a method that does not apply DVS. Heuristic methods obtain promising results when compared to optimal results generated by our ILP-based method.

Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors

High performance and low-power very large-scale integrations are required to implement complex media processing applications on mobile devices. Heterogeneous multicore processors are a promising way to achieve this objective. They contain multiple accelerator cores and CPU cores to increase the processing speed. Since media processing applications access a huge amount of data, fast address generation is very important. To increase the address generation speed, accelerator cores contain address generation units (AGUs). To reduce the power consumption, the AGUs have limited hardware resources such as adders and counters. Therefore, the AGUs generate simple addressing patterns where the address increases linearly in each clock cycle. Media processing applications frequently encounter addressing patterns where the same data are accessed in different time slots. To implement such addressing patterns, the same data have to be allocated into multiple memory addresses in such a way that those addresses can be generated by the AGUs. Allocation of the same data in multiple addresses is called the “data-duplication.” The data-duplication increases the data-transfer time and also the total processing time significantly. To remove such data-transfer bottlenecks, this paper proposes a memory allocation method that exploits the temporal and spatial locality of the memory access in media processing applications. We evaluate the proposed method using media processing applications to validate its effectiveness. According to the results, the proposed method reduces the total processing time by 14% to more than 85% compared to previous works.

Study on Explicit Memory Management for CBEA Green Computing Architecture

Heterogeneous multi-core processors are attractive for power efficient green computing because of their ability to meet varied resource requirements. The multi-level memory hierarchy of Cell Broadband Engine Architecture (CBEA) which requires explicit management by software poses significant challenges to performance increasing and programming. In this paper, with analysis of characteristic of the architecture, we implemented four access methods and a corresponding access library with a uniform memory access interface. Besides getting performance boosts beyond current level technology, the memory access library with uniform access interface could collect profile information of memory management for further performance optimization. Experimental results show the performance of proposed method is better than related works and profile information provided by the method is helpful for programmer to optimize application performance.

Network Coding on Heterogeneous Multi-Core Processors for Wireless Sensor Networks

While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used as processing nodes of the wireless sensor networks in the near future. To this end, this paper introduces an efficient network coding algorithm developed for the heterogenous multi-core processors. The proposed idea is fully tested on one of the currently available heterogeneous multi-core processors referred to as the Cell Broadband Engine.

Automatic analysis of DMA races using model checking and k-induction

Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratch-pad” memories. The price for increased performance is higher programming complexity – the programmer must manually orchestrate data movement using direct memory access (DMA) operations. Programming using asynchronous DMA operations is error-prone, and DMA races can lead to nondeterministic bugs which are hard to reproduce and fix. We present a method for DMA race analysis in C programs. Our method works by automatically instrumenting a program with assertions modeling the semantics of a memory flow controller. The instrumented program can then be analyzed using state-of-the-art software model checkers. We show that bounded model checking is effective for detecting DMA races in buggy programs. To enable automatic verification of the correctness of instrumented programs, we present a new formulation of k-induction geared towards software, as a proof rule operating on loops. Our techniques are implemented as a tool, Scratch, which we apply to a large set of programs supplied with the IBM Cell SDK, in which we discover a previously unknown bug. Our experimental results indicate that our k-induction method performs extremely well on this problem class. To our knowledge, this marks both the first application of k-induction to software verification, and the first example of software model checking in the context of heterogeneous multicore processors.

Workload Mode Identification for Chip Heterogeneous Multiprocessors

With the potential for tens to hundreds of processing elements on future single chip multicore designs also comes the potential to execute a wider variety of input streams, or workloads. At the same time, the trend is for single users to utilize an entire single chip multicore computer. A central challenge for these computers is how to model and identify persistent changes in the input stream, or workload modes. Computer architects often model single program phases as Markov chains. We define workload modes and analyze and evaluate two modeling techniques, a Workload Classification Model (WCM) and a Hidden Markov Model (HMM). We include experimentation on a cell phone example, illustrating how WCM is, on average, 34 times more time efficient and 83% more space efficient than HMM, while improving overall performance by an average of 191% and being, on average, 56% more energy efficient. We found that even sub-optimal use of WCM can outperform HMM, further supporting the need for design time workload models. Our main contribution is to show how the design of single user multicore architecture to models of workloads that arise from single user usage patterns will be necessary as the complexity of applications and architectures grows. Thus, we advocate Workload Specific Processors as a new means of orienting single-user chip heterogeneous multiprocessors.

Accelerating network applications by distributed interfaces on heterogeneous multiprocessor architectures

Hosts with several, possibly heterogeneous and/or multicore, processors provide new challenges and opportunities to accelerate applications with high communications bandwidth requirements. Many opportunities to scale these network applications with the increase in the link bandwidths are related to the exploitation of the available parallelism provided by the presence of several processing cores in the servers, not only for computing the workload of the user application but also for decreasing the overhead associated to the network interface and the system software. This paper analyses some alternatives to distribute the network interface among the different cores available in the host. These alternatives include the use of heterogeneous multicore processors, such as network processors, and the exploitation of the affinity between the network interface and the location (proximity to the memories where the different data structures are stored) and characteristics of the processing architecture. The proposed distributed network interfaces provide improvements in throughput and latency that have been experimentally evaluated by using an intrusion prevention system, which constitutes a useful network function.

Programming Techniques for the Cell Processor

Abstract Cell Broadband Engine is a heterogeneous multicore processor designed mainly for applications in scientific computing, graphics, and gaming with high performance requirements. We give an overview of its architecture, review some selected development tools and programming frameworks, and describe techniques for writing efficient programs for Cell.

An Operating System Architecture Design for Heterogeneous Multi-Core Processor Based on Multi-Master Model

The traditional distributed operating system (OS) and homogeneous multiprocessors OS are not suitable for heterogeneous multi-core processor (HMP) in real-time and efficiency performance. After researching the structure and the development trend of the HMP, this paper presents a multi-master model real-time operating system architecture for HMP, which is designed with symmetric structure and functional modularization, and every kernel can manage resources, tasks and other shared devices as a master to improve the real-time and efficiency performance, to solve the bottle-neck problem that the single master can not satisfy the requirement of performance with increasing of the slave number. This architecture can adapt to different structure processor core with configurable function module. On the other hand, it can also reduce the development difficulty of the heterogeneous multi-core processor OS.

Lattice gauge theory on a multi-core processor, Cell/B.E

Abstract We report our implementation experience of a lattice gauge theory code on the Cell Broadband Engine, which is a new heterogeneous multi-core processor. As a typical operation, we take a SU(3) matrix multiplication which is one of the most important parts of lattice gauge theories. Employing full advantage of the Cell/B.E. including SIMD operations and many registers, which enable the full use of the arithmetic units through the loop-unrolling, we obtain about 200 GFLOPS with 16 SPE, which corresponds around 80% of the theoretical peak. To our knowledge, this is the fastest value of this operation obtained on the Cell/B.E. so far. However, when we measure the whole time including the data supply, the speed drops down to about 13 GFLOPS.We found that the bandwidth of the data transfer between the main memory and EIB, 25 GB/s, is a bottleneck. In other words, it is possible to run the arithmetic units on the Cell/B.E. with 200 GFLOPS speed, but the current socket structure of Cell/B.E. prevents it. We discuss several techniques to improve the problem partially by reducing the transferred data.

Fast computation for electromagnetic scattering problems using a heterogeneous multi-core processor

Potential of hardware acceleration of the method of moments using a heterogeneous multi-core processor. The parallel efficiency is almost 100% and the computational time is about 100 times faster than that using a conventional CPU.

History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors

The authors introduce a history-aware, resource-based dynamic (or simply HARD) scheduler for heterogeneous chip multi-processors (CMPs). HARD relies on recording application resource utilisation and throughput to adaptively change cores for applications during runtime. The authors show that HARD can be configured to achieve both performance and power improvements and compare HARD to an alternative dynamic scheduler and a static scheduler to provide better understanding.