Heterogeneous Multiprocessing Research Articles

Design and Implementation of a Criticality- and Heterogeneity-Aware Runtime System for Task-Parallel Applications

Heterogeneous multiprocessing (HMP) is an emerging technology for high-performance and energy-efficient computing. While task parallelism is widely used in various computing domains, such as embedded, big-data, and machine-learning computing domains, it still remains unexplored to investigate the efficient runtime support that effectively utilizes the criticality of the tasks of the target application and the heterogeneity of the underlying HMP system with full resource management. To bridge this gap, we propose CHRT, a criticality- and heterogeneity-aware runtime system for task-parallel applications. CHRT dynamically estimates the performance and power consumption of the target task-parallel application and robustly manages the full HMP system resources (i.e., core types, counts, and voltage/frequency levels) to maximize the overall efficiency. Our quantitative evaluation based on widely-used task parallel benchmarks and two full HMP systems (i.e., the XU3 and HiKey970 HMP systems) demonstrates the effectiveness of CHRT in that CHRT achieves significantly higher energy (e.g., 60.4 and 57.2 percent on average on the XU3 system) and energy-delay product (e.g., 52.2 and 44.0 percent on average on the HiKey970 system) efficiency than the baseline runtime system that employs the breadth-first scheduler and the state-of-the-art criticality-aware runtime system and incurs low performance overheads.

The large-scale parallelization of the Boids model on the K computer and the heterogeneous multi-processing unit

While attempting the parallelization of multiagent systems, a load imbalance often slows down the calculation. Hirokawa et al. presented a multilevel hierarchy of parallelism to mitigate the load-imbalance problem of the Boids model using a pseudo-quadruple arithmetic technique. In this paper, we modify the hierarchies of parallelization for both the K computer and a heterogeneous multiprocessing (HMP) unit, and evaluate the performance of the proposed solutions on these systems. We observed that the parallelization can decrease the negative effects of a load imbalance. Furthermore, we discovered that the power consumption can be effectively controlled by calculating the load and that the simultaneous use of both high-performance cores and low-energy cores slows down the calculations on the HMP unit. Parallelization has been reported to have the potential for enabling the completion of simulations in real time and to have the ability to evaluate up to 3000 billion agents using the K computer.

Hardware-software collaboration for dark silicon heterogeneous many-core systems

In dark silicon many-core systems, system-level techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the allowable power budget and eliminate thermal hotspot. However, this will unexpectedly increase communication overhead due to the longer average distance between active cores in a typical mesh-based Network-on-Chip (NoC), and in turn reduce application performance. Inspired by ARM’s big.LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) which enables energy-efficient solutions, in this paper, we propose two alternative hardware–software collaborated techniques to address the temperature/communication conflict in the dark silicon era. A Folded Torus-like NoC, FoToNoC, is presented to address the Cluster-switching based heterogeneous system, and a Quad-core-group based NoC, QcNoC, is presented to address the In-kernel switcher based heterogeneous system. Matched management strategies are accordingly proposed to collaboratively solve the trade-offs on inter-core communication, application performance, chip temperature, and system energy-efficiency in different design phases and aspects. Experimental results show that, FoToNoC can improve as large as 36.85% on application performance, save up to 30.35% on system energy consumption and reduce chip peak temperature by 4.11∘C on average compared with traditional techniques. Furthermore, due to the heterogeneous core organization and the fine-grained optimization on energy-efficiency in QcNoC, averagely 18.40% reduction on system energy consumption can be achieved with an average 2.24∘C reduction on chip peak temperature compared with that in FoToNoC. We further demonstrate the practicality and the effectiveness of the proposed methods by case studies on real-world applications including the industry standard H.264 decoder and DSP-stone benchmarks.

High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors

Heterogeneous multiprocessing is the future of chip design with the potential for tens to hundreds of programmable elements on single chips within the next several years. These chips will have heterogeneous, programmable hardware elements that lead to different execution times for the same software executing on different resources as well as a mix of desktop-style and embedded-style software. They will also have a layer of programming across multiple programmable elements forming the basis of a new kind of programmable system which we refer to as a Programmable Heterogeneous Multiprocessor (PHM). Current modeling approaches use instruction set simulation for performance modeling, but this will become far too prohibitive in terms of simulation time for these larger designs. The fundamental question is what the next higher level of design will be. The high-level modeling, simulation and design required for these programmable systems poses unique challenges, representing a break from traditional hardware design. Programmable systems, including layered concurrent software executing via schedulers on concurrent hardware, are not characterizable with traditional component-based hierarchical composition approaches, including discrete event simulation. We describe the foundations of our layered approach to modeling and performance simulation of PHMs, showing an example design space of a network processor explored using our simulation approach.