Heterogeneous Multiprocessor Research Articles

Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems

With the advent of heterogeneous multiprocessor architectures, efficient scheduling for high performance has been of significant importance. However, joint considerations of reliability, temperature, and stochastic characteristics of precedence-constrained tasks for performance optimization make task scheduling particularly challenging. In this paper, we tackle this challenge by using an affinity (i.e., probability)-driven task allocation and scheduling approach that decouples schedule lengths and thermal profiles of processors. Specifically, we separately model the affinity of a task for processors with respect to schedule lengths and the affinity of a task for processors with regard to chip thermal profiles considering task reliability and stochastic characteristics of task execution time and intertask communication time. Subsequently, we combine the two types of affinities, and design a scheduling heuristic that assigns a task to the processor with the highest joint affinity. Extensive simulations based on randomly generated stochastic and real-world applications are performed to validate the effectiveness of the proposed approach. Experiment results show that the proposed scheme can reduce the system makespan by up to 30.1% without violating the temperature and reliability constraints compared to benchmarking methods.

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs

Abstract This paper presents a framework targeted to low-cost and low-power heterogeneous MultiProcessors that exploits FPGAs and multicore CPUs, with the overarching goal of providing developers with a productive programming model and runtime support to fully use all the processing resources available. FPGA productivity is achieved using a high-level programming model based on OpenCL, the standard for cross-platform parallel heterogeneous programming. In this work, we focus on the parallel_for pattern, and as part of the runtime support for this pattern, we leverage a new scheduler that strives to maximize the number of iterations per joule by dynamically and adaptively partitioning the iteration space between the multicore and the accelerator when working simultaneously. A total of 7 benchmarks are ported and optimized for a low-cost DE1 board. The results show that the heterogeneous solution can improve performance up to 2.9 × and increases energy efficiency up to 2.7 × compared to the traditional approach of keeping all the CPU cores idle while the accelerator computes the workload. Our results also demonstrate two interesting insights: first, an adaptive scheduler able to find at runtime the right chunk size for each type of application and device configuration is an essential component for these kinds of heterogeneous platforms, and second, device configurations that provide higher throughput do not always achieve better energy efficiency when only the running power (excluding the idle power component) is considered.

METHOD OF SOLVING SYSTEM OF LINEAR ALGEBRAIC EQUATIONS WITH USE OF HIGH PERFORMANCE COMPUTING ON GPU

The article discusses the use of graphics processing units for solving large system of linear algebraic equations (SLAE). A heterogeneous multiprocessor computing platform produced by the NIIVK, whose architecture allows the integration of general‑ purpose microprocessor modules with graphics processor modules was used as an equipment for solving SLAEs. The description of the SLAE solution program, developed on the basis of the CUBLAS CUDA software interface library, is given. A method is proposed for increasing the accuracy of calculations of linear systems based on the use of a modified Gauss method. It has been established that the use of the modified Gauss method practically does not increase the program operation time with a significant increase in the accuracy of calculations. It is concluded that the use of graphics processors for solving SLAEs allows processing matrices of a larger size compared to the use of general‑purpose microprocessors.

DI_GA: A Heuristic Mapping Algorithm for Heterogeneous Network-on-Chip

Heterogeneous multi-core processors have become the forefront of processor development due to their advantages in system throughput and execution efficiency, but they also bring many new challenges to system design. The mapping of heterogeneous Network-on-Chip (NoC) is challenging. To solve this problem, this paper proposes a heterogeneous multi-core processor task mapping algorithm based on an improved genetic algorithm. By constructing a good initial population method to improve the initial population quality, a dual population genetic mechanism is used in the iteration process. The algorithm can make tasks more reasonably distributed to various network nodes, and has high efficiency for optimizing network power consumption on heterogeneous multi-cores.

Heterogeneous Multiprocessor Matching Degree Scheduling Algorithm Based on OpenCL Framework

In a heterogeneous multi-core system, the merits of the task scheduling algorithm have a great impact on the efficiency of the system. This paper implements a matching degree scheduling algorithm based on heterogeneous multiprocessor. Before the actual scheduling, the static task feature value and the processor core configuration feature value are mapped into the same European space, and the “program-core-distance” matching value is calculated by using the WED. In the actual scheduling, the matching value and the size of the input byte are obtained, and the tasks are matched with the processor under the influence of the two to determine the execution order of the tasks on each processor. The scheduling method based on OpenCL framework is compared with the traditional scheduling algorithm. It shows that the scheduling scheme implemented in this paper has significantly improved efficiency when executing tasks.

A meta heuristic-based task scheduling and mapping method to optimize main design challenges of heterogeneous multiprocessor embedded systems

In this paper, we proposed a meta heuristic-based task scheduling method to optimize lifetime reliability, performance and power consumption of heterogeneous MPSoCs. Lifetime reliability is affected by several failure mechanisms with different behaviors which are mainly dependent on temperature and its variation pattern. To improve lifetime reliability of multiprocessor systems, it is required to consider the effect of all potential failures and their distinct impact during the optimization process. Moreover, improving power consumption and execution time makes the optimization process more complicated due to the existing trade offs among these parameters. Our proposed task scheduling method optimizes lifetime reliability by considering the effect of all failure mechanisms, power consumption and execution time of heterogeneous MPSoCs. It employs a design space exploration engine based on the Non-dominated Sorting Genetic Algorithm (NSGA-II) to make the exploration process more efficient. To demonstrate the effectiveness of our proposed task scheduling and mapping method and compare it to the related studies, several experiments are performed. Moreover, the importance of thermal cycling (TC), as an emerging thermal concern in computing the lifetime reliability of MPSoCs, and also the capability of our proposed method in controlling it are studied and compared to related research. Experimental results show that employing our proposed scheduling method improves performance, lifetime reliability and power consumption about 24%, 30% and 3.6% respectively on average compared to two selected related studies. Furthermore, our proposed approach decreases the occurrence rate of all failure mechanisms compared to related studies and outperforms them in term of the thermal cycling rate about 48% on average.

Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore

This paper presents a model-based parallelization approach to parallelize embedded systems on single-ISA heterogeneous multicore processors, especially processors with the ARM big.LITTLE architecture, wherein the core assignment of the Simulink blocks is determined based on the control design constraints and characteristics of the big.LITTLE architecture. The proposed approach uses a hierarchical clustering method on Simulink blocks to reduce the problem scale, and an integer linear programming (ILP) formulation to determine the core assignment solution, considering load balancing and minimization of inter-core communication across cores with different performances. Finally, we generate the parallel code of the model based on the core assignment solution for execution on the processors. We evaluate the proposed approach by comparing it with existing methods and generating the parallel code on a single-board computer with the big.LITTLE architecture to determine its effectiveness.

QT-Adaptation Engine: Adaptive QoS-Aware Scheduling and Governing in Thermally Constrained Mobile Devices

Modern mobile devices are equipped with heterogeneous multicore processors which integrate asymmetric CPU cores and GPUs. More cores require additional power consumption and produce more heat, which can result in performance degradation due to thermal throttling. To address this issue, this paper proposes a QT-adaptation engine to monitor current temperature and quality of service (QoS), and derives a QoS-temperature model (QT-model) through a run-time learning mechanism (QT-learning) to balance dynamic workloads and dynamic thermal behavior. Based on the derived QT-model, the QT-adaptation engine migrates threads among cores using the proposed critical thread aware scheduler to ensure high QoS, and uses a self-adapting governor to meet the temperature constraint for system robustness. The concept is implemented on a commercial LG Nexus $5\times$ and evaluated using real world applications. Results show the proposed approach increases the frame per second rate by up to 25% compared to other current methods while meeting temperature constraints.

Efficient large-scale heterogeneous debugging using dynamic tracing

Abstract Heterogeneous multi-core and many-core processors are increasingly common in personal computers and industrial systems. Efficient software development on these platforms needs suitable debugging tools, beyond traditional interactive debuggers. An alternative, to interactively follow the execution flow of a program, is tracing within the debugging environment, as long as the tracer has a minimal overhead. In this paper, the dynamic tracing infrastructure of GNU debugger (GDB) was investigated to understand its performance limitations. Thereafter, we propose an improved architecture for dynamic tracing on many-core processors within GDB, and demonstrate its scalability on highly parallel platforms. In addition, the scalability of the thread data collection and presentation component was studied and new views were proposed within the Eclipse Debugging Service Framework and the Trace Compass visualization tool. With these scalability enhancements, debuggers such as GDB can more efficiently help debugging multi-threaded programs on heterogeneous many-core processors composed of multi-core CPUs, and GPUs containing thousands of cores.

An energy-efficient, QoS-aware and cost-effective scheduling approach for real-time workflow applications in cloud computing systems utilizing DVFS and approximate computations

Green cloud computing attracts significant attention from both academia and industry. One of the major challenges involved, is to provide a high level of Quality of Service (QoS) in a cost-effective way for the end users and in an energy-efficient manner for the cloud providers. Towards this direction, this paper presents an energy-efficient, QoS-aware and cost-effective scheduling strategy for real-time workflow applications in cloud computing systems. The proposed approach utilizes per-core Dynamic Voltage and Frequency Scaling (DVFS) on the underlying heterogeneous multi-core processors, as well as approximate computations, in order to fill in schedule gaps. At the same time, it takes into account the effects of input error on the processing time of the component tasks. Our goal is to provide timeliness and energy efficiency by trading off result precision, while keeping the result quality of the completed jobs at an acceptable standard and the monetary cost required for the execution of the jobs at a reasonable level. The proposed scheduling heuristic is compared to two other baseline policies, under the impact of various QoS requirements. The simulation experiments reveal that our approach outperforms the other examined policies, providing promising results.

A Method to Construct Task Scheduling Algorithms for Heterogeneous Multi-Core Systems

The use of heterogeneous multicore processors (HMP) is spreading rapidly from data centers to large-scale deployment in smartphones because they give greater flexibility to adapt to power constraints and performance needs. In this study, we show that an intelligent task scheduler is critical for improving the performance and energy efficiency in an HMP environment. We assume that the tasks are independent in the environment, with hard real-time constraints and multicore systems, where the processors can be manipulated to change the clock cycle speed and power levels. Tasks are assumed to arrive aperiodically where the tasks are applications from the SPEC CPU 2006 benchmark suite. In the evaluation, we used a real system comprising of two multicore processors, which supported on-the-fly dynamic voltage/frequency scaling. We extracted several important components from previously proposed algorithms and combined them to construct algorithms with better performance. Our results showed that some of the best combinations reduced the energy consumption and achieved a better completion rate in the environment. In addition, a method is proposed for calculating the upper-bound of the task completion rate and energy consumption so that there is a guide as to how near the results are to the optimal performance.

Multi-objective league championship algorithm for real-time task scheduling

League championship algorithm is a recently proposed population-based evolutionary algorithm for finding global optimal solutions in continuous optimization problems. The proposed work adopts the algorithm by modifying the team formation step for solving real-time task scheduling problem in heterogeneous multiprocessors. Two different objectives: tardiness and energy consumption were considered for scheduling. Our proposed algorithm is implemented using Java and tested using the graphs generated by the benchmark tools: task graph for free and task graph generator. Simulation results prove the performance of the proposed algorithm is better in terms of the objective functions over the other existing metaheuristic algorithms such as genetic algorithm, ant colony optimization and particle swarm optimization.

Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors

While single-ISA heterogeneous multi-core processors are widely used in mobile computing, typical code generations optimize the code for a single target core, leaving it less suitable for the other cores in the processor. We present a microarchitecture-aware code generation methodology to mitigate this issue. We first suggest adopting Function-Multi-Versioning (FMV) to execute application codes utilizing a core at full capacity regardless of its microarchitecture. We also propose to add a simple but powerful backend optimization pass in the compiler to further boost the performance of applicable cores. Based on these schemes, we developed an automated flow that analyzes the program and generates multiple versions of hot functions tailored to different microarchitectures. At runtime, the running core chooses an optimal version to maximize computation performance. The measurements confirm that the methodology improves the performance of Cortex-A55 and Cortex-A75 cores in Samsung's next-generation Exynos 9820 processor by 11.2% and 17.9%, respectively, while running TensorFlow Lite.

Progressive Multicore RLNC Decoding With Online DAG Scheduling

A complete generation of packets coded with Random Linear Network Coding (RLNC) can be quickly decoded on a multicore system by scheduling the involved matrix block operations in parallel with an offline (pre-recorded) directed acyclic graph (DAG). The waiting for a complete generation of packets can be avoided with progressive RLNC decoding that commences the decoding (and can decode some packets) before all packets in a generation have been received. This article develops and evaluates a novel progressive RLNC decoding strategy based on the principle of DAG scheduling of parallel matrix block operations. The novel strategy involves helper matrices for conducting the Gauss Jordan elimination based on rows of blocks of matrix elements. The matrix block computations are dynamically scheduled by an online DAG which permits branching, e.g., to skip unnecessary matrix block operations. The throughput and delay of the novel progressive RLNC decoding strategy are evaluated with experiments on two heterogeneous multicore processor boards. The novel progressive RLNC decoding achieves throughput levels on par with state-of-the-art non-progressive (full-generation) RLNC decoding and achieves three times higher throughput than the fastest (highest-throughput) known progressive RLNC decoder for small generation sizes and short data packets. Also, our progressive RLNC decoding greatly reduces receiver delays for moderate to large generation sizes; the delay reductions are particularly pronounced when a low-delay RLNC version is employed (e.g., reduction to one tenth of the non-progressive decoding delay for a generation size of 256 packets).

DBEFT: A Dependency-Ratio Bundling Earliest Finish Time Algorithm for Heterogeneous Computing

Performance effective task scheduling algorithms are essential for taking advantage of the heterogeneous multi-processor in heterogeneous computing environments. In this paper, we present a task scheduling algorithm named as Dependency-ratio Bundling Earliest Finish Time (DBEFT). DBEFT is a list based scheduling algorithm combined with task duplication, which can achieve high performance and low time complexity simultaneously. DBEFT selects the task from the perspective of extending parallelism between tasks instead of giving priorities to tasks on the critical path. Also, DBEFT reduces communication cost by adopting a bundling scheduling strategy. The experiments were conducted on both random graph set and real-world applications, and the results show that DBEFT obtained significant performance improvement, outperforming CEFT by 15%, PEFT by 30% and HEFT 33% in terms of SLR respectively.

Energy-Aware Task Allocation for Heterogeneous Multiprocessor Systems by Using Integer Linear Programming

Energy-Aware Task Allocation for Heterogeneous Multiprocessor Systems by Using Integer Linear Programming

ILP models for the allocation of recurrent workloads upon heterogeneous multiprocessors

The problem of partitioning systems of independent constrained-deadline sporadic tasks upon heterogeneous multiprocessor platforms is considered. Several different integer linear program (ILP) formulations of this problem, offering different trade-offs between effectiveness (as quantified by speedup bound) and running time efficiency, are presented. One of the formulations is leveraged to improve the best speedup guarantee known for a polynomial-time partitioning algorithm, from 12.9 to 7.83. Extensive computational results on synthetically generated instances are also provided to establish the effectiveness of the ILP formulations.

Novel Framework for Designing Representative Usage-Based Benchmarks for Smartphones

Smartphones dominate the consumer electronics market. Heterogeneous multicore processors are nowadays often integrated into smartphones. The power and performance evaluation of mobile multicore processors is a key issue in their design. This paper is the first to address the issue of improving the power and performance in modern, multicore smartphones by revisiting existing benchmarks used for evaluating these devices. Unlike earlier computers, modern consumer devices execute workloads that are characterized by heterogeneous concurrently running processes, which are launched at different times. Yet, modern smartphones architecture designs are still being evaluated using representative benchmark suites comprised of individual programs. This method of evaluation can be very misleading, as it does not represent the way these devices are actually being used. This paper first proposes a novel learning framework that identifies representative usage patterns of various real workloads, where each representative pattern represents a single class in a heterogeneous collection of actual usage patterns. We then use these representative patterns to optimize the power and performance of common multicore computer architectures integrated into smartphones. Our experiments show that using our representative patterns for optimization results in, on average , 11.5% and 16.7% power and performance improvements, respectively, compared to the state-of-art optimization methods.

Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores

Heterogeneous multicore processors (HMPs) are commonly deployed to meet the performance and power requirements of emerging workloads. HMPs demand adaptive and coordinated resource management techniques to control such complex systems. While Multiple-Input-Multiple-Output (MIMO) control theory has been applied to adaptively coordinate resources for single-core processors, the coordinated management of HMPs poses significant additional challenges for achieving robustness and responsiveness, due to the unmanageable complexity of modeling the system dynamics. This paper presents, for the first time, a methodology to design robust MIMO controllers with rapid response and formal guarantees for coordinated management of HMPs. Our approach addresses the challenges of: (1) system decomposition and identification; (2) selection of suitable sensor and actuator granularity; and (3) appropriate system modeling to make the system identifiable as well as controllable. We demonstrate the practical applicability of our approach on an ARM big.LITTLE HMP platform running Linux, and demonstrate the efficiency and robustness of our method by designing MIMO-based resource managers.

Recent Advances in Heterogeneous Parallel Processing Schemes for Protein- Ligand Docking

Objectives: Molecular docking is widely used for molecular level recognition of leads and compounds which might be useful in the drug discovery domain. Docking is done in order to predict the binding mode and binding affinity of a complex which is formed by two or more constituent molecules with known structure. Objective is to find out the best available techniques in the docking domain. Methodology: We use Hex tool to simulate the various parameters and find out the bottlenecks. Fast Fourier Transform (FFT) and Spherical Polar Transformations (SPT) are applied to study the docking process. Findings: Various performance bottlenecks and parameter effect on the simulation. Improvements: It is observed that GPU optimization is possible by using FFT and SPT. The ligand space considered was limited to shape complementary. This could be considered for future e work.