Required Hardware Resources Research Articles

A novel blade tip clearance measurement method based on event capture technique

Blade tip clearance (BTC) measurement is an essential technology in turbomachinery health monitoring so as to enhance efficiency and reliability as well as to ensure timely maintenance. The existing BTC measurement methods, which based on continuous sampling technique, depend highly on the devices sampling frequency, data transmission speed, storage memory, and computation capability, can hardly achieve online real-time measurement and long-term continuous monitoring. BTC distribution of a turbomachinery possesses discreteness, symmetry, monotonicity and quasi-periodicity, based on these characteristics, this paper proposes a novel BTC measurement method based on event capture technique. The method sorts the sensors signal into distinct events according to pre-set trigger thresholds, describes the relationship between the event kinds and the BTC distribution via mathematical equations, and solves the BTC values accordingly. The measurement error, measuring sensitivity, measurable range, and solving stability of the proposed method are demonstrated. A test to validate the proposed method for BTC measurement in the inlet section of a turboengine is performed, and the results show that, the event capture technique is capable of achieving fast and accurate BTC measurement. The proposed methods own a measurement error within 0.02 mm (for dual-channel configuration) and 0.01 mm (for multi-channel configuration) comparing with the continuous sampling technique. Meanwhile their hardware resource requirement are reduced to 0.02% (for dual-channel configuration) and 0.1% (for multi-channel configuration) comparing with the continuous sampling technique. For processing these performances, the proposed method can be applied for online real-time BTC measurement and long-term continuous BTC monitoring.

High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures

FPGA Implementation and Evaluation of an Approximate Hilbert Transform-Based Envelope Detector for Ultrasound Imaging Using the DSP Builder Development Tool.

In this paper, we present the FPGA implementation of an approximate Hilbert Transform-based envelope detector to compute the magnitude of the received ultrasound echo signals in real-time using a Model-based design flow. The proposed architecture exploits the negative odd-symmetry and interleaved zero-valued coefficients of a Hilbert Transform-based FIR filter to reduce hardware resource requirements and complexity. The hardware design is modeled using the DSP Builder development tool allowing the automatic generation of HDL algorithms directly from the Matlab/Simulink environment. The generated VHDL code was synthesized for an Intel Stratix IV FPGA and validated on a Terasic DE4-230 board. The accuracy and performance of the envelope detector are analyzed with real ultrasound phantom data for different filter orders, coefficient length and two filter design methods: Equiripple and Least-Squares. The normalized residual sum of squares (NRSS) and the normalized root mean square error (NRMSE) cost functions are used for comparison with the reference absolute value of the Matlab Hilbert function. The results demonstrate that the proposed method yields similar results to conventional envelope detection methods, while being simpler to implement and requiring lower computational cost.

A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter

Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system generator based on the Zynq-7000 development board (ZYBO). The technique is compared, for reliability and hardware resources requirement, with triple modular redundancy (TMR), five modular redundancy (FMR) and the modified triplex–duplex architecture. Furthermore, radiation induced failures are emulated by switching all duplicated modules inputs to different signals, or to ground during simulation. The simulation results show that the proposed technique has 25% and 30%longer expected life compared to TMR and FMR techniques, respectively, and has the lowest hardware resource requirement compared to FMR and the modified triplex–duplex techniques.

A JND-Based Pixel-Domain Algorithm and Hardware Architecture for Perceptual Image Coding.

This paper presents a hardware efficient pixel-domain just-noticeable difference (JND) model and its hardware architecture implemented on an FPGA. This JND model architecture is further proposed to be part of a low complexity pixel-domain perceptual image coding architecture, which is based on downsampling and predictive coding. The downsampling is performed adaptively on the input image based on regions-of-interest (ROIs) identified by measuring the downsampling distortions against the visibility thresholds given by the JND model. The coding error at any pixel location can be guaranteed to be within the corresponding JND threshold in order to obtain excellent visual quality. Experimental results show the improved accuracy of the proposed JND model in estimating visual redundancies compared with classic JND models published earlier. Compression experiments demonstrate improved rate-distortion performance and visual quality over JPEG-LS as well as reduced compressed bit rates compared with other standard codecs such as JPEG 2000 at the same peak signal-to-perceptible-noise ratio (PSPNR). FPGA synthesis results targeting a mid-range device show very moderate hardware resource requirements and over 100 Megapixel/s throughput of both the JND model and the perceptual encoder.

Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE

In order to meet the latency requirements of the ultra-reliable low latency communication (URLLC) mode of the third-generation partnership project’s long term evolution (LTE) mobile communication standard, this paper proposes a novel turbo decoding algorithm that supports an arbitrarily high degree of parallel processing, facilitating significantly higher processing throughputs and substantially lower processing latencies than the state-of-the-art (SOTA) LTE turbo decoder. As in conventional turbo decoding algorithms, the proposed Arbitrarily Parallel Turbo Decoder (APTD) decomposes each frame of information bits into a sequence of windows, where the bits within different windows are processed simultaneously using forward and backward recursions in a serial manner. However, in contrast to conventional turbo decoding algorithms, the APTD does not require different windows to be composed of an identical number of bits, which allows the use of an arbitrary number of windows and hence an arbitrary degree of parallelism, when decoding information bits of an arbitrary frame length. Furthermore, conventional turbo decoding algorithms alternate between simultaneously processing the windows in the upper decoder and those in the lower decoder. By contrast, the APTD processes the odd-indexed windows in the upper decoder at the same time as the even-indexed windows in the lower decoder and alternates between this and the reversed arrangement, hence further improving the decoding throughput and latency. Furthermore, the APTD achieves a reduced hardware resource requirement by calculating the extrinsic information based only on the outputs of the forward recursions, rather than based on both the forward and backward recursions of conventional turbo decoding algorithms. We demonstrate that the proposed APTD achieves superior latency, throughput, and computational efficiency than the SOTA LTE turbo decoder at all frame lengths, but particularly at the short frame lengths that are typically used in URLLC approaches. For example, at a frame length of $N={504}$ bits, the proposed APTD achieves an FER of 10−5 at the same $E_{b}/N_{0}$ as $I=8$ iterations of a conventional turbo decoder but with a computational efficiency that is 6 times higher than that of the SOTA turbo decoder, while achieving a latency and throughput that are 0.7 and 1.4 times those of the SOTA decoder, respectively.

A Reconfigurable Architecture for Discrete Cosine Transform in Video Coding

Discrete cosine transform (DCT) is an indispensable module in video codecs and is a major part in many video coding standards including the latest high efficiency video coding (HEVC). As the video resolution increases, both transform sizes and the number of transforms increase continuously which poses challenges to the reusability design especially in hardware implementation. This paper presents reconfigurable transform architecture to flexibly support the reusability of different transform sizes. The proposed architecture maximally reuses the hardware resources by rearranging the order of input data for different transform sizes while still exploiting the butterfly property. Furthermore, this architecture supports reconfigurable throughput according to different hardware resource requirements. By applying the proposed architecture to the field-programmable gate array (FPGA) design of HEVC core transform matrices, the synthesis results show much lower consumption of hardware resources comparing to existing methods in the literature. The implementation in Altera's Stratix III FPGA can operate at 139 MHz and supports real-time processing of 3840×2160 ultrahigh definition video at a minimum of 45 f/s and up to 359 f/s for different DCT sizes.

BulkSort: System Design and Parallel Hardware Implementation Considerations

Algorithms are commonly perceived as difficult subjects. Many applications today require complex algorithms. However, the researchers look for ways to make them as simple as possible. In high time demanding fields, the process of sorting represents one of the foremost issues in the data structure for searching and optimization algorithms. In parallel processing, we divide program instructions among multiple processors by breaking problems into modules that can be executed in parallel, to reduce the execution time. In this paper, we proposed a novel parallel, re-configurable and adaptive sorting network of the BulkSort algorithm. Our architecture is based on simple and elementary operations such as comparison and binary shifting. The main strength of the proposed solution is the ability to sort in parallel without memory usage. Experimental results show that our proposed model is promising according to the required resources and its ability to perform a high-speed sorting process. In this study, we take into account the analysis result of the Simulink design to establish the required hardware resources of the proposed system.

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations

In low-density parity check (LDPC) decoder implementations, the architecture of the node processing units (NPUs) has a significant impact both on the hardware resource requirements and on the processing throughput. Additionally, some NPU architectures impose limitations on the decoder’s support for intra- or interstandard LDPC code flexibility at run-time. In this brief, we present a generalised algorithmic method of constructing NPUs that support run-time flexibility while maintaining a low hardware resource requirement and high maximum operating frequency. FPGA-based synthesis results demonstrate that the proposed architecture offers a significantly improved hardware efficiency, when compared to two commonly employed alternatives.

Experimental demonstration of a directionally-unbiased linear-optical multiport.

All existing optical quantum walk approaches are based on the use of beamsplitters and multiple paths to explore the multitude of unitary transformations of quantum amplitudes in a Hilbert space. The beamsplitter is naturally a directionally biased device: the photon cannot travel in the reverse direction. This causes rapid increases in the optical hardware resources required for complex quantum walk applications, since the number of options for the walking particle grows with each step. Here we present the experimental demonstration of a directionally-unbiased linear-optical multiport, which allows reversibility of the photon direction. An amplitude-controllable probability distribution matrix for a unitary three-edge vertex is reconstructed with only linear-optical devices. Such directionally-unbiased multiports allow direct execution of quantum walks over a multitude of complex graphs and in tensor networks. This approach would enable simulation of complex Hamiltonians of physical systems and quantum walk applications in a more efficient and compact setup, substantially reducing the required hardware resources.

Machine Learning in High Energy Physics Community White Paper

Machine learning is an important applied research area in particle physics, beginning with applications to high-level physics analysis in the 1990s and 2000s, followed by an explosion of applications in particle and event identification and reconstruction in the 2010s. In this document we discuss promising future research and development areas in machine learning in particle physics with a roadmap for their implementation, software and hardware resource requirements, collaborative initiatives with the data science community, academia and industry, and training the particle physics community in data science. The main objective of the document is to connect and motivate these areas of research and development with the physics drivers of the High-Luminosity Large Hadron Collider and future neutrino experiments and identify the resource needs for their implementation. Additionally we identify areas where collaboration with external communities will be of great benefit.

The VISPA internet-platform in deep learning applications

Latest developments in many research fields indicate that deep learning methods have the potential to significantly improve physics analyses. They not only enhance the performance of existing algorithms but also pave the way for new measurement techniques that are not possible with conventional methods. As the computation is highly resource-intensive both dedicated hardware and software are required to obtain results in a reasonable time which poses a substantial entry barrier. We provide direct access to this technology after a revision of the internet platform VISPA to serve the needs of researches as well as students. VISPA equips its users with working conditions on remote computing resources comparable to a local computer through a standard web browser. For providing the required hardware resources for deep learning applications we extend the CPU infrastructure with a GPU cluster consisting of 10 nodes with each 2 GeForce GTX 1080 cards. Direct access through VISPA, preinstalled analysis software and a workload management system allowed us on one hand to support more than 100 participants in a workshop on deep learning and in corresponding university classes, and on the other hand to achieve significant progress in particle and astroparticle research. We present the setup of the system and report on the performance and achievements in the above mentioned usecases.

Cloud Computing for Infectious Disease Surveillance and Control: Development and Evaluation of a Hospital Automated Laboratory Reporting System

BackgroundOutbreaks of several serious infectious diseases have occurred in recent years. In response, to mitigate public health risks, countries worldwide have dedicated efforts to establish an information system for effective disease monitoring, risk assessment, and early warning management for international disease outbreaks. A cloud computing framework can effectively provide the required hardware resources and information access and exchange to conveniently connect information related to infectious diseases and develop a cross-system surveillance and control system for infectious diseases.ObjectiveThe objective of our study was to develop a Hospital Automated Laboratory Reporting (HALR) system based on such a framework and evaluate its effectiveness.MethodsWe collected data for 6 months and analyzed the cases reported within this period by the HALR and the Web-based Notifiable Disease Reporting (WebNDR) systems. Furthermore, system evaluation indicators were gathered, including those evaluating sensitivity and specificity.ResultsThe HALR system reported 15 pathogens and 5174 cases, and the WebNDR system reported 34 cases. In a comparison of the two systems, sensitivity was 100% and specificity varied according to the reported pathogens. In particular, the specificity for Streptococcus pneumoniae, Mycobacterium tuberculosis complex, and hepatitis C virus were 99.8%, 96.6%, and 97.4%, respectively. However, the specificity for influenza virus and hepatitis B virus were only 79.9% and 47.1%, respectively. After the reported data were integrated with patients’ diagnostic results in their electronic medical records (EMRs), the specificity for influenza virus and hepatitis B virus increased to 89.2% and 99.1%, respectively.ConclusionsThe HALR system can provide early reporting of specified pathogens according to test results, allowing for early detection of outbreaks and providing trends in infectious disease data. The results of this study show that the sensitivity and specificity of early disease detection can be increased by integrating the reported data in the HALR system with the cases’ clinical information (eg, diagnostic results) in EMRs, thereby enhancing the control and prevention of infectious diseases.

Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders

The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC) algorithms, is an ideal candidate for designing high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on experimental studies. We propose a heuristic that switches the decoding from GaB to PGaB after certain number of iterations and show that our heuristic reduces the average iteration count by up to 62% compared with GaB. We evaluate the hardware performance and resource requirement trends of PGaB over three quasicyclic codes using the Xilinx Virtex-6 field programmable gate array. We extend this analysis to performance comparison over our implementations of gradient descent bit flipping (GDBF) and probabilistic GDBF (PGDBF) algorithms for each code studied in this paper. We achieve up to four orders of magnitude better error correction performance than the GaB with less than 1% loss in throughput performance. Our heuristic consistently results with an improvement in maximum operational clock rate across all codes compared with the GDBF and PGDBF.

Towards a Reference Model of Software Resources Quality

International standards for software product quality classify software resources as a non-functional requirement for software product. Resources requirements based-standards describe required resources requirements related to software and hardware requirements, in which hardware resources requirements specify requirements relevant to hardware environment in which the software will operate. Whereas, software resources requirements specify sizing and timing requirements required by software product. This paper propose a reference model to identify and measure resources requirements of software product quality based on ISO international standards. The proposed reference model is experimented to present its applicability using the software specifications of an ATM machine to identify and measure the functional size of resources requirements independently from development technology. This measure take place at an early phase of the software development life cycle and used by software project managers as one of the primary inputs for the effort estimation process of software products.

Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator.

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

Data Acquisition and Analysis of Smart Campus Based on Wireless Sensor

In order to speed up the information construction process of data collection and analysis for smart campus, this paper aiming at the problems existing in the smart campus planning and current research. The acquisition network of underlying data is designed using 6LoWPAN wireless sensor technology which based on IPv6 technology and has the advantages of low power consumption, short distance and low requirement of hardware resources. At the same time, the embedded gateway is designed to interconnection of 6LoWPAN network and Ethernet based on 6–4 tunnel technology and the Netfilter framework. In addition, the sharing platform of data resource is designed using the C/S architecture, and realization the data acquisition system for smart campus based on 6LoWPAN wireless sensor technology. Again, the acquisition of variety data and equipment management is achieved by designing of data acquisition rules, data acquisition drive, data acquisition equipment online management. Finally, the problem of data storage and management of the smart campus data acquisition system is solved by using the powerful storage and processing capabilities for date of Hadoop distributed system. At the same time, the safe, accurate service to date end is realized by data models encapsulate services. Therefore, smart campus is using the new generation of information technology such as internet of things, cloud computing and big data to perceive, store, manage and analyse all the key information of campus system, and serves the teachers and students in the campus.

Very Efficient Tone Reservation PAPR Reduction Fully Compatible With ATSC 3.0 Standard: Performance and Practical Implementation Analysis

A common issue in any multicarrier communication system such as the American digital video broadcasting (ATSC 3.0) standard is the high peaks of the transmitted signal. This disadvantage constrains the high power amplifiers to be deployed in their linear region which lowers their power efficiency. To overcome this issue, various techniques aiming at reducing the signal fluctuations have been investigated. Recently, Tone Reservation (TR)-based algorithms have been studied and proposed for the second generation of digital video broadcasting (DVB-T2) and ATSC 3.0 standards. The algorithm is essentially based on an iterative gradient approach to cancel one peak of the time-domain signal at each iteration. In this paper, we propose a novel TR-based algorithm implementable and compatible with the ATSC 3.0 standard and named as grouped carrier peak windowing (GCPW). This algorithm is based on a new kernel definition targeting the cancellation of multiple signal peaks at a time which highly reduces the total number of iterations, therefore reducing the system global latency and being more suited for implementation in today’s ATSC 3.0 transmitters. Taking into account hardware resources requirements, we propose a new method to select the highest signal peaks to be considered in the PAPR reduction process. Hence, the system latency, complexity, and memory resources are reduced and better performance than the ATSC 3.0 gradient-based algorithm can be offered. The implementation of the GCPW algorithm in fixed-point architectures is also studied and optimized in this paper. We demonstrate through simulation results that the proposed algorithm offers very good performance/latency/complexity/memory tradeoff in both floating and fixed point implementations.

Reverse Converters for the Moduli Set { $$2^{n}, 2^{n-1}-1,2^{n}-1, 2^{n+1}-1\}(n\,\hbox {Even})$$ 2 n , 2 n - 1 - 1 , 2 n - 1 , 2 n + 1 - 1 } ( n Even )

In this paper, two residue number system (RNS) to binary converters for the moduli set { $$2^{n}, 2^{n-1}-1,2^{n}-1, 2^{n+1}-1\}$$ for (n even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (A), conversion time (T), AT and $$AT^{2}$$ trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the $$(2^{n} +1)$$ channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented.

Comparison of a genetic programming approach with ANFIS for power amplifier behavioral modeling and FPGA implementation

Accurate modeling of power amplifiers (PA) is of upmost importance in the design process of wireless communication systems where a high linearity and efficiency is required. To deal with the nonlinear behavior of PAs effectively a linearization stage is applied to minimize the distortions of in-band and adjacent transmission channels, which translate to an improvement of the signal integrity and the operation cost of the transmitter system. This paper presents a method based on genetic programming with a local search heuristic (GP-LS) to emulate the electrical memory effects by using the characteristic conversion curves of the radio frequency (RF) PA NXP Semiconductor of 10 W GaN HEMT working at 2.34 GHz. This method is compared with an Adaptive Neuro-Fuzzy Inference Systems (ANFIS) through several performance metrics (NMSE, MAE and correlation coefficient), with GP-LS achieving a better modeling accuracy. Moreover, the models produced by GP-LS permit a reduction in the required hardware resources, when it is implemented on a Field-Programmable Gate Array through the DSP Builder tool. The models are derived using a data-driven approach, posed in two different ways. Firstly, experiments are performed using a testbed Arria V GX for a flexible vector signal generation that provides the raw data of the PA characterization using an LTE-Advanced signal with 10-MHz bandwidth. Secondly, the modeling is derived from a filtered version of the data and then adding a high-frequency signal as a post processing step to approximate the true behavior of the system. In both cases, the models are generated with ANFIS and GP-LS, performing extensive logic-based simulations and implementing the models on a Cyclone III development board. Both approaches are compared based on accuracy and required hardware resources, with GP-LS substantially outperforming ANFIS. These results suggest that the GP-LS models can be implemented in a digital predistortion chain and used in the linearization stage for a RF-PA.