Hardware Modules Research Articles

COVFILTER: A Low-cost Portable Device for the Prediction of Covid-19 for Resource-Constrained Rural Communities

Early identification of COVID-19 is critical for preventing death and significant illness. People living in remote parts of resource-constrained countries find it more difficult to get tested due to a lack of adequate testing. As a result, having a primary filtering tool that can assist us in simplifying bulk COVID testing to prevent community spread is vital. In this paper, we introduce CovFilter, a low-cost portable device for COVID-19 prediction for resource-constrained rural communities, with the goal of encouraging people to be tested for COVID-19 in a more informed manner. CovFilter Hardware Module collects health parameters from three sensors while the CovFilter Prediction Module predicts COVID-19 status using the health data. We train supervised learning algorithms and an artificial neural network to predict COVID-19 from vital sign readings where MultilayerPerceptron outperformed ANN, NaiveBayes, Logistic, SGD, DecisionStump, and SVM with an F1 of 93.22%. We further show that a weighted majority voting ensemble classifier can outperform all single classifiers achieving an F1 of over 94%.

Biological Breakdown of Sports in Athletics Based on Multimedia Image Acquisition Techniques.

This paper provides an in-depth analysis and study of the decomposition of sports biology of athletics events through multimedia image acquisition techniques. The proposed design uses SOPC hardware-software collaboration technology, which makes full use of the parallelism of hardware as well as the flexibility of software to essentially improve the speed of image processing and greatly improve the efficiency of image processing. The high speed and parallelism of hardware are used to realize the image acquisition part with high timing requirements and the preprocessing algorithm with a large number of operations and strong repetition, in addition to the difficulties of many initialization configuration parameters of each peripheral. Additionally, the need for frequent adjustment of peripheral working parameters is solved by making full use of the scalability and flexibility of software, and the control signals output by software can coordinate the work of each hardware module to ensure that each module of the system cooperates. It is also possible to coordinate the work of each hardware module through the control signal output from the software to ensure that each module of the system cooperates and operates in an orderly and efficient manner and provides the possibility of realizing a higher level of the image processing algorithm. The system includes four main factors: swinging action, supporting action, vacating action, and speed rhythm. Based on this system, 14 key kinematic indicators were selected to reflect the technical status of the youth walkers. The landing angle decreased with the increase of speed, and the landing technique was insufficient; it had better control of the large and small arm angle, and their stride width was open, while the other four athletes showed increased tension in the hip joint and upper limb with the increase of walking speed, as well as the wrong action of forward and internal rotation of the large and small arms.

Implementation and integration of image processing blocks in a real-time bottle classification system

A practical solution to the problems caused by the water, air, and soil pollution produced by the large volumes of waste is recycling. Plastic and glass bottle recycling is a practical solution but sometimes unfeasible in underdeveloped countries. In this paper, we propose a high-performance real-time hardware architecture for bottle classification, that process input image bottles to generate a bottle color as output. The proposed architecture was implemented on a Spartan-6 Field Programmable Gate Array, using a Hardware Description Language. The proposed system was tested for several input resolutions up to 1080 p, but it is flexible enough to support input video resolutions up to 8 K. There is no evidence of a high-performance bottle classification system in the state-of-the-art. The main contribution of this paper is the implementation and integration of a set of dedicated image processing blocks in a high-performance real-time bottle classification system. These hardware modules were integrated into a compact and tunable architecture, and was tested in a simulated environment. Concerning the image processing algorithm implemented in the FPGA, the maximum processing rate is 60 frames per second. In practice, the maximum number of bottles that can be processed would be limited by the mechanical aspects of the bottle transportation system.

High-precision time synchronization chip design for industrial sensor and actuator network

Mission-critical (MC) sensor and actuator networks (SANs) are being applied widely for multiaxis motion control of robotic manipulators , particularly for performing MC tasks in smart manufacturing. One of the most challenging tasks in MC-SANs is the development of a precision time synchronization (PTS) protocol. A conventional precision time system uses the IEEE 1588 v2 standard [1] ; however, in MC-SANs, many factors need to be considered when designing an IoT computing system, such as robustness, cost-effectiveness, interoperability and scalability. This study proposes a high-precision time synchronization protocol based on Modbus sensors and actuator networks for an industrial fieldbus network. The PTS protocol design and hardware synthesis are conducted with a consistent and systematic design methodology. GRAFCET is used to model the individual functional modules and hierarchical behavior of the system. The behavior of each module is represented as a sequential–concurrent hybrid discrete event system . We apply high-level synthesis rules to design PTS hardware for a complex PTS system based on the VHSIC hardware description language (VHDL). The PTS hardware module has an embedded PTS algorithm with a proportional error correction model, and the time synchronization accuracy of the precision time protocol (PTP) chip is up to 42 ns. Experimental results demonstrate that our high-performance PTS controller chip can satisfy the requirements of multiaxis motion control and that it is more efficient than other protocols and products designed for similar industrial manufacturing applications.

Connected and automated vehicle platoon maintenance under communication failures

Connected and automated vehicles (CAVs) use vehicle-to-vehicle (V2V) wireless communication to drive in platoons, which can improve traffic efficiency and reduce energy consumption. However, some vehicles in a platoon may experience communication failures for various reasons, such as packet loss, signal blocking, or damage to vehicle communication module hardware. This will result in two phenomena: the platoon communication topology will be changed, and the behavior of vehicles without communication capabilities will degenerate to that of automated vehicles (AVs). The platoon will be unstable under the influence of these two phenomena. To mitigate the impact of these two phenomena on platoons, we propose a dynamic communication topology-based CAV-following model. This model takes into account changes in communication topology in a platoon due to communication failures or perceptual errors resulting from vehicle degradation. Two core features ensure that this model is able to perform platoon maintenance under communication failure. First, the CAVs in a platoon dynamically adjust the weight values of the acquired driving information based on the communication topology. Second, an adaptive Kalman filter (AKF) method is applied to reduce perceptual error. The effectiveness of the platoon maintenance scheme proposed in this study is verified by a series of simulation experiments. The results show that the proposed model can effectively maintain CAV platoons regardless of communication failures under steady-state or non-steady-state traffic flows. This finding indicates that CAV designers should design control schemes that take into account possible changes in the communication topology. Furthermore, our method has potential advantages for improving the platoon stability of CAVs driving on roads where communication is poor.

A Self-Adaptive SEU Mitigation Scheme for Embedded Systems in Extreme Radiation Environments

When electronic systems are working in radiation environments, transient errors, and permanent errors may occur. Static random-access memory (SRAM) has been the one of most significant parts in various semiconductor chips for its high performance and high logic density features. However, because of their dedicated electronic circuits, SRAMs are sensitive to radiation effects. In this article, a portable scheme combined with error correcting code (ECC) and refreshing techniques is proposed to correct errors and mitigate error accumulation in extreme radiation environments. Since the proposed scheme is small and transparent to other modules and no additional latency is introduced, it therefore can be easily applied to the system where the hardware modules are designed with fixed reading and writing latency. We evaluated this design by simulation in a hardware fault injection platform and radiation experiments in the neutron radiation facility. The results obtained in the neutron experiment, where the flux of neutron particles is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$5 \times {\rm 10^6\text{ cm}^2. \ s^{-1}}$</tex-math></inline-formula> , show that the number of bit-flips in 32 kB self-refresh ECC RAM on the Xilinx Artix-7 FPGA remains zero, while the number of bit-flips in unhardened RAM rose to 32 in 1.5 h.

Hardware design of the generic rear transition module for the global trigger system of the ATLAS phase II upgrade

The High-Luminosity Large Hadron Collider is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the Large Hadron Collider Runs 1–3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of the trigger and data acquisition system. Global trigger is a new subsystem in the ATLAS phase-II upgrade, which will bring event filter-like capability to the level-0 trigger system. A common hardware platform in Advanced Telecommunications Computing Architecture form factor named Global Common Module is proposed to be configured as processor nodes in the global trigger. To mitigate the risk and simplify the Global Common Module hardware design, a Generic Rear Transition Module is being developed. The Generic Rear Transition Module, which has been implemented with a Xilinx Versal Prime Field Programmable Gate Array and sufficient multi-gigabit transceivers, cannot only achieve system control and communication with the Front-End Link eXchange, but also provide additional processing or readout capacity.

Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver

In 4G turbo and 5G LDPC, in order to realize a flexible, low-power, low-cost shared general-purpose block interleaving hardware module, it faces the challenges of interleaving structure integration, fewer gate circuits, parallel multistream operation, and switching between standards. Facing these challenges, after studying 3GPP TS 36.212 V15.4.0 and 3GPP TS 38.212 V15.4.0 protocols, common part of two major interleaving module standards is found. For the block interleave module in the rate matching of the 4G downlink turbo code and the bit interleave module after the rate matching of the 5G NR downlink LDPC code, this paper first designs a memory and implements the two codes interleaving on it. Then, based on the Altera Quartus prime platform and ModelSim for functional verification. Experimental results show that under SMIC 28 nm, operating frequency 50MHz, after synopsys synthesis, the memory module area is 0.17 μ m 2 , and the power consumption is 6.45 mW. Through the shared design, 32 bits parallel access, and switching between standards, the proposed scheme reduces the hardware cost, power consumption, and clock overhead, and improves the flexibility of 4G LTE and 5G NR communication downlink hardware implementation.

VLSI Architecture Design and Implementation of CANNY Edge Detection

In One of the most essential methods in digital image processing is edge detection. Because of its capacity to detect edges even in images heavily contaminated by noise, the Canny edge detector is the most widely used edge detection algorithm. A modified canny edge detector is created in MATLAB and implemented in FPGA in this project. The mask is used for gradient calculation, and bilinear interpolation of four pixels is used in non-maximal suppression. In the iris detection subsystem, this edge detector is used as a pre-processing stage. The goal of creating the hardware modules for the canny edge detector was to minimise its complexity, improve its performance, and make it appropriate for VLSI implementation on a reconfigurable FPGA-based platform.

Secure Artificial Intelligence of Things for Implicit Group Recommendations

The emergence of Artificial Intelligence of Things (AIoT) has provided novel insights for many social computing applications, such as group recommender systems. As the distances between people have been greatly shortened, there has been more general demand for the provision of personalized services aimed at groups instead of individuals. The existing methods for capturing group-level preference features from individuals have mostly been established via aggregation and face two challenges: 1) secure data management workflows are absent and 2) implicit preference feedback is ignored. To tackle these current difficulties, this article proposes secure AIoT for implicit group recommendations (SAIoT-GRs). For the hardware module, a secure Internet of Things structure is developed as the bottom support platform. For the software module, a collaborative Bayesian network model and noncooperative game are introduced as algorithms. This secure AIoT architecture is able to maximize the advantages of the two modules. In addition, a large number of experiments are carried out to evaluate the performance of SAIoT-GR in terms of efficiency and robustness.

Remote Device Management via Smart Contracts

With the continued scaling of transistor feature size, the cost of IC development has been escalating. The economics of semiconductor IC development favors high volume manufacturing, while high volume cannot be attained without developing an IC that serves many applications. Some of these applications are in low-margin Internet of Things (IoT) devices, where an SoC cannot command a high price. Consequently, without the ability to customize IC features after production, its lowest-priced application will determine an IC’s price. This motivates the manufacturers to develop chips with provisions for post-manufacturing IC customization. This paper explores how an IC can be programmed repeatedly and securely using blockchain-based smart contracts to allow users to upgrade or <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rent</i> features. The availability of such a system could, for example, allow a buyer to upgrade her processor from a low-end to a high-end part by making an additional payment to the manufacturer. Implementing such a system will require remote device management capabilities. Remote device management presents unique design considerations, such as, necessity for transparency of the actions that a device takes on behalf of a user; the requirement of a trusted arbiter; and provision for management of these devices beyond the intended lifespan. To overcome the challenges of transparency, longevity, and the necessity of a trusted arbiter, we propose embedded smart contracts in concert with a blockchain. Our proposed smart contract takes the device feature configuration request as input and outputs the corresponding configuration. To support remote, secure, and authorized updates, we propose an on-die hardware module which communicates with the smart contract and enforces its functionalities. This was prototyped using a programmable system-on-chip working in concert with Ethereum blockchain. The prototype demonstrates the feasibility and practicality of the proposed solution.

Implementation of a Security System in IaaS Cloud Server through an Encrypted Blockchain

Infrastructure as a Service (IaaS) is a kind of cloud sharing service allocated to different category of application at the same time. The shared cloud services are provided through internet for computing, networking, and data storage applications. The utilization of IaaS reduces the maintenance and installation cost of physical hardware modules at the base station. The cloud service providers configure their available cloud components with respect to the suitability of the user requirements. The security protocol available in the IaaS servers are usually better than the traditional local servers. However, the IaaS servers are also open to attacks when the modules encounter misconfiguration and vulnerabilities. The work enforces an encrypted blockchain model for enhancing the quality of service in the IaaS systems on handling image data.

Open-source, Python-based, hardware and software for controlling behavioural neuroscience experiments.

Laboratory behavioural tasks are an essential research tool. As questions asked of behaviour and brain activity become more sophisticated, the ability to specify and run richly structured tasks becomes more important. An increasing focus on reproducibility also necessitates accurate communication of task logic to other researchers. To these ends, we developed pyControl, a system of open-source hardware and software for controlling behavioural experiments comprising a simple yet flexible Python-based syntax for specifying tasks as extended state machines, hardware modules for building behavioural setups, and a graphical user interface designed for efficiently running high-throughput experiments on many setups in parallel, all with extensive online documentation. These tools make it quicker, easier, and cheaper to implement rich behavioural tasks at scale. As important, pyControl facilitates communication and reproducibility of behavioural experiments through a highly readable task definition syntax and self-documenting features. Here, we outline the system's design and rationale, present validation experiments characterising system performance, and demonstrate example applications in freely moving and head-fixed mouse behaviour.

A modular agricultural robotic system (MARS) for precision farming: Concept and implementation

AbstractIncreasing global population, climate change, and shortage of labor pose significant challenges for meeting the global food and fiber demand, and agricultural robots offer a promising solution to these challenges. This paper presents a new robotic system architecture and the resulting modular agricultural robotic system (MARS) that is an autonomous, multi‐purpose, and affordable robotic platform for in‐field plant high throughput phenotyping and precision farming. There are five essential hardware modules (wheel module, connection module, robot controller, robot frame, and power module) and three optional hardware modules (actuation module, sensing module, and smart attachment). Various combinations of the hardware modules can create different robot configurations for specific agricultural tasks. The software was designed using the Robot Operating System (ROS) with three modules: control module, navigation module, and vision module. A robot localization method using dual Global Navigation Satellite System antennas was developed. Two line‐following algorithms were implemented as the local planner for the ROS navigation stack. Based on the MARS design concept, two MARS designs were implemented: a low‐cost, lightweight robotic system named MARS mini and a heavy‐duty robot named MARS X. The autonomous navigation of both MARS X and mini was evaluated at different traveling speeds and payload levels, confirming satisfactory performances. The MARS X was further tested for its performance and navigation accuracy in a crop field, achieving a high accuracy over a 537 m long path with only 15% of the path having an error larger than 0.05 m. The MARS mini and MARS X were shown to be useful for plant phenotyping in two field tests. The modular design makes the robots easily adaptable to different agricultural tasks and the low‐cost feature makes it affordable for researchers and growers.

A General Framework for Accelerator Management Based on ISA Extension

Thanks to the promised improvements in performance and energy efficiency, hardware accelerators are taking momentum in many computing contexts, both in terms of variety and relative weight in the silicon area of many chips. Commonly, the way an application interacts with these hardware modules has many accelerator-specific traits and requires ad-hoc drivers that usually rely on potentially expensive system calls to manage accelerator resources and access orchestration. As a consequence, driver-based interfacing is far from uniform and can expose high latency, limiting the set of tasks suitable for acceleration. In this paper, we propose a uniform and low-latency interface based on Instruction Set Architecture (ISA) extension. All the previous studies that proposed extensions, were deeply tailored to address a single accelerator. One of the biggest disadvantages of those methods is their inability to scale. Adding more of these accelerators to one System-on-Chip (SoC) would result in ISA bloat, increasing power consumption and complexifying the decoding phase proportionally. Our proposed framework consists of a six-instruction ISA extension and the corresponding architectural support that implements the interface abstraction and the reservation logic at the hardware level. Our proposal allows controlling a broad class of integrated accelerators directly from the CPU. The proposed framework is ISA-independent, which means that it is applicable to all the existing ISAs. We implement it on the gem5 simulator by extending the RISC-V ISA. We evaluate it by simulating three compute-intensive accelerators and comparing our interfacing with a conventional driver-based one. The benchmarks highlight the performance benefits brought by our framework, with up to 10.38x speed up, as well as the ability to seamlessly support different accelerators with the same interface. The speed up advantage of our technique diminishes as the granularity of the workloads increases and the overhead for driver-based accelerators becomes less important. We also show that the impact of its hardware components on chip area and power consumption is limited.

Опыт автоматизации физиологических экспериментов

The article describes experiences accumulated over the past decades by I. P. Pavlov Institute of Physiology RAS. They are related to the development and implementation of automation systems for physiological experiments. The article provides examples of developing hardware tools for measuring signals, converting them into digital form, data entry and accumulation to be used on general-purpose computers as well as systems of mini-computers, micro-computers, personal computers and custom-made problem-oriented hardware modules for automating physiological experiments in the main areas of research conducted at Pavlov Institute of Physiology. The article also focuses on the conceptual development of problem-oriented software, data base management systems, and graphical display of results. In particular, it discusses several cases of the development of hardware and software modules for various physiological experiments: modules used in the system for the assessment of the functional state of human respiratory muscles, the examination of contractile function of blood vessels and nodes of the circulatory and lymphatic systems, for monitoring changes in the frequency of impulse activity of neurons, for organizing a controlled electrical effect on a laboratory animal in behavioral experiments, for measuring the vital parameters of laboratory animals in experiments on the mechanisms of visceral pain.

ПРИОРИТЕТНЫЕ НАПРАВЛЕНИЯ И МЕРОПРИЯТИЯ СОВРЕМЕННОЙ ЦИФРОВИЗАЦИИ В МЕЛИОРАЦИИ

Purpose: formation of priority directions and effective measures for developing modern digitalization in land reclamation, corresponding to a high-tech, sustainable, environmentally safe domestic crop production system. Materials and methods. The object of research is the priority areas and activities of modern digitalization of production and the social sphere of the economy. The subject is successful digitalization solutions in the field of land reclamation. As research materials, the conceptual provisions of the departmental project and the Digital Agriculture platform of the Ministry of Agriculture of Russia, information and data obtained from open sources were used. The fundamental research methods are methods of comparative and systematic analysis of the collected and systematized materials on the research theme. Results. The analysis of the state of the domestic reclamation water management complex was carried out, and the expediency of its digitalization based on platform approaches was revealed. The key directions of land reclamation digitalization are proposed, including the processes of design, construction, operation of land reclamation facilities and the processes of state management of land reclamation activities, which should be based on the departmental platform “Digital Land Reclamation” of the Ministry of Agriculture of Russia. The functional structure of the digital platform project was formed and characterized as part of the software and hardware modules: “Efficient reclamation and water management complex”, “Intelligent reclamation system”, “Smart reclamation field”, “Safe reclamation”, “Competitive enterprise” and “Professional melioration”. Conclusion. Updating the digitalization of Russian agricultural production will require the consolidation of all participants in digital solutions in the field of land reclamation in terms of preparing a detailed, evidence-based concept for the development of the Digital Land Reclamation platform, coordinated with the departmental project “Digital Agriculture”.

Sensor Based Classification and Evaluation Methods using Machine Learning Algorithm for the Evaluation of Indian Traditional Medicine (Siddha)

The present work analyses sensor based classification and evaluation methods for the evaluation of churna. The churna is a powdered form of Siddha medicine. The churna is evaluated based on organoleptic and physicochemical parameters. The organoleptic parameters such as color and physicochemical parameters such as moisture content value and pH value are analysed in this work. The proposed methodology facilitates the development and integration of hardware and software modules for churna identification and classification. The proposed hardware setup comprises Raspberry pi camera, color sensor, moisture sensor and pH sensor interfaced with raspberry pi 3b. Churnas are discriminated by classifying the color values using machine learning algorithms such as the Support Vector Machine (SVM) and Random Forest (RF) classifiers separately. The experimental results depict that the performance of the RF Classifier excels the SVM Classifier in churna name identification with greater accuracy, sensitivity and specificity.

Интеграционный подход в исследовании сосудов плаценты при преэклампсии

Introduction. Preeclampsia is key in obstetric pathology, which is one of the causes of maternal and perinatal morbidity and mortality. It is due to the difficulties of diagnosis, variable clinical picture, severity, and high risk of an unfavorable outcome. This problem requires special attention not only from obstetricians and gynecologists, but also from pathologists who make intravital morphological diagnosis ofplacenta in women with preeclampsia. The purpose of the study was to perform amorphological, morphometric, and immunohistochemical analysis of obliterative angiopathy in the vessels of placental stem villi with preeclampsia of varying severity. Materials and methods.We studied 60 placentas, 40 of which were from women having preeclampsia of varying severity, as well as 20 healthy placentas (the comparison group). For morphometric studies, an automated histological analysis system Leica Application Suite hardware and software module based on a Leica DM4000B microscope was used. The immunohistochemical study was carried out with markers CD34, VEGF-A, and endothelial NOS. Results. We established a directly proportional relationship between the degree of preeclampsia and the severity of arteriole lumen obliteration of the stem villi, and accordingly the degree of placental insufficiency. The most pronounced disorders of fetoplacental circulation were observed in combined severe preeclampsia and extragenital pathology. Conclusion. The data obtained allow us to confirm the significance of obliterative angiopathy in preeclamptic placentas as an integral component. Prevention of ischemic changes in the placenta, where obliterative angiopathy of the villus vessels plays a leading role, is an urgent medical problem that requires an objective approach to predict the condition of the newborn. Keywords: preeclampsia, placenta, obliterative angiopathy, morphometric, immunohistochemical study

Результаты исследований по разработке аппаратурно-программного обеспечения для наземно-подземного электромагнитного зондирования

Results of the research on development of the hardware-software complex for surface-to-mine electromagnetic sounding is considered in the paper. It taking into account its effectiveness, informativeness and peculiarities of its practical implementation. On the base of experimental studies and numerical analysis, the hardware and software modules providing synchronization of the transmitter and receiver, visual inspection of the measured signal including its frequency structure and amplitudes during the field observations with specified parameters was developed. Results of the experimental studies using the hardware-software complex showed technological effectiveness and prospects of its practical implementation to control physical state of the water protective strata over the salt mines.