Hardware Implementations Of Cryptographic Algorithms Research Articles

FFCSA - Finite Field Constructions, Search, and Algorithms

In this work we present the new GAP package FFCSA - Finite Field Constructions, Search, and Algorithms. It was designed to enable Design Space Exploration for hardware implementations of cryptographic algorithms defined over finite fields. FFCSA constructions and searches are used to produce the design space, and FFCSA algorithms, parameterized for the current candidate field, are used to generate expressions needed for implementation in hardware.

SCRIPT

Power side-channel attacks (SCAs) have been proven to be effective at extracting secret keys from hardware implementations of cryptographic algorithms. Ideally, the power side-channel leakage (PSCL) of hardware designs of a cryptographic algorithm should be evaluated as early as the pre-silicon stage (e.g., gate level). However, there has been little effort in developing computer-aided design (CAD) tools to accomplish this. In this article, we propose an automated CAD framework called SCRIPT to evaluate information leakage through side-channel analysis. SCRIPT starts by defining the underlying properties of the hardware implementation that can be exploited by side-channel attacks. It then utilizes information flow tracking (IFT) to identify registers that exhibit those properties and, therefore, leak information through the side-channel. Here, we develop an IFT-based side-channel vulnerability metric ( SCV ) that is utilized by SCRIPT for PSCL assessment. SCV is conceptually similar to the traditionally used signal-to-noise ratio (SNR) metric. However, unlike SNR, which requires thousands of traces from silicon measurements, SCRIPT utilizes formal methods to generate SCV-guided patterns/plaintexts, allowing us to derive SCV using only a few patterns (ideally as low as two) at gate level. SCV estimates PSCL vulnerability at pre-silicon stage based on the number of plaintexts required to attain a specific SCA success rate. The integration of IFT and pattern generation makes SCRIPT efficient, accurate, and generic to be applied to any hardware design. We validate the efficacy of the SCRIPT framework by demonstrating that it can effectively and accurately determine SCA success rates for different AES designs at pre-silicon stage. SCRIPT is orders of magnitude more efficient than traditional pre-silicon PSCL assessment (SNR-based), with an average evaluation time of 15 minutes; whereas, traditional PSCL assessment at pre-silicon stage would require more than a month. We also analyze the PSCL characteristic of the multiplication unit of RISC processor using SCRIPT to demonstrate SCRIPT’s applicability.

Improving power analysis attack resistance using intrinsic noise in 3D ICs

Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic 3D models, this work demonstrates the impact of noise in PDN on the 3D chip's resilience against correlation power analysis (CPA) attack, which is one of SCA attacks. The characteristic of PDN noise is extracted from our experiments. To expand the natural defense originated from the 3D integration, this work proposes to exploit the PDN noise inherently existing in 3D chips to thwart CPA attacks. Instead of introducing external noise or flattening the power profile, the proposed method utilizes the spatially and temporally varied supply voltages from other 3D planes to blur the power correlation of the crypto unit. Both theoretical analysis and experimental validation prove that the proposed method can effectively enhance the resilience of a crypto unit embedded in the 3D chip against CPA attacks. Simulation results show the proposed method improves the average guessing entropy by 9× over the baseline. Emulation on an FPGA platform demonstrates that the proposed method successfully slows down the key retrieval speed of CPA attack, with significantly less power overhead than representable power equalization techniques. Test vector leakage assessment (TVLA) shows that the proposed method improves the confidence to accept null hypothesis 201× over the baseline.

Flexible Architectures for Cryptographic Algorithms — A Systematic Literature Review

Symmetric and asymmetric cryptographic algorithms are used for a secure transmission of data over an unsecured public channel. In order to use these algorithms in real-time applications, many flexible hardware architectures have been proposed and implemented with multiple design constraints. Therefore, a systematic study is required to analyze various implementation approaches. This paper has focused on the identification and classification of recent research practices pertaining to the flexible hardware implementation of cryptographic algorithms. We have used Systematic Literature Review (SLR) process to identify 51 research articles, published during 2008–2017. The identified researches have been classified according to three design approaches: (1) crypto processor, (2) crypto coprocessor and (3) multicore crypto processor. Consequently, a comparative analysis of various cryptographic algorithms in terms of flexibility, throughput, area, power and implementation technology has been presented. A comprehensive investigation of flexible architectures for implementing cryptographic algorithms facilitates researchers and designers of the domain to select an appropriate design approach for a particular algorithm and/or application according to their needs.

Finding the key

Page 1114, ‘Deep learning (DL)-assisted and combined attack: a novel side-channel attack (SCA) ‘, W. Yu, J. Chen Researcher Weize Yu sitting adjacent to the cryptographic circuit setup testing the novel SCA technique. Flowchart illustrating the setup of the cryptographic system and paths to the secret key. Researchers from the Old Dominion University and the University of Minnesota Twin Cities in the US have exploited a deep learning (DL)-assisted and combined side-channel attack (SCA) method to disclose the secret key of an advanced encryption standard (AES) cryptographic circuit. The results demonstrate that, despite standard SCAs being ineffective even after 1 million plaintexts are enabled, the DL-assisted attack method requires only 32,500 plaintexts be enabled to leak the circuits secret key. Cryptographic circuits are the digital hardware implementations of cryptographic algorithms, used in situations which require private data to be processed confidentially and can be used for encrypting processors and Internet of Things (IoT) devices in our daily lives. Cryptographic algorithms are visible to the public while the secret (original) keys are private. Without obtaining the secret key, no one can unravel the relationship between the plaintexts and the ciphertexts for a cryptographic circuit. As a result, if the secret key of a cryptographic circuit is unknown, an adversary is incapable of leaking confidential information by exploring the correlation between the plaintexts (input data) and corresponding physical leakages such as EM noise. AES is the most popular cryptographic algorithm and, with the assistance of the original key, can encrypt plaintexts and decrypt ciphertexts. This encryption protects the data from external attacks, but AES is vulnerable to non-invasive malicious attacks such as SCAs. The teams Letter introduces a novel DL-assisted side-channel attack to obtain the secret key from an AES circuit and is the first work to test this approach. To secure AES cryptographic circuits, countermeasures like dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS) were proposed. These add random noises into physical leakage profiles to weaken the correlation between the processed data and the physical leakages to thwart standard SCAs. To break through this added layer of security, one of the authors Weize Yu notes that “the random noise inserted into different physical leakage profiles are strongly correlated and deep neural networks (DNN) can be utilised to model the correlation to filter the inserted random noises by combing two different physical leakages.” Ultimately, the protected AES cryptographic circuit can be cracked without much effort by a regular side-channel attack after filtering out the inserted random noises. If the DL technique is used to pre-process the physical leakages to enhance the correlation, the protected cryptographic circuit can be cracked easily with only 32,500 plaintexts being sufficient to leak the secret key. This work sets a representative example of combining side-channel analysis and machine learning to strengthen circuit attacks. Previously, side-channel attacks and machine learning attacks were two separate research areas. However, with the drastic development of machine learning, more algorithms have been demonstrated to be suitable for mining unknown information. By continuing to utilise machine learning to assist side-channel analysis, more secret information can be obtained more efficiently than with conventional techniques. The greatest challenge faced by the group was in designing a suitable DNN architecture that can model the relationship between the power noise and the EM emission noise efficiently and accurately. Since there was no solid theory to guide the teams design of the DNN, its features were determined empirically so as to find an appropriate DNN architecture to maximize the training efficiency. This required testing a variety of hidden layer and neuron numbers and analysing the sensitivities on the training error of the DNN, until the optimised results were acquired. The next step in the team's work, according to Yu, is “to demonstrate our novel attack on a cryptographic circuit which employs other countermeasures such as the masking technique.” This adds a random mask of data to the plaintext file generated by an embedded pseudo-random number generator (PRNG). The team will attempt to use the kernel support vector machine (SVM) algorithm to classify the output of the PRNG and the corresponding prediction accuracy achieves over 90%. This area is likely to achieve greater attention in the future given the recent focus on information security and privacy. More effort will be devoted to designing machine learning-resistant cryptographic circuits and these countermeasures may eventually win out. If both side-channel and machine learning attacks need to be considered, the design of more sophisticated cryptographic circuits is inevitable. As a result, designing cryptographic circuits against non-invasive attacks will be an area of key focus in future research.

Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits

As a type of side-channel attack, fault attacks on the hardware implementation of cryptographic algorithms has been widely studied, and has been successfully applied to a variety of ciphers. So far, many hardware countermeasures against fault attacks have been proposed. However, most of them are tailored to a specific cryptographic algorithm and cannot provide a comprehensive level of protection against all possible faults. In this paper, we present a novel, secure and generic framework based on the robustness of null convention logic pipelines and dual-rail encoded systems, which is resistant to fault attacks at the circuit level by implementing technologies such as rail synchronization, maximum delay matching, error-detecting monitors, and self-feedback mechanisms. Both the theoretical analysis and simulation results show that all faults at the output of computational blocks can be fully detected and corrected. The new framework gives us the ability to detect and correct the faults induced in the register.

Residue Number Systems: A New Paradigm to Datapath Optimization for Low-Power and High-Performance Digital Signal Processing Applications

Residue Number System (RNS) is a non-weighted number system which was proposed by Garner back in 1959 to achieve fast implementation of addition, subtraction and multiplication operations in special-purpose computations. Unfortunately, RNS did not turn out as a popular alternative to two?s complement number system in those days. The rigidity of instruction set architectures of the market-dominant computers and microprocessors then has been the main barrier to sustain the development of RNS-based applications. In recent years, technological advancement in semiconductor technology has revived the interests to reconsider RNS for application-specific computing. There are at least two unique motivations which make RNS computations more attractive and applicable in modern digital signal processing applications. Firstly, the modular and distributive properties of RNS are used to achieve performance improvements especially in the emerging distributed and ubiquitous computing platforms such as cloud, wireless ad hoc networks, and applications which require tolerance against soft error. Secondly, energy efficiency becomes a key driver in the continual densification of complementary metal oxide semiconductor (CMOS) digital integrated circuits. The high degree of computational parallelism in RNS offers new degree of freedom to optimize energy performance, particularly for very long word length arithmetic such as those involved in the hardware implementation of cryptographic algorithms. Our aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications. Different applications of RNS are investigated to demonstrate how this unconventional number system can be leveraged to benefit their implementation.

Comparative analysis of binary-decimal numbers summers on cryptography algorithms realizations

Nowadays the maintenance of information systems without modern information security methods and means is impossible. Among them the primary role for security providing is assigned to cryptography. Most of encryption systems and digital signature systems use integer arithmetic modulo a large positive number. Therefore, to ensure the best performance of information security systems need effective methods of implementation of operations and multiply exponentiation for a large number of precision. High performance, simplicity, security and reliability can be achieved by hardware implementations of cryptographic algorithms using binary-decimal numbers summers. In the paper thecomparative analysis of existing binary-decimal numbers summers is carried out. Different variants of its making are identifying and binary-decimal numbers summers’ speed and complexity of implementation are estimating.

All-or-Nothing Transforms as a countermeasure to differential side-channel analysis

Side-channel attacks on hardware implementations of cryptographic algorithms have recently been the focus of much attention in the research community. Differential power analysis (DPA) has been shown to be particularly effective at retrieving secret information stored within an implementation. The design of DPA-resistant systems that are efficient in terms of speed and area poses a significant challenge. All-or-Nothing Transforms are cryptographic transforms, which are currently employed in numerous applications. We examine All-or-Nothing Encryption systems from the DPA perspective. This paper shows that All-or-Nothing cryptosystems, whilst not preventing side-channel leakage, do fundamentally inhibit DPA attacks. Furthermore, we develop extensions to the All-or-Nothing protocol to strengthen the DPA resistance of the cryptosystem, providing a practical alternative to masking countermeasures for symmetric ciphers.

Bi primitive switching crypto system with key generation mechanism for secure applications

Ensuring security to the information transaction is a major challenge in the communication environment. The choice to guarantee the data transfer using a ciphering algorithm leads to high cost and complexity. The software-based implementations of cryptographic algorithms are easy to design and operate, but the performance penalty paid is high. The hardware implementations of cryptographic algorithms are considered as a task involving intensive computation and evaluation. Microcontroller-based applications for the same prove to be good solutions to the problem for cost-optimized applications. This paper aims to design, implement, and test a microcontroller (AT89c51)-based crypto system using the Tiny Encryption Algorithm and the Extended Tiny Encryption Algorithm as security primitives. The real-time data can be processed with scheduling of the primitives and the context switching between the primitives reduces the probability of being attacked. The keys for the crypto system are generated using internal timers of the microcontroller. The data to be transmitted are encrypted with any one of the security primitives with the generated key and the encrypted data are transmitted both in wired and wireless modes. At the receiving end, the received data are decrypted and the performance of the crypto system is evaluated on the basis of throughput, code size used, and execution time.

Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison

Hardware implementation of cryptographic algorithms is subject to various attacks. It has been previously demonstrated that scan chains introduced for hardware testability open a back door to potential attacks. Here, we propose a scan-protection scheme that provides testing facilities both at production time and over the course of the circuit's life. The underlying principles to scan-in both input vectors and expected responses and to compare expected and actual responses within the circuit. Compared to regular scan tests, this technique has no impact on the quality of the test or the model-based fault diagnosis. It entails negligible area overhead and avoids the use of an authentication test mechanism.

Implementation of correlation power analysis attack on an FPGA DES design

Differential power analysis DPA has become a great threat to cryptographic chips as an important side channel attack. But it is still not easy to put attacks on encryption algorithm with FPGA implementation. In this paper, a data encryption standard DES algorithm is implemented on a FPGA. Then an experimental platform of DPA for FPGA implementation is built with verified feasibility. Experimental results for correlation-based DPA attack on the DES hardware implementation show that our DPA experimental platform is effective in realising the DPA attack on hardware implementation of cryptographic algorithms.

Scan-Based Attack on AES through Round Registers and Its Countermeasure

Scan-based side channel attack on hardware implementations of cryptographic algorithms has shown its great security threat. Unlike existing scan-based attacks, in our work we observed that instead of the secret-related-registers, some non-secret registers also carry the potential of being misused to help a hacker to retrieve secret keys. In this paper, we first present a scan-based side channel attack method on AES by making use of the round counter registers, which are not paid attention to in previous works, to show the potential security threat in designs with scan chains. And then we discussed the issues of secure DFT requirements and proposed a secure scan scheme to preserve all the advantages and simplicities of traditional scan test, while significantly improve the security with ignorable design overhead, for crypto hardware implementations.

Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches

Hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks. Side-channel attacks that are based on multiple measurements of the same operation can be countered by employing masking techniques. Many protection measures depart from an idealized hardware model that is very expensive to meet with real hardware. In particular, the presence of glitches causes many masking techniques to leak information during the computation of nonlinear functions. We discuss a recently introduced masking method which is based on secret sharing and multi-party computation methods. The approach results in implementations that are provably resistant against a wide range of attacks, while making only minimal assumptions on the hardware. We show how to use this method to derive secure implementations of some nonlinear building blocks for cryptographic algorithms. Finally, we provide a provable secure implementation of the block cipher Noekeon and verify the results by means of low-level simulations.

Identity-Based Secure Inter-Domain Routing Protocol

提出了一个采用基于身份密码体制的安全域间路由协议——基于身份域间路由协议(identity-based inter-domain routing,简称id²r).id²r协议包括密钥管理机制、源AS验证机制LAP(the longest assignment path)和AS_PATH真实性验证机制IDAPV(identity-based aggregate path verification).密钥管理机制采用一个分布式层次密钥分发协议(distributed and hierarchical key issuing,简称DHKI),以解决基于身份密码系统固有的密钥托管问题.LAP的基本思想是,任一发出前缀可达路由通告的自治系统都必须提供该前缀的分配路径及证明,只有提供前缀最长有效分配路径的自治系统才是该前缀的合法源AS.IDAPV采用基于身份的聚合签名体制,生成保证AS_PATH路径属性真实性的路由聚合证明.性能评估结果显示,基于2007年12月7日的RouteViews数据,id2r路由器仅额外消耗1.71Mbytes内存,是S-BGP的38%;更新报文长度明显短于S-BGP;当硬件实现密码算法时,收敛时间几乎接近于BGP.;The paper proposes a secure inter-domain routing protocol which adopts identity-based cryptographic system—id²r (identity-based inter-domain routing). id²r consists of a key management mechanism, an origin AS verification mechanism LAP (the longest assignment path), and an AS_PATH authenticity verification mechanism IDAPV (Identity-based Aggregate Path Verification). The key management mechanism adopts a distributed and hierarchical key issuing protocol DHKI (distributed and hierarchical key issuing) to solve the inherent key escrow problem in the identity-based cryptographic system. The basic idea of LAP is that all ASes must provide the assignment path and attestations of their announced prefixes, and for a prefix, the AS which provides the longest valid assignment path is its legitimate origin AS. With identity-based aggregate signature scheme, IDAPV generates a route aggregate attestation to guarantee the authenticity of AS_PATH. Performance evaluation results indicate that based on RouteViews data on December 7, 2007, an id2r router only consumes 1.71Mbytes additional memory, which is 38% of S-BGP router; id2r has shorter UPDATE message than S-BGP; convergence time of id2r with hardware implementation of cryptographic algorithm approximately equals BGP.

The research of DPA attacks against AES implementations

This article examines vulnerabilities to power analysis attacks between software and hardware implementations of cryptographic algorithms. Representative platforms including an Atmel 89S8252 8-bit processor and a 0.25 μm 1.8 v standard cell circuit are proposed to implement the advance encryption standard (AES). A simulation-based experimental environment is built to acquire power data, and single-bit differential power analysis (DPA), and multi-bit DPA and correlation power analysis (CPA) attacks are conducted on two implementations respectively. The experimental results show that the hardware implementation has less data-dependent power leakages to resist power attacks. Furthermore, an improved DPA approach is proposed. It adopts hamming distance of intermediate results as power model and arranges plaintext inputs to differentiate power traces to the maximal probability. Compared with the original power attacks, our improved DPA performs a successful attack on AES hardware implementations with acceptable power measurements and fewer computations.

Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard

Hardware implementations of cryptographic algorithms are vulnerable to fault analysis attacks. Methods based on traditional fault-tolerant architectures are not suited for protection against these attacks. To detect these attacks we propose an architecture based on robust nonlinear systematic error-detecting codes. These nonlinear codes are capable of providing uniform error detecting coverage independently of the error distributions. They make no assumptions about what faults or errors will be injected by an attacker. Architectures based on these robust constructions have fewer undetectable errors than linear codes with the same n,k. We present the general properties and construction methods of these codes as well as their application for the protection of a cryptographic devices implementing the Advanced Encryption Standard.

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC

In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchronous design methodologies. In principle, any functional synchronous block can be encapsulated as a locally synchronous island to form a GALS module. There are, however, several important trade-offs and design decisions involved in doing so. Partitioning a design into several GALS compatible modules is still the most difficult task facing GALS system designers. The controlling state machine of a synchronous functional block may need to be enhanced significantly to accommodate varying latencies involved in data transfers between GALS modules.Such design challenges can not be easily generalized, and in this paper, are presented based on the experiences of designing a GALS system that implements a cryptographic algorithm. The example design uses the GALS methodology to improve resistance against cryptographic power attacks. The problem of side channel attacks against hardware implementations of cryptographic algorithms are briefly presented first, and the GALS architecture featuring several countermeasures against such attacks is introduced. The main part of the paper concentrates on the design decisions involved in the development of this architecture.

An on-chip signal suppression countermeasure to power analysis attacks

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential power analysis (DPA) and simple power analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.