Abstract Quartz flexure accelerometers (QFAs) are widely used in high-precision inertial navigation due to their superior linearity, resolution, and stability. However, their accuracy is fundamentally limited by stochastic noise processes, including velocity random Walk (VRW), acceleration random walk (AccRW) and bias instability (BI). To overcome these limitations, this study proposes a bottleneck residual convolutional neural network (BR CNN) for real-time stochastic error compensation in QFAs. The BR CNN employs a compact encoder–decoder architecture with residual connections, enabling efficient noise suppression while maintaining low computational latency for embedded implementation. The model was trained using public inertial datasets, where synthetic stochastic noise consistent with QFA characteristics was added to evaluate denoising performance. A self-developed prototype integrating the proposed model with real-time signal acquisition and processing hardware was used for experimental validation. Results show that the BR CNN effectively reduces random error parameters, achieving VRW = 9.10 μg/√ Hz, RRW = 0.292 μg/√ Hz, and BI = 1.431 μg, indicating substantial improvement over uncorrected data (VRW = 15.68 μg/√ Hz, RRW = 0.504 μg/√ Hz, BI = 2.467 μg). The model attains an inference latency of 667 μs, verifying its real-time feasibility on microcontrollers. Relative to other CNN-based methods, the BR CNN provides an effective balance between accuracy and inference latency while operating under a conservative filtering strategy that minimizes the risk of signal distortion.

The increasing complexity of intelligent sensing environments, driven by the growth of Internet of Things technologies, has created a strong demand for neuromorphic systems capable of real-time, low-power multisensory perception. Traditional sensory architectures, constrained by single-modal processing and centralized computing, struggle to meet the requirements of diverse and dynamic input conditions. Multisensory neuromorphic devices offer a promising solution by mimicking the distributed, event-driven processing of biological systems. Recent efforts have explored synaptic devices and material systems that respond to various input modalities, including visual, tactile, thermal, and chemical stimuli. However, challenges remain in signal conversion, encoding compatibility, and the fusion of heterogeneous inputs without loss of unisensory information. This review provides a comprehensive overview of the physical mechanisms, device behaviors, and integration strategies that underpin signal processing in neuromorphic hardware. We highlight synaptic mechanisms conducive to cross-modal interaction, analyze representative signal fusion approaches at the device level, and discuss future directions for constructing efficient, scalable, and biologically inspired multisensory neuromorphic systems.

Modern wireless systems are expected to support both communication and sensing, forming the foundation of Integrated Sensing and Communication (ISAC). Although many approaches have been proposed, practical and efficient solutions remain an open challenge. This work addresses this issue by constraining transmitted MIMO radar waveforms to finite-alphabet signals, which are better suited for power amplifiers and signal processing hardware. Under this setting, we investigate methods to jointly enhance communication and sensing performance. First, by exploiting the beampattern-invariance property, we reduce the computational complexity of an existing finite-alphabet waveform generation method and address its limitations to further improve performance. Furthermore, we propose beampattern-preserving schemes that embed communication data into radar waveforms without altering the beampattern, enabling practical ISAC implementation. Specifically, two information-encoding methods and a new precoding technique are introduced, together with an extension to multi-user scenarios based on time and code division. Simulation results demonstrate the trade-off between radar and communication performance.

The next-generation embedded systems are becoming more called upon to accommodate real time and high throughput digital signal processing (DSP) applications to be executed with exceedingly tight limitations on power consumption, latency and silicon area. DSP implementations realized in conventional software running on general-purpose processors and embedded CPUs can generally not meet these very high performance requirements. Hardware accelerators are potentially a solution however, it is of critical importance that the alignment between the algorithmic features and the architecture design decisions is in place. Here, algorithm-architecture co-design has become an important paradigm towards realization of optimized application-specific DSP hardware. The paper will provide a co-design hardware accelerator algorithm architecture approach to the design of high-throughput DSP hardware accelerators optimized in the future generation embedded systems. This design is a joint optimization of signal processing algorithms and hardware design which combines the algorithm-level transformations, parallelism exploitation, pipelined data-path design, and architecture-sensitive memory optimizations into a single design flow. An accelerator architecture based on the scalable and modular design of DSPs is created, which allows the flexible parallelism and data reuse. The proposed architecture is validated by mapping representative DSP Kernels such as finite impulse response (FIR) filtering and fast fourier transform (FFT) on the proposed architecture. The accelerator is designed on an FPGA platform, and experimental assessment is done to appreciate throughput, latency and energy efficiency. The performance and energy efficiency results are shown to be immense in comparison with traditional baseline architectures that are not optimized by co-design. These results affirm that an algorithm-architecture co-design is a successful approach to the implementation of a high-performance and energy-efficient DSP accelerator in next-generation embedded system.

This paper presents a novel method for recovering optimal energy resolution in a NaI(Tl) detector directly from raw photomultiplier tube (PMT) signals, bypassing the need for traditional hardware signal processing modules such as preamplifiers, amplifiers and analog-to-digital converter. The approach utilizes a digital waveform recorder and an Artificial Neural Network (ANN) trained with experimental data derived from Compton scattered photons occuring in a High-Purity Germanium (HPGe) detector. The ANN method, when applied to the raw PMT pulses, yields similar energy resolutions to the conventional method where the PMT signal is processed by a preamplifier and a spectroscopy amplifier. However, it consistently outperforms the raw PMT pulse amplitude and integral methods, demonstrating superior energy resolution, especially given the low amplitude and high background fluctuations inherent in the raw PMT signals. Notably, the ANN achieved a photoelectric peak resolution of 7.4% at 661.7 keV for 137Cs, which is comparable to the optimal resolution obtained with full analog electronics. This technique, demonstrated with a 137Cs radioactive source for primary photons, can allow for the precise determination of energy deposition in NaI(Tl) or similar detectors from photons having energies equal or smaller than the energy of the primary photons which undergoes the Compton scattering. This work highlights the potential of ANNs, when coupled with waveform digitizers, for streamlining detector setups and optimizing performance.

Acoustic sensing is a passive and cost-effective option for unmanned aerial vehicle detection, where both signal processing and microphone hardware jointly determine field performance. In this study, we focus on the hardware front-end as a foundation for improving the reliability of subsequent DSP- or AI-based detection methods. We present a detection-focused comparison of several microphones in outdoor tests, combining calibrated range measurements with spectral analysis of real unmanned aerial vehicle emissions from three platforms. We report hardware metrics only: signal-to-noise ratio, effective detection range, attenuation slope with distance, and the low-frequency background floor. Across wind conditions and source orientations, the RØDE NTG-2 with WS6 windshield delivered the most balanced performance: in strong wind, it extended the detection range over the bare NTG-2 by approximately 31–131% (depending on azimuth), lowered the low-frequency noise floor by about 2–3 decibels, and matched or increased the wideband signal-to-noise ratio by 1.8–4.4 decibels. A parabolic NTG-2 achieved very low background noise levels at low frequencies and strong on-axis reach but proved vulnerable to gust-induced transients. Based on this evidence, we propose an eight-channel, dual-tier array of NTG-2 + WS6 elements that preserves near-hemispherical coverage and phase coherence, establishing a practical hardware baseline for outdoor acoustic unmanned aerial vehicle detection and a reproducible platform for subsequent localization and classification studies.

Abstract Physical reservoir computing (PRC) harnesses the intrinsic nonlinear dynamics of physical systems for efficient temporal data processing, offering significant advantages in energy-efficient hardware implementation. This study explores the potential of oriented semiconducting polymer (SCP) thin films as reservoirs for PRC, focusing on two types of SCP benzo[c]cinnoline-based conjugated polymer diketopyrrolopyrrole benzo[c]cinnoline p(DPP-BZC) and regioregular poly(3-hexyl thiophene) (RR-P3HT). To enable anisotropic charge transport, uniaxially oriented thin films with edge-on molecular orientation were fabricated using the floating film transfer method. The films were electrically evaluated for anisotropic nonlinear responses, phase-shifting capabilities, and high-dimensional mapping in PRC tasks. Performance metrics, including waveform generation accuracy, were systematically investigated under varying device configurations and molecular structures. The study underscores the critical role of different conjugated polymers and their orientations in PRC performance, paving the way for developing next-generation materials for temporal signal processing and low-power intelligent hardware.

Future Department of Defense needs include rapid implementation and testing of signal processing algorithms on forward deployed unmanned autonomous hardware systems. Various signal processing algorithms can be designed to test the feasibility of using MATLAB with the hardware description language (HDL) Coder toolbox for rapid implementation and their use in signal processing hardware for real time aerospace and missile applications. This documents the signal processing algorithms and test inputs, MATLAB implementation, and performance and implementation results for generated very high-speed integrated circuit hardware description language (VHDL) code for specific targets.

Lock-in amplifiers (LIAs) are critical tools in precision measurement, particularly for applications involving weak signals obscured by noise. Advances in signal processing algorithms and hardware synthesis have enabled accurate signal extraction, even in extremely noisy environments, making LIAs indispensable in sensor applications for healthcare, industry, and other services. For instance, the electrical impedance measurement of the human body, organs, tissues, and cells, known as bioelectrical impedance, is commonly used in biomedical and healthcare applications because it is non-invasive and relatively inexpensive. Also, due to its portability and miniaturization capabilities, it has great potential for the development of new point-of-care and portable testing devices. In this document, we highlight existing techniques for high-frequency resolution and precise phase detection in LIA reference signals from field-programmable gate array (FPGA) designs. A comprehensive review is presented under the key requirements and techniques for single- and dual-phase digital LIA architectures, where relevant insights are provided to address the LIAs' digital precision in measurement system configurations. Furthermore, the document highlights a novel method to enhance the spurious-free dynamic range (SFDR), thereby advancing the precision and effectiveness of LIAs in complex measurement environments. Finally, we summarize the diverse applications of impedance measurement, highlighting the wide range of fields that can benefit from the design of high performance in modern measurement technologies.

Silicon photonic signal processors promise a new generation of signal processing hardware with significant advancements in processing bandwidth, low power consumption, and minimal latency. Programmable silicon photonic signal processors, facilitated by tuning elements, can reduce hardware development cycles and costs. However, traditional programmable photonic signal processors based on optical switches face scalability and performance challenges due to control complexity and transmission losses. Here, we propose a scalable parallel signal processor on silicon for versatile applications by interleaving wavelength and temporal optical dimensions. Additionally, it incorporates ultra-low-loss waveguides and low-phase-error optical switch techniques, achieving an overall insertion loss of 10 dB. This design offers low loss, high scalability, and simplified control, enabling advanced functionalities such as accurate microwave reception, narrowband microwave photonic filtering, wide-bandwidth arbitrary waveform generation, and high-speed parallel optical computing without the need for tuning elements calibration. Our programmable parallel signal processor demonstrates advantages in both scale and performance, marking a significant advancement in large-scale, high-performance, multifunctional photonic systems.

In view of the security problems of image encryption algorithms encoded by single DNA or RNA, to increase the randomness of the diffusion process and the uncertainty of the coding rules, we propose a combining dynamic RNA and DNA computing based chaotic image encryption algorithm, which has a more complicated encryption process for improving the security of the encryption algorithm and increases the difficulty of decoding. First, a new three-dimensional hyperchaotic map is proposed, which exhibits a rich set of dynamic behaviors. Second, the sequences generated by the proposed map are passed to NIST test with good randomness and implemented by digital signal processing hardware, which shows the feasibility of the proposed chaotic map for industrial applications. Second, the K-means algorithm is used to split the plaintext into two parts. Third, the chaotic sequence is used to displace and diffuse the two parts of the plaintext, respectively. Then, chaotic sequences were used to encode using dynamic DNA and RNA of these two parts, respectively. Then, the chaotic sequences were used to compute the dynamic DNA and RNA computing of these two parts, respectively. Finally, the cipher text is decoded accordingly. The experimental results show that compared with some related encryption algorithms, our method has higher security.

Despite the success of Deep Learning (DL) serious reliability issues such as non-robustness persist. An interesting aspect is, whether these problems arise due to insufficient tools or fundamental limitations of DL. We study this question from the computability perspective by characterizing the limits the applied hardware imposes. For this, we focus on the class of inverse problems, which, in particular, encompasses any task to reconstruct data from measurements. On digital hardware, a conceptual barrier on the capabilities of DL for solving finite-dimensional inverse problems has in fact already been derived. This paper investigates the general computation framework of Blum-Shub-Smale (BSS) machines, describing the processing and storage of arbitrary real values. Although a corresponding real-world computing device does not exist, research and development towards real number computing hardware, usually referred to by “neuromorphic computing”, has increased in recent years. In this work, we show that the framework of BSS machines does enable the algorithmic solvability of finite dimensional inverse problems. Our results emphasize the influence of the considered computing model in questions of accuracy and reliability.

This article is about the hardware application of one of the basic filters (FIR filter) often used in digital signal processing. First, it introduces the development process of FIR digital filter and the development of FIR digital filter today, and then introduces FIR digital filter. The part combined with hardware, including the research on the hardware implementation technology of the programmable digital filter based on the emictor, the combination with the memistor and the combination with the programmable logic device FPGA is the second most typical research on the combination of digital signal processing technology and hardware in recent years, which respectively describes its main realisation. The combination of FIR digital filter and different hardware methods also has different advantages, but in general, compared with its separate development, the combination of hardware and it has more advantages.

An efficient low-delay polyphase implementation method for active noise control systems

ABSTRACT Designing high-performance integrated circuits that balance area, speed, and power is increasingly challenging. This study optimises hardware implementation of FIR filters using an innovative Amalgam Multiplier, minimising resource use without compromising performance. The key challenge in designing signal processing hardware is the multiplier design, which significantly affects efficiency. This study explores integrated circuit optimisation, addressing the delicate balance between area utilisation, speed, and power consumption. Focusing on hardware implementation of Finite Impulse Response (FIR) filters in signal processing, the article starts with a conventional FIR filter design using a standard array multiplier which consumed 1.790 W, with 8 s real-time completion. Then, Linear Phase FIR (LP-FIR) filter is designed using Braun and Dadda Multiplier. LP-FIR filter with Braun multiplier consumed 1.436 W power and 26 s of completion time whereas LP-FIR with Dadda multiplier consumed 1.363 W power and 23 s of completion time. Finally, the implementation of novel LP-FIR enhanced by Amalgam multiplier consumed 0.302 W power and 10.29 s of completion time, marking a significant advancement in integrated circuit design.

This paper focuses on the challenges faced in hardware design for array signal processing using adaptive beamforming technology. Guided by the requirements of phased array radar systems, the study introduces various beamforming techniques and explores the criteria for adaptive beamforming. Specifically, it covers the classical Sample Matrix Inversion (SMI) adaptive beamforming algorithm. In environments that demand miniaturization and real-time operation, the paper considers the use of subarrays. It delves into the impact of subarrays on the performance of adaptive beamforming and offers computational methods tailored for subarray-level beamforming. Using Xilinx's High-Level Synthesis (HLS), an adaptive beamforming module has been implemented. The correctness was verified through C-based simulation analysis, and the functionality was further validated using the Zynq Ultrascale+ MPSOC platform.

This review publication is an expanded version of the 2015 lecture at the III Moscow Seminar on Mathematical Bioacoustics and Analog Signal Processing in Physiology. Unlike the original 2015 version, this version includes developments by E.D. Adamovich and F.K. Orekhov, as well as a number of graphic materials of historical value. The work proposes new principles or approaches for multifactori/multimodal analysis of various bioacoustic signals based on N-dimension complex spectral analysis of different (bio) physical variables - “bioacoustic fingerprinting” and “bioacoustic footprinting”. Hadware-based technical examples of possible uses of this approache are given for the breef annotation in the text of this lecture.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

Theoretical and non-dimensional investigations have been performed to study the vibration control potential of approaches that are not only based on viscoelastic but also on endochronic elements. The latter are known from the endochronic theory of plasticity and provide the possibility of establishing rate-independent schemes for vibration control. The main question that has to be answered is: Can rate-independent damping be efficiently used to reduce mechanical vibrations? To answer this question, non-dimensional models for dynamical systems are derived and analyzed numerically in the time domain as well as in the frequency domain. The results are used to compare the performance of an optimally tuned endochronic absorber to the performance of an optimally tuned dynamic absorber with viscoelastic damping. Based on a novel closed-form representation for non-linear systems with endochronic elements, it has been possible to prove that the rate-independent control of vibration results in an overall control profit that is close to the control profit obtained by the application of well-established approaches. It has also been found that the new concept is advantageous if anti-resonances have to be considered in broadband vibration control. Based on these novel findings, a practical realization in the context of active vibration control is proposed in which the rate-independent control law is implemented with an appropriate signal processing hardware.

This work aims to achieve intelligent information collection for an automated electrical energy metering system. It utilizes mechatronic electric energy sensor devices to collect energy information from the automated metering system. By improving the spectral scale of the Discrete Fourier Transform (DFT) algorithm, accuracy in fundamental frequency, phase calculation, and amplitude calculation has been enhanced. In a simulated environment, a fusion dataset of infrared and visible images of transmission lines is used for harmonic detection through digital signal processing. Simulation results indicate that the improved DFT algorithm provides a significantly more accurate measurement of the fundamental frequency than the windowed interpolation algorithm. The improved DFT algorithm also outperforms the windowed interpolation algorithm in terms of calculating the phase of the fundamental frequency and each harmonic. Besides, in a digital signal processing hardware environment, it demonstrates higher accuracy in amplitude calculation than the windowed interpolation algorithm. This work achieves information collection for mechatronic electric energy sensors, providing crucial support for the management of automated electrical energy metering systems.