Hardware Design Problems Research Articles

Research on a portable shielding-free ultra-low field magnetic resonance imaging system

The portable light-weight magnetic resonance imaging system can be deployed in special occasions such as Intensive Care Unit (ICU) and ambulances, making it possible to implement bedside monitoring imaging systems, mobile stroke units and magnetic resonance platforms in remote areas. Compared with medium and high field imaging systems, ultra-low-field magnetic resonance imaging equipment utilizes light-weight permanent magnets, which are compact and easy to move. However, the image quality is highly susceptible to external electromagnetic interference without a shielded room and there are still many key technical problems in hardware design to be solved. In this paper, the system hardware design and environmental electromagnetic interference elimination algorithm were studied. Consequently, some research results were obtained and a prototype of portable shielding-free 50 mT magnetic resonance imaging system was built. The light-weight magnet and its uniformity, coil system and noise elimination algorithm and human brain imaging were verified. Finally, high-quality images of the healthy human brain were obtained. The results of this study would provide reference for the development and application of ultra-low-field magnetic resonance imaging technology.

Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL

Due to recent developments, the POSIT number system, winch has been planned as a successor for numbers that are expressed in IEEE floating-point, which are in the focus of advances in arithmetic. Although this format claims to deliver more precise outcomes with the same bit width as ordinary floating point, the duration of the operation fluctuation during posit field identification poses a hardware design problem. The POSIT-based MAC Unit is created using Verilog HDL in this study, and the designed architecture is evaluated for good operation before being implemented on an FPGA using Xilinx Vivado.

전문가 시스템 기반 살수 시험기 챔버를 위한 온도 제어 알고리즘 개발

The PID controller used to regulate the internal temperature of a splash water chamber has only one modeling and control gain set. In addition, it is very difficult to control the temperature within a splash water chamber because of hardware design problems. The heater can be finely controlled by changing the output amount from 0 to 100% through the PWM method. However, the chiller cannot be connected to the output of the PID controller due to hardware compatibility issues. Therefore, the chiller is not finely controllable and only has output levels of 100%, 60% and 40%. Therefore, the control system is designed to control the temperature using the heater only after setting the output level of the chiller. This type of design causes problems such as not reaching the desired temperature, exceeding the settling time, and creating overshoots. In this paper, an expert system is introduced to develop a control algorithm to solve the above-mentioned problems. The expert system to be developed consists of supervisory rules and reasoning rules; based on these rules, the output level of the chiller is switched to achieve the desired performance such as fast settling to the target temperature and elimination of overshoot. To validate the feasibility of the proposed method, several experiments are performed and the results are provided.

Generating circuits with generators

The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away. We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.

Peer review declaration

All papers published in this volume of Conference Series: Materials Science and Engineering have been peer reviewed through processes administered by the Editors. Reviews were conducted by expert referees to the professional and scientific standards expected of a proceedings journal published by IOP Publishing.• Type of peer review: Double-blind• Number of submissions received: 27• Number of submissions sent for review: 17• Number of submissions accepted: 17• Acceptance Rate (Number of Submissions Accepted / Number of Submissions Received X 100): 17/27*100 = 62,96%• Average number of reviews per paper: 2• Total number of reviewers involved: 9 Any additional info on review process: We usually use single-blind type of PR, but also in controversial cases we can use double-blind. This year we sent the paper to the reviewer for 2 weeks to make a review. Then authors made some improvements in their papers. If there was any doubt about acceptance or rejection after this step, we asked the third reviewer to analyze and make a decision. Editor rechecked the revised papers based on the gathered reviews, proofread the texts made in the Word template, edited the manuscript if needed, and checked the similarity before submitting papers in IOP. All papers meet the Technical Criteria, Quality Criteria, Presentation Criteria set by IOP Publishing.Aims and scope• Gyroscopic systems• Applied problems of navigation and motion control• Sensors for navigation and control systems• MEMS sensors, systems, and technologies• Data processing in navigation systems• Integrated and satellite navigation systems• Control theory and control systems• Electronic and electromechanical devices of navigation and control systemsThe aim of the workshop is to provide an overview of new technologies in navigation and motion control. The program includes tutorials on modern navigation and control systems as well as hardware design problems, which will be delivered both by the leading Russian and foreign scientists and young scientists. Contact person for queries: Dmitry O. Taranovskiy, PhD, head of editorial groupConcern CSRI Elektropribor, JSC, editor’s office, St. Petersburg, Russiaeditor@eprib.ru

Design and Implementation of Adaptive Multi-Tap Analog Interference Canceller

Due to the severity of self-interferences, analog interference canceller is an essential part of a full duplex radio system. As the self-interference can potentially be even much stronger than the received signal, it must be meritoriously suppressed before analog-to-digital conversion. This paper is aimed to provide an optimal radio frequency domain multi-tap interference cancellation design. To this end, the following two key problems are addressed: the hardware design problem and the adaptive weight adjusting problem. For optimal hardware design, a trade-off between widening effective delay range and maximizing the minimum cancellation capability is formulated. The principles and guidelines for optimal solution and hardware parameter design are derived. We also formulate adaptive weight adjusting as a multi-dimensional optimization problem, which is proved to be non-convex while adjusting the attenuators and phase shifters independently. By using a coordinate transformation technique, it is then converted into a convex optimization problem, and a convergent iterative algorithm based on the gradient descent method is applied to obtain the global optimum. The hardware implementation and experimental results substantiated the effectiveness of the proposed principles and algorithms.

The Seednoid Robot Platform: Designing a Multipurpose Compact Robot From Continuous Evaluation and Lessons From Competitions

Robots are designed to tackle specific problems or are designed as a multipurpose platform that achieves a concept. In this letter, we approach the hardware design problem from practice and evaluation through numerous competitions including the Darpa Robotics Challenge, the Amazon Picking Challenge, and other competitions that were held in Japan. The paper aims to answer the question what hardware design would we achieve if we continuously refine designs through competitions? We show that competitions lead to a more compact but capable platform design that is durable and has more end effector solutions. We also point out the limitations and benefits of using competitions for designing robot platforms. Our platform began from a human-inspired design for teleoperation and has evolved to mix both human-like and industrial robot structure.

Calculator: A Hardware Design, Math and Software Programming Project Base Learning

This paper presents the implementation by the students of a complex calculator in hardware. This project meets hardware design goals, and also highly motivates them to use competences learned in others subjects. The learning process, associated to System Design, is hard enough because the students have to deal with parallel execution, signal delay, synchronization … Then, to strengthen the knowledge of hardware design a methodology as project based learning (PBL) is proposed. Moreover, it is also used to reinforce cross subjects like math and software programming. This methodology creates a course dynamics that is closer to a professional environment where they will work with software and mathematics to resolve the hardware design problems. The students design from zero the functionality of the calculator. They are who make the decisions about the math operations that it is able to resolve it, and also the operands format or how to introduce a complex equation into the calculator. This will increase the student intrinsic motivation. In addition, since the choices may have consequences on the reliability of the calculator, students are encouraged to program in software the decisions about how implement the selected mathematical algorithm. Although math and hardware design are two tough subjects for students, the perception that they get at the end of the course is quite positive.

Adaptive fuzzy fitness granulation for evolutionary optimization

Nature may have been the original inspiration for evolutionary algorithms, but unlike artificially designed systems, nature has an abundance of resources and time. For man-made systems, computational complexity is a prohibitive factor in sufficiently large and complex problems of today. Much of this computational complexity is due to the fitness function evaluation that may either not exist or be computationally very expensive. But, an exact computation of fitness may not be really necessary as long as a proper rank is approximately preserved in the evolution’s scheme of the survival of the fittest. Here, we aim to exploit this feature of evolution and to investigate the use of fitness granulation via an adaptive fuzzy similarity analysis in order to reduce the number of fitness evaluations. In the proposed algorithm, an individual’s fitness is only computed if it has insufficient similarity to a pool of fuzzy granules whose fitness has already been computed. If an individual is sufficiently similar to a known fuzzy granule, then that granule’s fitness is used instead as a crude estimate. Otherwise, that individual is added to the pool as the core of a new fuzzy granule. Each granule’s radius of influence is adaptive and will grow/shrink depending on the population fitness. The proposed technique is applied to two sets of problems. First is a set of several numerical benchmark problems with various optimization characteristics. Second is a set of four hardware design problems that are evaluated via finite element analysis. Performance of the proposed algorithm is compared with several other competing algorithms, i.e. a fast evolutionary strategy (FES), a GA-NN, as well as a simple GA, in terms of both computational efficiency and accuracy. Statistical analysis reveals that the proposed method significantly decreases the number of fitness function evaluations while finding equally good or better solutions. Moreover, application to the hardware design problems reveals better structural designs more consistently with better computational efficiency.

Differential pixel-based low-power and high-speed implementation of DCT for on-board satellite image processing

Low-power and high-speed discrete cosine transform (DCT) implementation of the images captured by the satellites presents a hardware design problem. The cost of the DCT implementation is dominated by the complexity of the multiplication of input data (image) with the DCT matrix. The techniques for minimising the complexity of multiplication by employing a differential pixel method are presented. In the proposed method 8×8 blocks of input image matrix are considered, the difference between the adjacent pixels is calculated and those differential pixels are used in DCT transformation. Synthesis results on 0.18 µm CMOS technology show that the proposed method gives an average of 13.2% reduction in power consumption and 10.9% improvement in speed over the conventional method. The proposed method can also be combined with the common subexpression elimination method for further reduction.

Evolutionary discovery of algorithms as circuits for quantum computers

This paper demonstrates an application of an evolutionary approach for solving a class of non-trivial, hardware-design problems. Array processing features of the computer language APL simplify the implementation of an evolutionary solution in which simulation is performed by a genetic algorithm on a population of candidate solutions until one or more are satisfactory quantum algorithms. The objective of the simulation model is the automatic discovery of quantum computer algorithms. The algorithms are expressed in a circuit model that specifies the sequences in which quantum operators are to be applied. The automatically configured circuits operate as quantum computers that for the present have their domains of application limited to evaluation of only a few specific functions. The simulations use a small collection of basic and relatively low-level operators to obtain perfect results for five different target functions. These functions were chosen to demonstrate how, on a personal computer, an evolutionary method is able to discover novel designs of computing hardware. The results establish that it is feasible to use genetic algorithms in an evolutionary method to invent correct hardware designs. The progress of simulated evolution is directed by input/output constraints and a fitness function. Alternative configurations of circuit models can obtain algorithms with promise for future quantum computers. Current simulations yield primitive quantum algorithms with a total of twelve or fewer inputs and outputs. The discovered algorithms produce the correct results for evaluating the five selected logical and arithmetic functions.

The allocation problem in hardware design

In the synthesis of hardware structures different design steps are solved by combinatorial optimization techniques. For one optimization step a scheduled flow graph is examined and it is determined, if operations can be assigned to the same professor. The search for a minimum number of processors is equivalent to the search for a minimum coloring of the corresponding incompatibility graph. For the general case and some special cases the graph classes of these incompatibility graphs are determined and for each class an optimal algorithm or an approximate heuristic is given.

From algorithm to market: Real‐world issues in speech development projects

Papers on speech technology have typically addressed issues in one of two disparate areas: (a) hypotheses and observations aboul articulatory, auditory, or acoustic aspects of speech production and perception, and the development of the algorithms that underlie those observations; and (b) marketing and sales issues somewhat or totally unrelated to (a) such as competitive analyses, industry‐specific applications, and applications software or the user interface. There is, however, a complex world of logistics that afffects a speech technology project in the most fundamental way. Nothing describes this more accurately and effectively than a brief history of the DECtalk development project at Digital Equipment Corp. It is a realistic illustration of the evolution from laboratory system to product. In 1981, Dennis Klatt, a senior research scientist at MIT, was searching for an industrial partner to help develop and produce a text‐to‐speech system derived from Klatttalk, a set of algorithms for a speech synthesizer that he had been working on since 1970. After almosl 9 months of searching, he found individuals within Digital Equipment Corp. who were willing to risk the costs of an extensive development project for a technology which, at the time, had no market. This relationship between academia and industry turned out to be so mutually beneficial and enlightening that Klatt was prompted to discuss it publicly from the academician's perspective [D. H. Klatt, Proc. Speech Tech. '87, 293–294 (1987)]. This discussion outlines some of the more important logistical issues from the corporate point of view and a description of these constitutes a typical project history: problems in hardware design and development; dependence upon external engineering and support groups (e.g., manufacturing, technical documentation, etc.) and external vendors; and testing for design verification/maturity and physical robustness. In addition, speech development was proceeding simultaneously in two separate places (Maynard and MII), the need to run in real‐time entailed the perennial decisions on cost versus performance, and debugging cycles required constant compromise.

Comparison of PSK and of multilevel AM data modulators

Coherent quaternary PSK (QPSK) and quaternary AM (QAM) models are compared and conditions for their equivalence are presented. Hardware design problems of both ‘soft’ and ‘hard’ driven integrated circuits and balanced mixers and their applications in systems are described. An approach to PSK modulator design employing only digital circuits is also discussed. The theory is illustrated using measurements taken at a rate of 1[sdot]544 Mbit/s.