Hard Real-time Tasks Research Articles

Energy-Efficient Real-Time Scheduling of Tasks with Abortable Critical Sections

In this paper, an energy-efficient scheduling algorithm, called ceiling-based conditional abortable scheduling (CB-CAS) algorithm, is proposed to schedule periodic hard real-time tasks in a non-ideal DVS processor. Based on the schedulability analysis, CB-CAS calculates a proper processor speed for task execution so that the energy consumption can be reduced without violating the timing constraints of tasks. For saving more energy, we also assume that the critical sections of tasks are abortable, which is a strategy originally proposed to reduce priority inversions. In this paper, CB-CAS introduces a conditional abort rule and a dynamic speed adjustment method to work with the rate monotonic scheduling algorithm and the priority ceiling protocol so that the energy consumption could be reduced further. Whenever two tasks are conflicting for the same resource, CB-CAS will examine the cost of blocking the higher-priority task and the cost of aborting the lower-priority task. CB-CAS will abort the lower-priority task and adjust the processor speed dynamically only if it is more energy efficient. The schedulability analysis and the properties of CB-CAS are given in this paper. The capabilities of CB-CAS were also evaluated by a series of experiments, for which we have some encouraging results.

HRT-PLRU: A New Paging Schemefor Executing Hard Real-Time Programson NAND Flash Memory

For advanced features of next generation vehicles, the real-time programs in automotive embedded systems are dramatically increasing. For such large volume program codes, this paper proposes a novel framework to use high-density and low-cost nonvolatile memory, i.e., NAND flash memory, as a low-cost means of storing and executing hard real-time programs. Regarding this, one challenge is that NAND flash memory allows only 2 KB page-based read operations not per-byte random accesses, which requires RAM as working storage for code executions. This paper proposes two solutions, i.e., partitioned RAM solution and shared RAM solution, that minimize the RAM size required to deterministically guarantee the deadlines of all the hard real-time tasks. The proposed solutions are verified with the actual real-time programs for unmanned autonomous driving. To the best of our knowledge, this is the first work that allows us to use NAND flash memory for hard real-time program executions with the minimal usage of RAM.

Energy-efficient real-time heterogeneous cluster scheduling with node replacement due to failures

Energy preservation in computing systems is an important research topic nowadays. Clusters are usually composed of different hardware with different performance and energy consumption. Performance and efficiency are two metrics introduced in this paper that describe servers' computational power and energy efficiency, respectively. Based on these metrics, we propose three scheduling policies for hard real-time tasks that are executed on a heterogeneous cluster with power-aware dynamic voltage/frequency scaling processors. Simulation experiments show promising results as compared to those of other existing scheduling policies. In order to study the effects of processor failures, the impact of replacing high-performance processors with high-efficiency processors is studied. Furthermore, the load balancing mechanism used in the system is viewed from an energy perspective.

Deadline and activation time assignment for partitioned real-time application on multiprocessor reservations

Providing temporal isolation between critical activities has been an important design criterion in real-time open systems, which can be achieved using resource reservation techniques. As an abstraction of reservation servers, virtual processor is often used to represent a portion of computing power available on a physical platform while hiding the implementation details. In this paper, we present a general framework of partitioning an application comprised of hard real-time tasks with precedence constraints onto multiple virtual processors in consideration of communication latencies between tasks. A novel method is proposed for assigning deadlines and activation times to tasks such that tasks partitioned onto different virtual processors can be analyzed separately using well-established theories for uniprocessor. Extensive simulations have been performed and the results have shown that, compared to existing algorithms, the proposed method achieves better performance in terms of minimizing both total bandwidth and the maximum individual bandwidth.

Scheduling aperiodic requests in the presence of hard real-time tasks with linear timing constraints

This paper considers the problem of scheduling aperiodic requests in the presence of hard real-time tasks with linear timing constraints. This problem may arise when designing control real-time systems. A scheduling algorithm for aperiodic requests that can reduce the average aperiodic response time in comparison with the Slack Stealing algorithm is proposed. The proposed algorithm is based on the fact that it considers initial real-time constraints belonging to a class of linear timing constraints and thereby prolongs the deadlines of hard real-time requests, which frees up additional time for execution of aperiodic requests.

Fault tolerant scheduling of hard real-time tasks on multiprocessor system using a hybrid genetic algorithm

Conventional methods for fault-tolerant scheduling of real-time tasks based on traditional heuristic approach offer poor performance and inefficient system utilization. The primary-backup (PB) approach is often used as a fault-tolerant scheduling technique to guarantee RT tasks to meet their deadline despite the presence of fault. We propose a novel scheduling algorithm using optimization approach based on genetic algorithm (GA) hybridized with knowledge from the real-time task scheduling domain for providing fault-tolerance (FT) in multiprocessor environment. Exhaustive simulation reveals that the new GA based primary-backup fault-tolerant scheduling (PBFTS) approach outperforms other fault-tolerant scheduling schemes in terms of system utilization and efficiency.

Multi-layered scheduling of mixed-criticality cyber-physical systems

In this paper, we deal with the schedule synthesis problem of mixed-criticality cyber-physical systems (MCCPS), which are composed of hard real-time tasks and feedback control tasks. The real-time tasks are associated with deadlines that must always be satisfied whereas feedback control tasks are characterized by their Quality of Control (QoC) which needs to be optimized. A straight-forward approach to the above scheduling problem is to translate the QoC requirements into deadline constraints and then, to apply traditional real-time scheduling techniques such as Deadline Monotonic (DM). In this work, we show that such scheduling leads to overly conservative results and hence is not efficient in the above context. On the other hand, methods from the mixed-criticality systems (MC) literature mainly focus on tasks with different criticality levels and certification issues. However, in MCCPS, the tasks may not be fully characterized by only criticality levels, but they may further be classified according to their criticality types, e.g., deadline-critical real-time tasks and QoC-critical feedback control tasks. On the contrary to traditional deadline-driven scheduling, scheduling MCCPS requires to integrate both, deadline-driven and QoC-driven techniques which gives rise to a challenging scheduling problem. In this paper, we present a multi-layered schedule synthesis scheme for MCCPS that aims to jointly schedule deadline-critical, and QoC-critical tasks at different scheduling layers. Our scheduling framework (i) integrates a number of QoC-oriented metrics to capture the QoC requirements in the schedule synthesis (ii) uses arrival curves from real-time calculus which allow a general characterization of task triggering patterns compared to simple task models such as periodic or sporadic, and (iii) has pseudo-polynomial complexity. Finally, we show the applicability of our scheduling scheme by a number of experiments.

The fork-join real-time task model

Hard real-time task models have evolved from periodic models to more sophisticated graph-based ones like the Digraph Real-Time Task Model (DRT) [1]. These models have in common that tasks are sequential in nature and do not allow for forking structures, modeling job releases that occur in parallel within the same task. To capture these, we present a task model that extends the DRT model with the possibility of forking and joining release paths. We are developing an exact schedulability test for EDF on uniprocessor systems with a pseudo-polynomial bound of its runtime.

A hard real-time capable multi-core SMT processor

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.

Timing effects of DDR memory systems in hard real-time multicore architectures

Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities. Unfortunately, their use in integrated architectures such as IMA or AUTOSAR is limited by the fact that multicores do not guarantee a time composable behavior for the applications: the WCET of a task depends on inter-task interferences introduced by other tasks running simultaneously. This article focuses on the off-chip memory system: the hardware shared resource with the highest impact on the WCET and hence the main impediment for the use of multicores in integrated architectures. We present an analytical model that computes the worst-case delay, also known as Upper Bound Delay (UBD), that a memory request can suffer due to memory interferences generated by other co-running tasks. By considering the UBD in the WCET analysis, the resulting WCET estimation is independent from the other tasks, hence ensuring the time composability property and enabling the use of multicores in integrated architectures. We propose a memory controller for hard real-time multicores compliant with the analytical model that implements extra hardware features to deal with refresh operations and interferences generated by co-running non hard real-time tasks.

Scheduling of hard real-time multi-phase multi-thread (MPMT) periodic tasks

In this paper we study the scheduling of parallel and real-time recurrent tasks on multiprocessor platforms. Firstly, we propose a new parallel task model which allows recurrent tasks to be composed of several phases, each one composed of several threads. Each thread requires a single processor for execution and can be scheduled simultaneously. We then propose an algorithm to transpose popular Fork-Join task model to our MPMT task model. Secondly, we define several kinds of real-time schedulers that can be applied to our parallel task model. We distinguish between two scheduling classes: Hierarchical schedulers and Global Thread schedulers. We present and prove correct an exact schedulability test for each class. Lastly, we also evaluate the performance of our scheduling paradigm in comparison with Gang scheduling by means of simulations. In this work we extend the work of Lupu and Goossens in Scheduling of hard real-time multi-thread periodic tasks (Real-Time and Network Systems, 2011) which considers mono-phase multi-thread task model. We extend their previous results to a Multi-Phase Multi-Thread task model.

Multiprocessor schedulability of arbitrary-deadline sporadic tasks: complexity and antichain algorithm

Baker and Cirinei (Lecture Notes in Computer Science, vol. 4878, Springer, pp. 62---75, 2007) have introduced an exact but naive algorithm, that consists in solving a state reachability problem in a finite automaton, to check whether a set of sporadic hard real-time tasks is schedulable on an identical multiprocessor platform. However, this algorithm suffers from poor performance due to the exponential size of the automaton relative to the size of the task set. In this paper, we build on the work of Baker and Cirinei, and rely on their formalism to characterise the complexity of this problem. We prove that it is PSpace-complete. In order to obtain an algorithm that is applicable in practice to systems of realistic sizes, we successfully apply techniques developed by the formal verification community, specifically antichain techniques (Doyen and Raskin in Lecture Notes in Computer Science, vol. 6015, Springer, pp. 2---22, 2010) to this scheduling problem. For that purpose, we define and prove the correctness of a simulation relation on Baker and Cirinei's automaton. We show that our improved algorithm yields dramatically improved performance for the schedulability test and opens for many further improvements. This work is an extended and revised version of a previous conference paper by the same authors (Lindstrom et al., Proceedings of the 19th International Conference on Real-Time and Network Systems (RTNS 2011), pp. 25---34, 2011).

Synchronization Analysis for Hard Real-Time Multicore Systems

Multicore processors are increasingly used in real-time embedded systems. Better utilization of hard real-time systems requires accurate scheduling and synchronization analysis. In this paper, we characterize the major synchronization penalties arising from partitioned fixed priority scheduling for hard real-time tasks on multicore platform, including transitive remote preemption, multiple remote blocking, and multiple priority inversions. Subsequently, we propose a new response time analysis by improving the approach to bound task blocking time. The key idea of this approach is to classify the total blocking time into (i) direct blocking, including local and remote blocking, and transitive remote preemption; and (ii) multiple local interference which is incurred by multiple priority inversion. Simulation results indicate that the proposed approach produces less pessimistic results in task blocking time, and better schedulability performance.

Analysis and implementation of the multiprocessor bandwidth inheritance protocol

The Multiprocessor Bandwidth Inheritance (M-BWI) protocol is an extension of the Bandwidth Inheritance (BWI) protocol for symmetric multiprocessor systems. Similar to Priority Inheritance, M-BWI lets a task that has locked a resource execute in the resource reservations of the blocked tasks, thus reducing their blocking time. The protocol is particularly suitable for open systems where different kinds of tasks dynamically arrive and leave, because it guarantees temporal isolation among independent subsets of tasks without requiring any information on their temporal parameters. Additionally, if the temporal parameters of the interacting tasks are known, it is possible to compute an upper bound to the interference suffered by a task due to other interacting tasks. Thus, it is possible to provide timing guarantees for a subset of interacting hard real-time tasks. Finally, the M-BWI protocol is neutral to the underlying scheduling policy: it can be implemented in global, clustered and semi-partitioned scheduling. After introducing the M-BWI protocol, in this paper we formally prove its isolation properties, and propose an algorithm to compute an upper bound to the interference suffered by a task. Then, we describe our implementation of the protocol for the LITMUS RT real-time testbed, and measure its overhead. Finally, we compare M-BWI against FMLP and OMLP, two other protocols for resource sharing in multiprocessor systems.

Energy-efficient scheduling for hybrid tasks in control devices for the Internet of Things.

In control devices for the Internet of Things (IoT), energy is one of the critical restriction factors. Dynamic voltage scaling (DVS) has been proved to be an effective method for reducing the energy consumption of processors. This paper proposes an energy-efficient scheduling algorithm for IoT control devices with hard real-time control tasks (HRCTs) and soft real-time tasks (SRTs). The main contribution of this paper includes two parts. First, it builds the Hybrid tasks with multi-subtasks of different function Weight (HoW) task model for IoT control devices. HoW describes the structure of HRCTs and SRTs, and their properties, e.g., deadlines, execution time, preemption properties, and energy-saving goals, etc. Second, it presents the Hybrid Tasks' Dynamic Voltage Scaling (HTDVS) algorithm. HTDVS first sets the slowdown factors of subtasks while meeting the different real-time requirements of HRCTs and SRTs, and then dynamically reclaims, reserves, and reuses the slack time of the subtasks to meet their ideal energy-saving goals. Experimental results show HTDVS can reduce energy consumption about 10%–80% while meeting the real-time requirements of HRCTs, HRCTs help to reduce the deadline miss ratio (DMR) of systems, and HTDVS has comparable performance with the greedy algorithm and is more favorable to keep the subtasks' ideal speeds.

Global EDF-Based On-Line Energy-Aware Real-Time Scheduling Algorithm in Multi-Core Systems

PDF HTML阅读 XML下载 导出引用 引用提醒 多核系统中基于Global EDF 的在线节能实时调度算法 DOI: 10.3724/SP.J.1001.2012.04054 作者: 作者单位: 作者简介: 通讯作者: 中图分类号: 基金项目: 国家教育部博士点基金(20104307110005); 湖南省优秀研究生创新资助(CX2010B026); 国防科学技术大学优秀研究生创新资助(B100601) Global EDF-Based On-Line Energy-Aware Real-Time Scheduling Algorithm in Multi-Core Systems Author: Affiliation: Fund Project: 摘要 | 图/表 | 访问统计 | 参考文献 | 相似文献 | 引证文献 | 资源附件 | 文章评论 摘要:随着多核系统能耗问题日益突出,在满足时间约束条件下降低系统能耗成为多核实时节能调度研究中亟待解决的问题之一.现有研究成果基于事先已知实时任务属性的假设,而实际应用中,只有当任务到达之后才能够获得其属性.为此,针对一般任务模型,不基于任何先验知识,提出一种多核系统中基于Global EDF 在线节能硬实时任务调度算法,通过引入速度调节因子,利用松弛时间,结合动态功耗管理和动态电压/频率调节技术,降低多核系统中任务的执行速度,达到实时约束与能耗节余之间的合理折衷.所提出的算法仅在上下文切换和任务完成时进行动态电压/频率调节,计算复杂度小,易于在实时操作系统中实现.实验结果表明,该算法适用于不同类型的片上动态电压/频率调节技术,节能效果始终优于Global EDF 算法,最多可节能15%~20%,最少可节能5%~10%. Abstract:As the energy consumption of multi-core systems becomes increasingly prominent, meeting the time constraints while reducing as much as possible system energy consumption is still an urgent problem in real-time energy-aware scheduling in multi-core system. Most existing works have assumptions on priori information of real-time tasks, but in real applications the tasks’ property be received only when the tasks arrive. Therefore, based on the general task model with no priori to tasks’ properties, this paper proposes a global EDF-based on-line energy-aware scheduling algorithm for hard real-time tasks in multi-core system. The proposed algorithm can reduce the execution speed of task in multi-core system and reach a reasonable compromise between real-time constraints and energy savings, as it introduces a speed scale factor for utilizing the slack time and combines dynamic power management with dynamic voltage/frequency scaling techniques. The algorithm implements dynamic voltage/frequency scaling only in each context switch time and task completion time, with the smaller computational complexity, and easier to be included in real-time operating system. Experimental results show that the algorithm can be well applied to different kinds of dynamic voltage/frequency scaling on chip, and compared with Global EDF algorithm, it gain more energy savings in all cases, which can improve energy savings about 15% to 20% at most and about 5% to 10% at least. 参考文献 相似文献 引证文献

Paravirtualizing Linux in a real-time hypervisor

This paper describes a new hypervisor built to run Linux in a virtual machine. This hypervisor is built inside Anaxagoros, a real-time microkernel designed to execute safely hard real-time and non real-time tasks. This allows the execution of hard real-time tasks in parallel with Linux virtual machines without interfering with the execution of the real-time tasks. We implemented this hypervisor and compared performances with other virtualization techniques. Our hypervisor does not yet provide high performance but gives correct results and we believe the design is solid enough to guarantee solid performances with its future implementation.

Convex optimization framework for intermediate deadline assignment in soft and hard real-time distributed systems

It is generally challenging to determine end-to-end delays of applications for maximizing the aggregate system utility subject to timing constraints. Many practical approaches suggest the use of intermediate deadline of tasks in order to control and upper-bound their end-to-end delays. This paper proposes a unified framework for different time-sensitive, global optimization problems, and solves them in a distributed manner using Lagrangian duality. The framework uses global viewpoints to assign intermediate deadlines, taking resource contention among tasks into consideration. For soft real-time tasks, the proposed framework effectively addresses the deadline assignment problem while maximizing the aggregate quality of service. For hard real-time tasks, we show that existing heuristic solutions to the deadline assignment problem can be incorporated into the proposed framework, enriching their mathematical interpretation.

Priority inversion with fungible resources

Priority inversion occurs when the execution of a task is unnecessarily delayed by the dispatch of a lower priority task. This anomaly can result in failure if it causes the delay of hard real-time tasks. Priority inheritance protocols have been developed to limit priority inversions during competition over shared resources. Such methods are designed for individually identifiable resource units. Other approaches are indicated when shared resources contain interchangeable resource units. Current practices with resource deadlock, a scheduling anomaly that has many characteristics in common with priority inversion, provide insight into the control of priority inversion with these fungible resources.

PAVENET OS: A Compact Hard Real-Time Operating System for Precise Sampling in Wireless Sensor Networks

The paper shows a compact hard real-time operating system for wireless sensor nodes called PAVENET OS. PAVENET OS provides hybrid multithreading: preemptive multithreading and cooperative multithreading. Both of the multithreading are optimized for two kinds of tasks on wireless sensor networks, and those are real-time tasks and best-effort ones. PAVENET OS can efficiently perform hard real-time tasks that cannot be performed by TinyOS. The paper demonstrates the hybrid multithreading realizes compactness and low overheads, which are comparable to those of TinyOS, through quantitative evaluation. The evaluation results show PAVENET OS performs 100 Hz sensor sampling with 0.01% jitter while performing wireless communication tasks, whereas optimized TinyOS has 0.62% jitter. In addition, PAVENET OS has a small footprint and low overheads (minimum RAM size: 29 bytes, minimum ROM size: 490 bytes, minimum task switch time: 23 cycles).