Half-loop Arrays Research Articles

Formation mechanism of horizontal-half-loop arrays and stacking fault expansion behavior in thick SiC epitaxial layers

The formation mechanism of half-loop arrays (HLAs) that form parallel (horizontal) to the step-flow direction in 120 μm thick 4H-silicon carbide (SiC) epitaxial layers was investigated using ultraviolet photoluminescence (UVPL) imaging and x-ray topography (XRT). The horizontal-HLAs are generated by the multiplication and glide of basal plane dislocation (BPD) loops that are created within the epitaxial layer. The BPD loops were initiated after ∼40–50 μm of growth from a small BPD segment, which glides toward the surface as well as the substrate interface. BPD multiplication occurs and several loops are generated. Some of these loops are terminated by the growth front and create HLAs due to the 4° offcut of the wafer. XRT images show that successive BPD loops interact with previously generated HLA segments. Successive loops also interact with the moving growth front and create new HLAs that are spatially displaced from the previous HLA segments. These appear as a string of horizontal-HLAs in the UVPL images. The expansion of stacking faults (SFs) from these horizontal-HLAs was investigated, and we show that they all lie on the same basal plane. The complex defect structure is created in the epitaxial layer from a single BPD loop but extends over a large (∼5 × 0.5 cm2) region of the SiC wafer during epitaxial growth. The high density of HLAs and BPDs would generate several SFs upon device operation leading to severe device degradation.

Effects of stress on the evolution of Σ-shaped dislocation arrays in a 4H-SiC epitaxial layer

Five Σ-shaped dislocation arrays in 100-mm-diameter, 12-μm-thick 4H-SiC epitaxial wafers were observed using photoluminescence mapping. The structure of the Σ-shaped dislocation arrays was characterized using nondestructive analytical techniques of photoluminescence mapping, microphotoluminescence spectroscopy, and x-ray topography. Each Σ-shaped dislocation array consists of two basal plane dislocations (BPDs) at the interfacial dislocation terminal points and two half-loop arrays. The interfacial dislocation pairs nucleate from BPDs in the substrate. Three independent stresses lead to interfacial dislocations: thermal stress (τT), stress induced by misfit strain (τM), and interaction force (τI). The main cause of interfacial dislocation formation is attributed to the development of τT within the wafer due to temperature nonuniformity. τM and τI also contribute to the formation of interfacial dislocations. Larger stresses increase the BPD glide velocity in the interfacial dislocations, thereby producing longer Σ-shaped dislocation arrays.

Characterization and Reduction of Defects in 4H-SiC Substrate and Homo-Epitaxial Wafer

4H-SiC substrates and homo-epitaxial layers were obtained using the traditional methods of physical vapor transport and chemical vapor deposition. Defect morphology has been studied using both Synchrotron White Beam X-ray Topography and Monochromatic Beam X-ray Topography. Molten KOH etching method was adopted to further investigate the dislocation behavior mechanisms. Deflected dislocations were observed at the periphery regions in both substrate and epitaxial wafers. 3C polytypes and half loop arrays were observed in the 4H-SiC epitaxial wafer. It is also found that the majority of basal plane dislocations are converted to threading edge dislocations in the epitaxial wafer samples. The proportion of BPD to TED conversion depends on the surface step morphology and growth mode in epitaxial growth which in turn depends on the C/Si ratio. By the optimization of etching time prior to epitaxy and C/Si ratio, high-quality epitaxial wafers with extremely low basal plane dislocations densities (＜0.1 cm-2) was obtained.

(Invited) Study of Minority Carrier Lifetime Killer by Synchrotron X-Ray Topography

The lifetime of minority carrier is an important property of a semiconductor material that controls the performance of high voltage/ high power and frequency devices. For instance, in high power device applications, a longer carrier lifetime is desirable to mitigate power loss under forward bias. By comparison, a shorter lifetime is more suitable in high frequency devices as it help reduce power loss during switching cycles. Despite recent studies linking structural defects, growth parameters and material thickness to variation in carrier lifetime in silicon carbide epitaxial layers [1-3], little is known about these lifetime limiting defects/parameters and their influence on carrier recombination because of variability in measurement. Therefore, systematically identifying these factors will shed light into ways to mitigate/annihilate their effects. In this paper, we first report on the influence of structural defects on minority carrier lifetime in n-type 4H-SiC epitaxial layers. The lifetime maps for a 2” quarter wafer (sample 1) and a 4” diameter half wafer (sample 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the synchrotron X-ray topography (SXRT) map of structural defects. The lifetime map of sample 1 revealed a drastic reduction in carrier lifetime along the edges and inside one of its facets (facet 1), which was correlated with the presence of microcracks, BPD loops, overlapping triangular defects, high density of multi-layer Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). Like sample 1, sample 2 showed a reduced carrier lifetime along the edges, which corresponded to regions of high density of overlapping triangular defects, microcracks and BPD loops in the SXRT map. Furthermore, a shorter lifetime was observed in the middle region of sample 2. Synchrotron X-ray topography map correlated this shorter lifetime to networks of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that were generated during epilayers growth. Following further analysis of the SXRT maps, it was observed that the stacking faults in facet 1 of sample 1 were double Shockley stacking faults (DSSFs) that have likely nucleated from scratches present on the substrate surface and LAGBs present in that region, which propagated during epilayer growth. The mechanism of formation of these DSSFs is discussed in light of an electronic model proposed by Kuhr [4] and observed by Pirouz [5]. The mechanism of formation of the IDs and HLAs is also discussed. We discuss the mitigated influence of numerous morphological defects observed on the surface of both epilayer samples. Finally, the implication of these observations on the selection and processing of silicon carbide substrates for epilayer growth is addressed in light of the lifetime maps. 1. J. Hassan and J. P. Bergman, J. Appl. Phys. 105 (12), 2009 2. Louisa Lija, J. Hassan, I. Booker, P. Bergman and E. Janzen, Mat. Sci. Forum 740-742, 2013 3. B. Kallinger, P. Berwian, J. Friedrich, M. Rommel, M. Azizi, C. Hecht and P. Friedrichs, Mat. Sci. Forum 740-742, 2013 [4] P. Pirouz, et al., Phil. Mag. 86, 2006. [5] T. A. Kuhr et al., J. Appl. Phys. 92, 2002.

Investigation of Penetration Depth and Defect Image Contrast Formation in Grazing Incidence X-ray Topography of 4H-SiC Wafers

Synchrotron X-ray Topography has been shown to be a vital tool for the nondestructive characterization of defects in 4H-SiC crystals [1-2]. Techniques utilizing reflection geometry are particularly useful for discerning defects at different depths below the crystal surface. For example, in studying defects in SiC pin diode structures, which typically comprise a buffer layer homoepitaxially grown on a substrate, with the drift layer grown on top of the buffer layer, it is important to be able to discriminate the depth at which particular defect configurations reside. This is particularly important for the characterization of defects resulting from relaxation processes such as interfacial dislocations and half loop arrays [3]. There are generally two approaches adopted depending of the level of perfection of the crystal. In deformed regions (such as around dislocation cores) the penetration depth is simply determined by photoelectric absorption. In perfect regions it is determined by extinction. Extinction contrast predicts particularly shallow penetration depths in these geometries, whereas kinematical theory predicts much deeper penetration depths. However, even under the kinematical diffraction conditions, the penetration depth calculated theoretically by just considering a dislocation as a single line is much smaller than the value measured experimentally. In our study we compared two models involving different diffracting volumes. In one model, the volume is defined by the misorientation larger than the FWHM of the rocking curve in the vicinity of the dislocation core. In another model, the contrast is naturally formed by simulating the photoelectric absorption profile of the diffraction beam according to the local lattice plane tilt by assuming the dislocation image formation is dominant by orientation contrast. We will present a comparison between measured penetration depths in grazing incidence geometry with these two approaches and develop an optimized model to explain our observations. [1] Muller, G.S., et al., Volume production of high quality SiC substrates and epitaxial layers: Defect trends and device applications. Journal of Crystal Growth, 2012. 352(1): p. 39-42. [2] Dudley, M., et al., Characterization of 100 mm diameter 4H-Silicon carbide crystals with extremely low basal plane dislocation density, Material Science Forum,2001. 65: p. 353-356. [3] Wang, H., Dudley, M., et al., Studies of the Origins of Half-Loop Arrays and Interfacial Dislocations Observed in Homoepitaxial Layers of 4H-SiC. Journal of Electronic Materials, 2015. 44(5): p. 1268-1274

(Invited) Study of Minority Carrier Lifetime Killer by Synchrotron X-Ray Topography

The lifetime maps for a 2” n-type 4H-SiC quarter wafer (sample 1) and a 4” diameter half wafer (sample 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the synchrotron X-ray topography (SXRT) map of structural defects. The lifetime map of sample 1 revealed a drastic reduction in carrier lifetime along the edges and inside one of its facets (facet 1), correlated with microcracks, BPD loops, overlapping triangular defects, high density of multi-layer Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). Similarly, sample 2 showed a reduced carrier lifetime along the edges corresponding to regions of high density of overlapping triangular defects, microcracks and BPD loops in the SXRT map. Shorter lifetime observed in the middle region of sample 2 correlated with networks of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that were generated during epilayers growth. Further analysis of the SXRT maps revealed the SFs in facet 1 were double Shockley stacking faults (DSSFs) that have likely nucleated from scratches present on the substrate surface and LAGBs present in that region, which propagated during epilayer growth. We discuss the mitigated influence of numerous morphological defects observed on the surface of both epilayer samples.

Correlation of Lifetime Mapping of 4H-SiC Epilayers with Structural Defects Using Synchrotron X-Ray Topography

Lifetime maps for two 4H-SiC epi-wafers (samples 1 and 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the type and distribution of structural defects mapped by synchrotron X-ray topography (white beam and monochromatic). Sample 1 showed lower lifetime inside one of its higher doped facet regions and along its edges. The low lifetime in the facet region was associated with the presence of a high density of multi-layered Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). These stacking faults are likely double Shockley stacking faults (DSSFs) and probably nucleated from scratches present on the substrate surface and LAGBs present in that region, propagating during epilayer growth. In contrast, sample 2 showed a reduced carrier lifetime in the middle region associated with a network of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that are generated during epilayer growth. Along the edges of both samples, overlapping triangular defects, microcracks and BPD loops lowered lifetime.

Current Status of the Quality of 4H-SiC Substrates and Epilayers for Power Device Applications

ABSTRACTInterfacial dislocations (IDs) and half-loop arrays (HLAs) present in the epilayers of 4H-SiC crystal are known to have a deleterious effect on device performance. Synchrotron X-ray Topography studies carried out on n-type 4H-SiC offcut wafers before and after epitaxial growth show that in many cases BPD segments in the substrate are responsible for creating IDs and HLAs during CVD growth. This paper reviews the behaviors of BPDs in the substrate during the epitaxial growth in different cases: (1) screw-oriented BPD segments intersecting the surface replicate directly through the interface during the epitaxial growth and take part in stress relaxation process by creating IDs and HLAs (Matthews-Blakeslee model [1] ); (2) non-screw oriented BPD half loop intersecting the surface glides towards and replicates through the interface, while the intersection points convert to threading edge dislocations (TEDs) and pin the half loop, leaving straight screw segments in the epilayer and then create IDs and HLAs; (3) edge oriented short BPD segments well below the surface get dragged towards the interface during epitaxial growth, leaving two long screw segments in their wake, some of which replicate through the interface and create IDs and HLAs. The driving force for the BPDs to glide toward the interface is thermal stress and driving force for the relaxation process to occur is the lattice parameter difference at growth temperature which results from the doping concentration difference between the substrate and epilayer.

Assessment of Factors Controlling the X-ray Penetration Depth in Studies of 4H-SiC using Monochromatic and White Beam Synchrotron X-ray Topography in Reflection Geometry

Synchrotron X-ray Topography has been shown to be a vital tool for the nondestructive characterization of defects in 4H-SiC crystals [1-2]. Techniques utilizing reflection geometry are particularly useful for discerning defects at different depths below the crystal surface. For example, in studying defects in SiC pin diode structures, which typically comprise a buffer layer homoepitaxially grown on a substrate, with the drift layer grown on top of the buffer layer, it is important to be able to discriminate the depth at which particular defect configurations reside. This is particularly important for the characterization of defects resulting from relaxation processes such as interfacial dislocations and half loop arrays [3]. Accurate discernment of the depth of a defect requires precise measurement of the effective penetration depth of the X-ray beam in the diffraction geometry in question. This paper provides an assessment of the factors controlling that penetration depth in grazing incidence, reflection and back reflection geometries. There are generally two approaches adopted depending of the level of perfection of the crystal. In deformed regions (such as around dislocation cores) the penetration depth is simply determined by photoelectric absorption. In perfect regions it is determined by extinction. We will present a comparison between measured penetration depths in various diffraction geometries with those calculated using these two approaches and develop an optimized model to explain our observations. [1] Muller, G.S., et al., Volume production of high quality SiC substrates and epitaxial layers: Defect trends and device applications. Journal of Crystal Growth, 2012. 352(1): p. 39-42. [2] Dudley, M., et al., Characterization of 100 mm diameter 4H-Silicon carbide crystals with extremely low basal plane dislocation density, Material Science Forum,2001. 65: p. 353-356. [3] Wang, H., Dudley, M., et al., Studies of the Origins of Half-Loop Arrays and Interfacial Dislocations Observed in Homoepitaxial Layers of 4H-SiC. Journal of Electronic Materials, 2015. 44(5): p. 1268-1274

Studies of the Origins of Half Loop Arrays and Interfacial Dislocations Observed in Homoepitaxial Layers of 4H-SiC

Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. It is shown that the initial motion of the short edge oriented BPD segments that are drawn from the substrate into the epilayer is caused by thermal stress resulting from radial temperature gradients experienced by the wafer whilst in the epi-chamber. This same stress also causes the initial glide of the surface half-loop into the epilayer and through the advancing epilayer surface. These mobile BPD segments provide screw oriented segments that pierce the advancing epilayer surface that initially replicate as the crystal grows. Once critical thickness is reached, according to the Mathews-Blakeslee model, these screw segments glide sideways under the action of the mismatch stress leaving IDs and HLAs in their wake.

X-ray Topography Studies of Relaxation during the Homo-Epitaxy of 4H-SiC

ABSTRACTA review is presented of Synchrotron X-ray Topography and KOH etching studies carried out on n type 4H-SiC offcut substrates before and after homo-epitaxial growth to study defect replication and strain relaxation processes and identify the nucleation sources of both interfacial dislocations (IDs) and half-loop arrays (HLAs) which are known to have a deleterious effect on device performance. We show that these types of defects can nucleate during epilayer growth from: (1) short segments of edge oriented basal plane dislocations (BPDs) in the substrate which are drawn by glide into the epilayer; and (2) segments of half loops of BPD that are attached to the substrate surface prior to growth which also glide into the epilayer. It is shown that the initial motion of the short edge oriented BPD segments that are drawn from the substrate into the epilayer is caused by thermal stress resulting from radial temperature gradients experienced by the wafer whilst in the epi-chamber. This same stress also causes the initial glide of the surface half-loop into the epilayer and through the advancing epilayer surface. These mobile BPD segments provide screw oriented segments that pierce the advancing epilayer surface that initially replicate as the crystal grows. Once critical thickness is reached, according to the Mathews-Blakeslee model [1], these screw segments glide sideways under the action of the mismatch stress leaving IDs and HLAs in their wake. The origin of the mismatch stress is shown to be associated with lattice parameter differences at the growth temperature, arising from the differences in doping concentration between substrate and epilayer.

Studies of the Origins of Half-Loop Arrays and Interfacial Dislocations Observed in Homoepitaxial Layers of 4H-SiC

Synchrotron x-ray topography and KOH etching studies have been carried out on n-type 4H-SiC offcut substrates before and after homoepitaxial growth to study defect replication and strain relaxation processes and identify the nucleation sources of both interfacial dislocations (IDs) and half-loop arrays (HLAs), which are known to have a deleterious effect on device performance. Two cases are reported. In one, they nucleate from short segments of edge-oriented basal plane dislocations (BPDs) in the substrate which are drawn into the epilayer. In the other, they form from segments of half-loops of BPD that are attached to the substrate surface prior to growth which glide into the epilayer. The significance of these findings is: (1) It is demonstrated that it is not necessary for a BPD to intersect the substrate surface in order for it to be replicated into the homoepitaxial layer and take part in nucleation of IDs and HLAs; (2) The conversion of the surface intersections of a substrate BPD half-loop into threading edge dislocations (TEDs) does not prevent it from also becoming involved in nucleation of IDs and HLAs. This means that, while BPD to TED conversion can eliminate most of the BPD transfer into the epilayer, further mitigation may only be possible by continued efforts to reduce the BPD density in substrates by control of temperature-gradient- induced stresses during their physical vapor transport (PVT) growth.

Studies of Relaxation Processes and Basal Plane Dislocations in CVD Grown Homoepitaxial Layers of 4H-SiC

Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. These screw segments subsequently produce interfacial dislocations (IDs) and half-loop arrays (HLAs). We also report on the formation of IDs and HLAs generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches. The HLAs are known to result in Shockley fault expansion within the epilayer which results in forward voltage drop and device failure.

Studies of Relaxation Processes and Basal Plane Dislocations in CVD Grown Homoepitaxial Layers of 4H-SiC

It is well known that basal plane dislocations (BPDs) that are replicated from Physical Vapor Transport (PVT) grown 4H-SiC substrates into Chemical Vapor Deposition (CVD) grown homoepitaxial layers can have a detrimental effect on device performance by inducing the expansion of Shockley faults in the epilayer which cause forward voltage drop. As a result, significant advances have been made in engineering the processes by which BPDs are replicated into the epilayer. For example, the conversion of BPDs into less harmful threading edge dislocations (TEDs) at the substrate/epi interface can be enhanced by direct etching of the substrate surface intersections of the BPDs or by growth interrupts which induce etching. Conversion rates of BPDs into TEDs during epilayer growth have been studied in this paper. Secondly, the behavior of BPDs which are replicated into the epilayer has been studied using Synchrotron White Beam X-ray Topography (SWBXT), Monochromatic Beam X-ray Topography (SMBXT), KOH etching and other techniques on pre- and after- epilayer growth of the same substrate. It is observed that dislocation loops inside substrate can move towards interface and then produce interfacial dislocations (IDs) and half-loop arrays (HLAs) under certain growth conditions during homoepitaxy growth of 4H-SiC on off-cut substrates. The HLAs and IDs are observed to form from pairs of opposite sign screw oriented basal plane dislocations in the substrate which replicate into the epilayer and glide opposite directions once critical thickness has been exceeded. Thirdly, we report on both interfacial dislocations and HLA’s generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches.It is also observed that some dislocations glide past the interface and into the substrate. This will also be discussed.

Measurement of Critical Thickness for the Formation of Interfacial Dislocations and Half Loop Arrays in 4H-SiC Epilayer via X-Ray Topography

Synchrotron X-ray Beam Topography (SWBXT) and KOH etching observations are presented of interfacial dislocations (IDs) and half-loop arrays (HLAs) which can form under certain growth conditions during homoepitaxy of 4H-SiC on off-cut substrates. The HLAs and IDs are observed to form from pairs of opposite sign basal plane dislocations in the substrate which intersect the substrate surface in screw orientation. These dislocations glide in opposite direction in the epilayer once critical thickness has been exceeded. Half-loop arrays are formed at the same time as the screw-type basal plane dislocations (BPDs) side-glide inside the epilayer. From knowledge of the formation mechanism of the HLAs [, if the line of the HLA is extended to intersect the original threading dislocation line direction, then the distance between this intersection point and the ID along the line direction of the original BPD provides a measure of the critical thickness. It is also calculated that the critical thickness in this case is largely determined by the mutual attractive force between the pairs of opposite sign threading BPDs in the substrate. In addition we observed both interfacial dislocations and HLAs generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches.

Unexpected Sources of Basal Plane Dislocations in 4H-SiC Epitaxy

The suppression of degradation inducing basal plane dislocations (BPDs) in the critical drift layer of SiC power devices has occurred mainly by preventing BPDs in the substrate from propagating into the drift layer. As optimized epitaxial growth has produced drift layers free of BPDs over a large fraction of the wafer, other sources of BPDs have become important. Two alternate sources are discussed. The first is epitaxial inclusions, which mainly consist of grossly misoriented 4H-SiC. The local stress field around the inclusion introduces a cluster of BPDs. In low-BPD epitaxy, the outermost BPDs can glide centimeters forming half-loop arrays that have BPD segments along their whole length. The second source of BPDs not normally considered is BPDs that are converted to threading edge dislocation before reaching the drift layer. Experiments suggest that for high current levels and/or over time, device degradation is possible.

Effect of Stacking Faults Originating from Half Loop Arrays on Electrical Behavior of 10 kV 4H-SiC PiN Diodes

The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm2, and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

Correlation of Extended Defects on Carrier Lifetime in Thick SiC Epilayers

The effect of extended defects on carrier lifetime was investigated in 140 um thick 4H-SiC epilayers using whole wafer ultraviolet photoluminescence (UVPL) and microwave photoconductive decay (uPCD) mapping. Half-loop arrays (HLA) seen in the UVPL images showed a corresponding lifetime degradation in the same region, even before expansion of the HLAs to form SFs. Lifetime lowering was also seen for a defect comprising of a small 3C-SiC inclusion with a larger misoriented 4H-SiC region. Additionally, formation of slip planes after high temperature annealing was observed, which consequently shows a lifetime reduction in that region.

A Pictorial Tracking of Basal Plane Dislocations in SiC Epitaxy

The recently developed technique of UVPL imaging has been used to track the path of basal plane dislocations (BPDs) in SiC epitaxial layers. The glide of BPDs during epitaxial growth has been observed and the role of this glide in forming half-loop arrays has been examined. The ability to track the path of BPDs through the epitaxy has made it possible to develop a BPD reduction process for epitaxy grown on 8° offcut wafers, which uses an in situ growth interrupt and has achieved a BPD reduction of > 98%. The images also provide insight into the strong BPD reduction that typically occurs in epitaxy grown on 4° offcut wafers.

Nucleation mechanism of dislocation half-loop arrays in 4H-silicon carbide homoepitaxial layers

A model is presented for the formation mechanism of dislocation half-loop arrays formed during the homoepitaxial growth of 4H-SiC. The reorientation during glide of originally screw oriented threading segments of basal plane dislocation (BPD) renders them susceptible to conversion into sessile threading edge dislocations (TEDs), which subsequently pin the motion of the BPD. Continued glide during further growth enables parts of the mobile BPD to escape through the surface leaving arrays of half loops comprising two TEDs and a short BPD segment with significant edge component. The faulting behavior of the arrays under UV excitation is consistent with this model.