Half-bridge Configuration Research Articles

병렬 운전을 통한 4kW급 인공위성용 아날로그 LLC 공진형 컨버터 개발

A modular analog LLC resonant converter capable of delivering high power for aerospace applications with zero voltage switching turn on of power semiconductors has been proposed. The LLC converter utilizes a half bridge configuration, with top and bottom switches designed by paralleling two low capacity power semiconductors suitable for use in space, thereby increasing the current capacity to enable an output of up to 1.2kW. Each LLC converter module takes in 100V power and outputs 300V in a step up DC/DC converter configuration, designed to operate with regulated voltage and current. This paper describes the operating principles and steady state analysis of the proposed DC/DC converter. To validate its effectiveness, a prototype was constructed and tested. The tests yielded a max efficiency of 95.3% and an output of approximately 4kW, demonstrating the feasibility and output performance of high efficiency, high power supplies through load sharing of multiple modules in parallel.

Advanced gate driving concepts and switching optimization for SiC semiconductors

Silicon carbide (SiC) MOSFETS are increasingly favoured in power electronics for their improved properties compared to silicon-based counterparts, such as IGBTs. Their ability to operate at higher switching frequencies and execute faster switching transients is notable. However, these features also raise significant concerns with electromagnetic interference (EMI). To exploit the full capabilities of SiC-based technology, meticulous design strategies encompassing the power stage, commutation loop, and gate drive are essential. This paper conducts a comprehensive review of existing gate drive techniques aimed at enhancing the performance of SiC devices. Moreover, this study introduces an innovative approach for optimizing switching processes through the use of active gate drivers (AGD). By pre-mapping the gate-source voltage profiles for different conditions (such as load current, temperature, and DC-link voltage), it is possible to achieve a significantly improved switching trajectory. This optimization process can be applied on a cycle-by-cycle basis in practical scenarios. Herein, pre-mapping and optimization have been experimentally confirmed in a half-bridge configuration. Through simulation, it is demonstrated that optimizing the switching trajectory can lead to a balanced compromise between EMI and switching losses, showcasing the potential for significant performance enhancements in SiC device operation.

Fault Ride-Through Method for Interline Power Flow Controller Based on DC Current Limiter

The interline power flow controller (IPFC) based on a modular multilevel converter with a half-bridge configuration can control the active and reactive power flows of multiple alternating current (AC) lines. However, it forms a multiterminal system on the direct current (DC) side, which leads to DC faults. To reduce the protection and clearance requirements on the DC side of IPFCs, this paper proposes a hybrid current limiter topology suitable for generating a DC-side fault ride-through scheme. The current limiter employs a low-loss branch in steady-state conditions; when the fault occurs, a commutation capacitor and controllable power electronic devices are used to transfer the fault current to the current-limiting branch. To clarify the operating principles of the current limiter, the working states of each stage and electrical stress of each device are analyzed. Different components with varying limiter parameters are also discussed, and optimal parameters to achieve the best limitation effect are discussed. PSCAD simulations show that the proposed limiter can limit the overcurrent effectively, and DC-side fault clearance can be achieved easily with this fault ride-through strategy.

A New Hybrid Active Power Filter Topology Enabling Low Voltage Switching Devices and Storage Capacitors.

The increasing importance of mains harmonic content has been responsible for several improvements in Active Power Filter topologies in the last decade. The pure multiple half-bridge configurations are now becoming replaced by new hybrid topologies, aiming to be simultaneously less bulky and expensive. This new technique consists in reducing the voltages at the storage capacitors and consequently at the switching devices. This is achieved by introducing an extra filter between mains and the power electronics converter, tuned at the interest frequencies. This paper presents a new topology for parallel hybrid active filters that can reduce the converter voltage down to 5% of the mains voltage magnitude. A simple, comparative study will be presented, taking in consideration some topologies previously proposed by other authors.

Compact RF transmission unit for nuclear quadrupole resonance spectroscopy

Nuclear quadrupole resonance (NQR) spectroscopy is a non-destructive measurement technique that enables to detect materials of interest very accurately. This technique works by sending high power electromagnetic waves with radio frequency (RF) very specific to the molecular structure to excite the sample and detecting the respond signal with the same frequency. Portable NQR detectors can be potentially developed to detect explosives with non-metallic containers in the fields. However, commercial RF high power amplifiers are large and heavy, so they are not practical for field usage. In this work, we demonstrate a compact NQR transmission part which composed of an active input signal conditioner, a class-D amplifier, and an NQR coil. The active input signal conditioner circuit will convert a single rf pulse with low amplitude (<0.5Vp) to two pulses (with 180° phase difference) and they are subsequently amplified to TTL level. In the class-D amplifier, the pre-amplified pulses are further amplified by a high voltage gate driver IC to 24V amplitude. These high voltage pulses are converted to a single 24V pulse by MOSFETs connected in a half bridge configuration. Finally, the amplified pulse is fed to the NQR coil, i.e., a low impedance LC series resonance circuit. The voltage across the coil at resonance frequency is about 1kVpp.

Two spin-valve GMR thin films on half wheatstone bridge circuit for detecting green-synthesized Fe3O4@Ag nanoparticles-labeled biomolecule

The availability of low-cost, rapid, and easy-to-use instruments for detecting biomolecules is critical in giant magnetoresistance (GMR) based biosensors. This research reports the performance of two spin-valve (SV) GMR thin films on half Wheatstone bridge circuits for detecting biomolecules. The SV thin films with the structure of Ta(2 nm)/Ir20Mn80(10 nm)/Co90Fe10(3 nm)/Cu(2.2 nm)/Co84Fe10B4(10 nm)/Ta(5 nm) used as sensing element was fabricated using RF magnetron sputtering on Si/SiO2 substrate. The Fe3O4 magnetic nanoparticles as a label were synthesized by coprecipitation method based on the green synthesis route using Moringa oleifera (MO) extract. Furthermore, the utilization of Ag nanoparticles to form Fe3O4@Ag was also green-synthesized by the aqua-solution method using MO extract. The nanoparticles exhibited soft ferromagnetic behavior with the saturation magnetization of 55.0 emu/g for Fe3O4 and 43.4 emu/g for Fe3O4@Ag. A small amount of magnetic nanoparticles-ethanol solution was dropped onto each sensing element surface on half Wheatstone bridge. For comparison, one thin film was also investigated as a quarter Wheatstone bridge circuit. Based on this research, two sensors have faster magnetic switching and saturation than one sensor, confirmed by the left-shifting of Hs(sv) from 12.4 Oe down to 10.5 Oe for two sensors of the Fe3O4 sample. BSA is used as a biomarker to observe the performance of biosensors. The sensor on the half-bridge circuit in detecting Fe3O4@Ag/BSA achieved a better sensitivity of 0.51 mV/mg/mL than that of the quarter bridge of 0.46 mV/mg/mL. A small limit-of-detection of 0.5 mg/mL was achieved for Fe3O4@Ag/BSA. Moreover, the excellent reproducibility and stability of the sensor were confirmed by relative signal deviation ranges of 2–13 % for 60 s. Therefore, the half-bridge configuration is reliable for achieving competitive performance with green-synthesized magnetic labels in GMR as biosensors in encouraging more responsive detection.

Reciprocating Arc Silicon Strain Gauges.

Currently, silicon-strain-gauge-based diaphragm pressure sensors use four single-gauge chips for high-output sensitivity. However, the four-single-gauge configuration increases the number of glass frit bonds and the number of aluminum wire bonds, reducing the long-term stability, reliability, and yield of the diaphragm pressure sensor. In this study, a new design of general-purpose silicon strain gauges was developed to improve the sensor output voltage while reducing the number of bonds. The new gauges consist grid patterns with a reciprocating arc of silicon piezoresistors on a thin glass backing. The gauges make handling easier in the bonding process due to the use of thin glass for the gauge backing. The pressure sensors were tested under pressure ranging from 0 to 50 bar at five different temperatures, with a linear output with a typical sensitivity of approximately 16 mV/V/bar and an offset shift of -6 mV to 2 mV. The new approach also opens the possibility to extend arc strain gauges to half-bridge and full-bridge configurations to further reduce the number of glass frit and Al wire bonds in the diaphragm pressure sensor.

Compact SiC Power Module With Integrated Power Delivery and Cooling

As the transition from Si to SiC power devices rapidly grows, new packaging architectures need to be developed to fully benefit from the desired characteristics of SiC technology. The present study offers a highly integrated package (IP) with current carrier electrical feedthroughs that simultaneously combine power delivery and cooling functions. The thermal performance of the proposed solution is compared with the conventional package in a half-bridge configuration of a 50-kW two-level three-phase voltage source inverter (VSI). The specific thermal resistance of a power package is reduced by 13.5% in the proposed approach, showing an increased benefit at higher pumping power and heat flux conditions. Furthermore, design challenges are explored associated with the near-junction cooling as the performance is pushed toward 1 kW/cm2. Unlike the previous studies considering <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{j}$ </tex-math></inline-formula> as the main design constraint, the limiting parameter is found to shift to the maximum coolant temperature. With the design modifications focusing on overcoming the flash point limit of coolant, the specific thermal resistance is further reduced to 0.099 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}\cdot ^{\circ }\text{C}$ </tex-math></inline-formula> /W at 1 kW/cm2 at the expense of a 36.5% increase in the package volume. The findings of the study make a clear case for the need of innovative solutions to extract the highest benefit from integrated cooling at increased power density levels of next-generation inverters.

GaN on Engineered Bulk Silicon Power Integration Platform With Avalanche Capability Enabled by Built-in Si PN Junctions

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit.

Measurement of Circuit Parasitics of SiC MOSFET in a Half-Bridge Configuration

Fast switching transient of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> reduces switching loss. However, it excites device and circuit parasitics resulting in prolonged oscillation, high device stress, spurious turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> , EMI related issues, and higher switching loss. Behavioral or analytical models are used to estimate switching loss <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$(dv/dt)$</tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$(di/dt)$</tex-math></inline-formula> rates, etc., and it requires the value of circuit parasitics as input. Measurement is the only way to accurately estimate some device package-dependent circuit parasitics when the internal package geometry is unknown. Hence, measurement of circuit parasitic is essential for optimal design. This article presents a set of simple experimental measurement techniques to determine circuit parasitic inductance and capacitances relevant for switching transient study of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> in a half-bridge configuration. The accuracy of the proposed technique is verified through simulation and experimental results of the hard turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> and capacitor assisted soft turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> dynamics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> over a range of operating conditions for two 1.2-kV discrete SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> of different current ratings and two different PCB layouts. Furthermore, the proposed technique is also validated with the existing frequency response analysis-based impedance measurement.

A Temperature-Dependent Analytical Model of SiC MOSFET Short-Circuit Behavior Considering Parasitic Parameters

The superior electrical and thermal characteristics of silicon carbide (SiC) MOSFETs bring major challenges to its short-circuit reliability. To fully understand its short-circuit mechanism, estimate its safe operating area, and provide guidance for circuit design, it is crucial to establish a theoretical model to quantize the relationship between circuit parameters and short-circuit behavior of SiC MOSFETs. A temperature-dependent analytical model considering the parasitic inductances, nonlinear junction capacitances, and temperature dependence of the channel current is proposed in this article, which uses only the parameters in the datasheet or provided by manufacturers. The proposed model is established based on the analysis for each short-circuit stage in both single-device configuration and half-bridge configuration, and the quantitatively analytical results of the transient short-circuit waveforms, energy loss, and junction temperature rise can be calculated by solving the model. The accuracy of the analytical model is verified by comparing the analytical results with the experimental results. Furthermore, the effects of varied parameters on the short-circuit behavior are evaluated by the proposed analytical model. And the corresponding circuit design guidance for higher short-circuit reliability is given.

Development of a Didactic Platform for Flexible Power Electronic Converters

Power electronic converters are the subject of several studies and applications. Knowledge about those converters is essential for several technical and undergraduate courses in the field of Electrical Engineering and related areas. The presence of converter modules in laboratories can be beneficial for experimental validations in academic research and educational purposes, for allowing students to have practical contact with different converter topologies and applications. However, the commercially available power converters are generally manufactured for specific applications, with poor versatility and high cost, when applied for academic purposes. For this reason, several laboratories propose the design of versatile converters, mainly for multilevel converter research. Nevertheless, most of these projects present module designs based on half bridge topology due to their low cost. Therefore, this project topology requires more modules to operate as topologies based on a full-bridge converter. Besides, modules based on full-bridge topology can also work in a half-bridge configuration. Thus, this work presents the design of full-bridge modules capable of operating as different types of converters, as well as the project of the dc-link voltage measurement, isolated power supply and bypass circuits. Moreover, this work addresses the heatsink choice, the thermal evaluation for the semiconductor devices and the realization of galvanic isolation between the signal and power circuits.

A Simplified Hard-Switching Loss Model for Fast-Switching Three-Level T-Type SiC Bridge-Legs

Hard-switching losses in three-level T-type (3LTT) bridge-legs cannot be directly estimated from datasheet energy loss curves, which are given for symmetric two-level half-bridge configurations only. The commutations in a 3LTT bridge-leg occur between semiconductors with different blocking voltages and/or current ratings, and involve a third semiconductor device in the switching transition, which contributes additional capacitive losses. This paper, therefore, describes a simplifed approach to estimate a lower bound for the hard-switching losses of 3LTT bridge-legs (note that the approach is applicable to other three-level topolgies as well). In view of the very fast switching speeds of wide-bandgap semiconductors, the model neglects voltage/current overlap losses and considers only the dominating charge-related loss contributions (semiconductor output capacitances, body diode reverse-recovery charge), thus requiring minimal information from datasheets. A direct experimental verification with an 800 V DC-link 3LTT bridge-leg (1200 V and 650 V SiC MOSFETs) operating with output currents up to 25 A confirms the good accuracy of the simplified switching-loss model.

Temperature-Dependent Reverse Recovery Characterization of SiC MOSFETs Body Diode for Switching Loss Estimation in a Half-Bridge

In a hard switched <small>mosfet</small> based converter, turn-<small>on</small> energy losses is predominant in the total switching loss. At higher junction temperature the turn-<small>on</small> energy loss further increases due to the reverse recovery effect of the complementary <small>mosfet</small>s body diode in a half-bridge configuration. Estimation of the switching loss under different operating conditions at an early design stage is essential for optimizing the thermal design. Analytical switching loss models available in literature are generally used for estimating the switching losses due to its accuracy and simplicity. In this article, the inaccuracy in the reported loss models due to non-inclusion of temperature-dependent reverse recovery characteristics of body diode, is investigated. A structured method to determine the temperature-dependent switching loss of a SiC <small>mosfet</small> in a half-bridge is presented. A simple methodology has been proposed to analyze the carrier lifetime&#x0027;s temperature dependencies of a SiC <small>mosfet</small>s body diode. Device parameters from a <inline-formula><tex-math notation="LaTeX">$\text{1.2}\,\text{kV}/36\,\text{A}$</tex-math></inline-formula> SiC <small>mosfet</small>s datasheet are used for developing the loss model and experimental validation of the model.

Medium Voltage Power Switch in Silicon Carbide—A Comparative Study

This paper discusses various solutions of energy conversion in medium voltage using power switches in Silicon Carbide (SiC) technology. In particular, a comparative study is focused on four different variants of an inverter phase leg operating at 1.5 kV DC, which has not been presented in the literature yet. The first one is based on a standard two-level half-bridge built from a 3.3 kV SiC MOSFET power module rated at 450 A. Then, the two-level solution with series-connected devices inside 1.2 kV/450 A power modules is taken into account. Finally, a flying-capacitor phase leg also based on the same 1.2 kV devices is investigated in two different modes: a standard three-level operation and quasi-two-level mode with a significantly reduced capacitor. The presented study is founded on in-depth experiments: all four phase legs were designed, built, and tested in the laboratory. All versions were connected in a half-bridge configuration with an inductive load. Tests were conducted under identical conditions to test the overall performance and switching behavior for various gate resistances. In addition, different aspects are analyzed and compared in this paper, including parasitics, cooling performance, gate drivers and layout considerations, providing selection guidelines for power switches with SiC power devices in medium voltage power electronics applications.

A Concept for Detection of Humidity-Driven Degradation of IGBT Modules

Degradation caused by humidity affects the blocking characteristic of an insulated gate bipolar transistor (IGBT) module, leading to an increased leakage current and/or a reduced voltage blocking capability. The proposed measurement system enables the in situ detection of decreased breakdown voltage and increased leakage current. Thus, it can assess the degradation level of power modules when installed in a converter. This test is intended primarily for wind power converters and can be part of the start-up procedure of the system. The working principle has been validated on predamaged power modules arranged in half-bridge configuration, using a demonstrator implementation of the proposed approach in laboratory experiments. Due to the simplicity of the circuit, this concept is easy to integrate in existing inverter systems at a comparatively low cost.

Analytical Model to Study Turn-OFF Soft Switching Dynamics of SiC MOSFET in a Half-Bridge Configuration

Switching transients of SiC MOSFET are fast compared to its Si counterpart. Fast switching transient reduces switching loss but may induce prolonged oscillations, spurious turn-on, high device stress, and electromagnetic interference (EMI)-related issues, etc. In soft switched converters, use of external drain source capacitance can reduce these adverse effects along with the reduction in switching loss. However, the selection of external drain source capacitance is not straightforward. A large external capacitance reduces switching loss, (dv/dt), (di/dt), and transient over-voltage but may also result in higher dead-time loss and reduced switching frequency. This article presents an analytical model that captures the soft turn-off switching dynamics of SiC MOSFET using parameters obtained from device datasheet along with the values of external circuit parasitics. Unlike linear approximation, a nonlinear channel current model is used along with a comprehensive model of transfer capacitance. The effect of external gate drain capacitance is also considered. This leads to a better estimation of switching transition time, actual loss, (dv/dt), (di/dt), and transient over voltage. Also, a method to select an optimal value of external drain source capacitance is presented. The proposed model is validated through behavioral simulation and experiment for two 1.2-kV discrete SiC MOSFETs.

A 5-kV pulse generator with a 100-kV/µs slew rate based on series-connected 1700-V SiC MOSFETs for electrical insulation tests.

This study demonstrates a high-slew-rate 5-kV pulse generator for electrical insulation tests. Electrical equipment, such as electrical actuators and traction drive motors, are exposed to severe electrical stress because recent switching inverters have high-frequency outputs with high supply voltages using wide-bandgap power devices. For an advanced electrical insulation test, a high-voltage pulse generator is required with a high slew rate; however, such generators suffer from large switching noise, followed by measurement noise, such as ground voltage fluctuations and radiation noise, hindering the detection of partial discharge (PD) phenomena. In this study, we propose a 5-kV pulse generator based on series-connected 1700-V silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). Four 1700-V SiC MOSFETs are connected in series as a 5-kV SiC switching module, constituting a half-bridge configuration for the pulse generator. The obtained switching waveforms exhibit fast rise times of 48 ns under 5 kV and 6.2 ns under 400 V with a low voltage overshoot and ringing owing to superior device characteristics and reduced parasitic inductances. Because of the low switching noise, we detect a clear PD signal with a 1500-V pulse when using the fabricated pulse generator for a PD test of a twisted pair. The proposed pulse generator uses a hard switching configuration such that the pulse generator can vary the pulse width from 150 ns to DC and increase the switching pulse cycle beyond 1 MHz by changing the control signals of the SiC MOSFETs.

Datasheet-Driven Compact Model of Silicon Carbide Power MOSFET Including Third-Quadrant Behavior

This article presents a simulation model of silicon carbide (SiC) power MOSFET that accurately predicts both the static and dynamic third-quadrant behavior without compromising the first-quadrant's accuracy. Unlike existing models, this model features an asymmetric third-quadrant behavior for MOSFET characteristics necessary for the accurate synchronous rectifier simulations. Moreover, it includes the gate-dependent body diode behavior, essential for the accurate prediction of freewheeling high-side device behavior in half-bridge configurations with significant gate voltage oscillation. The model also includes reverse recovery characteristics for the accurate overshoot and power loss prediction. Despite having these added features, the model demonstrates good convergence and efficiency due to the replacement of conditional piecewise equations with continuous ones consisting of weighted variables. The model's convergence capability and efficiency have been verified by simulating a five-level cascaded H-bridge multilevel inverter. The model's superior efficiency and accuracy have been validated by comparing it with an established SiC power MOSFET model. Also, an easy-to-follow parameter extraction procedure is documented that only requires data commonly available in commercial datasheets for broader utility. Considering accuracy, efficiency, and convenience, the model is useful for all power electronics converter applications.

Layout-Based Ultrafast Short-Circuit Protection Technique for Parallel-Connected GaN HEMTs

Gallium-nitrideenhancement-mode high-electron-mobility transistors (GaN HEMTs) help to achieve high-power-density converter circuits due to their superior efficiency, higher switching speed, and small package size. However, increased switching speed results in a sharp increase in short-circuit (SC) current under a shoot-through fault with respect to other type of devices. GaN HEMTs can withstand the SC current only for several hundred nanoseconds. Therefore, fast SC protection solutions are critical for protecting power circuits. In this article, the voltage induced by high slew rate of SC current on the high-frequency power loop inductance resulting from the printed circuit board (PCB) layout is sensed to implement an ultrafast short-circuit protection technique. The proposed technique does not increase circuit parasitics and provides flexibility in layout design that makes it suitable for parallel-connected GaN HEMTs, which requires symmetric layout design for equal current sharing. A multipulse test is conducted under 1.56-MHz switching frequency, 400-V dc- bus voltage, and 40-A load current by using parallel-connected GaN HEMTs in a half-bridge configuration to verify the robustness and reliability of the proposed protection technique. Experimental results show that the proposed protection technique can detect SC fault within 40 ns and fault is completely cleared with a soft turn-off in 250 ns.