Wafer Growth Research Articles

Perovskite intermediate phase FAPbBr3·DMSO assisted in-situ growth of FAPbBr3 polycrystalline wafer for X-ray detection and imaging

Polycrystalline perovskite wafers featured in customizable in dimensions and thickness, represent a frontier in mass production of X-ray detectors. Nevertheless, inherent low crystallinity, elevated defect density, and grain boundaries in polycrystalline wafers typically impair the detection performance. Herein, a novel hot-pressing approach employing the perovskite intermediate phase FAPbBr3·DMSO was demonstrated to improve the quality and X-ray detection performance of polycrystalline perovskite wafers. The in-situ growth of FAPbBr3 wafers were promoted via dimethyl sulfoxide (DMSO) vapor released from the decomposition of FAPbBr3·DMSO phase during the hot-pressing process, resulting in compact morphology, large grain size, superior crystallinity and diminished defect density. The resulted wafers exhibit a high ion activation energy (Ea) of 0.45 eV and a substantial mobility-lifetime product (μτ) of 7.41 × 10−4 cm2 V−1. These advancements equip FAPbBr3 wafer-based detectors with remarkable sensitivity of 3694.6 μC Gyair−1 cm−2, low detection limit (LoD) of 43.8 nGyair s−1, and stable operational performance, comparable to that of single-crystal alternatives. Moreover, the detectors exhibit exceptional X-ray imaging capabilities with a spatial resolution of 4.41 lp mm−1. Thus, the thermally induced decomposition characteristic of perovskite intermediate phase presents a novel avenue for the amelioration of polycrystalline perovskite wafers, heralding a leap forward in X-ray detection performance.

Research on the Influence of Carbon Sources and Buffer Layers on the Homogeneous Epitaxial Growth of 4H-SiC.

In this study, a 4H-SiC homoepitaxial layer was grown on a 150 mm 4° off-axis substrate using a horizontal hot wall chemical vapor deposition reactor. Comparing C3H8 and C2H4 as C sources, the sample grown with C2H4 exhibited a slower growth rate and lower doping concentration, but superior uniformity and surface roughness compared to the C3H8-grown sample. Hence, C2H4 is deemed more suitable for commercial epitaxial wafer growth. Increasing growth pressure led to decreased growth rate, worsened thickness uniformity, reduced doping concentration, deteriorated uniformity, and initially improved and then worsened surface roughness. Optimal growth quality was observed at a lower growth pressure of 40 Torr. Furthermore, the impact of buffer layer growth on epitaxial quality varied significantly based on different C/Si ratios, emphasizing the importance of selecting the appropriate conditions for subsequent device manufacturing.

Promotion of a Mo-based ionic crystal precursor for MoS2 wafer growth

The influence of covalent/ionic molybdenum precursors on the quality of MoS2 is investigated. It is found that the reaction of Na2MoO4 as a typical ionic precursor is highly favourable for defect control and surface homogeneity in wafer growth.

Perovskite materials in X-ray detection and imaging: recent progress, challenges, and future prospects.

Perovskite materials have attracted significant attention as innovative and efficient X-ray detectors owing to their unique properties compared to traditional X-ray detectors. Herein, chronologically, we present an in-depth analysis of X-ray detection technologies employing organic-inorganic hybrids (OIHs), all-inorganic and lead-free perovskite material-based single crystals (SCs), thin/thick films and wafers. Particularly, this review systematically scrutinizes the advancement of the diverse synthesis methods, structural modifications, and device architectures exploited to enhance the radiation sensing performance. In addition, a critical analysis of the crucial factors affecting the performance of the devices is also provided. Our findings revealed that the improvement from single crystallization techniques dominated the film and wafer growth techniques. The probable reason for this is that SC-based devices display a lower trap density, higher resistivity, large carrier mobility and lifetime compared to film- and wafer-based devices. Ultimately, devices with SCs showed outstanding sensitivity and the lowest detectable dose rate (LDDR). These results are superior to some traditional X-ray detectors such as amorphous selenium and CZT. In addition, the limited performance of film-based devices is attributed to the defect formation in the bulk film, surfaces, and grain boundaries. However, wafer-based devices showed the worst performance because of the formation of voids, which impede the movement of charge carriers. We also observed that by performing structural modification, various research groups achieved high-performance devices together with stability. Finally, by fusing the findings from diverse research works, we provide a valuable resource for researchers in the field of X-ray detection, imaging and materials science. Ultimately, this review will serve as a roadmap for directing the difficulties associated with perovskite materials in X-ray detection and imaging, proposing insights into the recent status, challenges, and promising directions for future research.

(Invited) Challenges in Fabricating and Scaling up Silicon Carbide Wafers and Devices

Silicon Carbide is rapidly growing in the power electronics industry. This is fueled to a great degree by the adoption of electric cars and power electronics needed both inside the vehicle and to support the charging infrastructure. This attention from automotive industry comes with a clear spotlight on the cost, quality, and efficiency of SiC power devices. This in turn results in intense pressure and scrutiny to improve yields and reduce defects in every part of the manufacturing chain. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. Several companies are investing billions of dollars in capacity expansions driving exponential growth of wafers and devices.In this review, we will discuss the steps and processes of fabricating a SiC wafer including crystal growth, wafering, epitaxy and device fabrication. The process challenges associated with the steps unique to SiC will be highlighted with a perspective on scaling up volumes and the transition to 200mm wafers. New innovations at some of the steps are enabling higher efficiency and output. The impact of these innovations will be presented. In addition, defects at each step of the process will be reviewed along with how they interact with the following steps [1]. Finally, the effect of various processes and defects on devices and reliability will be presented [2,3].

Controlled Growth of Single-Crystal Graphene Wafers on Twin-Boundary-Free Cu(111) Substrates.

Single-crystal graphene (SCG) wafers are needed to enable mass-electronics and optoelectronics owing to their excellent properties and compatibility with silicon-based technology. Controlled synthesis of high-quality SCG wafers can be done exploiting single-crystal Cu(111) substrates as epitaxial growth substrates recently. However, current Cu(111) films prepared by magnetron sputtering on single-crystal sapphire wafers still suffer from in-plane twin boundaries, which degrade the SCG chemical vapor deposition. Here, it is shown how to eliminate twin boundaries on Cu and achieve 4 in. Cu(111) wafers with ≈95% crystallinity. The introduction of a temperature gradient on Cu films with designed texture during annealing drives abnormal grain growth across the whole Cu wafer. In-plane twin boundaries are eliminated via migration of out-of-plane grain boundaries. SCG wafers grown on the resulting single-crystal Cu(111) substrates exhibit improved crystallinity with >97% aligned graphene domains. As-synthesized SCG wafers exhibit an average carrier mobility up to 7284 cm2 V-1 s-1 at room temperature from 103 devices and a uniform sheet resistance with only 5% deviation in 4 in. region.

1.7-kV vertical GaN p-n diode with triple-zone graded junction termination extension formed by ion-implantation

Edge termination has emerged as an important area in the design and realization of vertical GaN power electronic devices. While the material properties of GaN are promising for high-performance devices, in practice the breakdown voltage can be compromised by inadequate edge termination (ET). While solutions in other materials (e.g. Si, SiC) are well-known, these are challenging to implement in GaN due to inherent difficulties in p-type doping GaN. In this work, we report a etch-free triple-zone graded junction termination extension (JTE) for vertical GaN diodes formed by Nitrogen ion implantation. The triple-zone design offers lower peak fields for effective field control. In addition, the proposed triple-zone JTE is beneficial for increasing the fabrication process window and allowing for more variability in epitaxial wafer growth in terms of p-GaN doping and thickness while maintaining high breakdown voltage. The fabricated GaN p-n diodes with triple-zone JTE obtain a maximum breakdown voltage of 1.73 kV with specific on-resistance Ron of 0.4 mΩcm2. Temperature-dependent reverse characteristics show that the devices have a positive temperature coefficient of the breakdown voltage indicating an avalanche breakdown mechanism. These results suggest that vertical GaN p–n diodes with N-implanted triple-zone JTE are promising for power applications.

Batch Production of Wafer-Scale Monolayer MoS2

Monolayer MoS2 has emerged as a highly promising candidate for next-generation electronics. However, the production of monolayer MoS2 with a high yield and low cost remains a challenge that impedes its practical application. Here, a significant breakthrough in the batch production of wafer-scale monolayer MoS2 via chemical vapor deposition is reported. Notably, a single preparation process enables the growth of multiple wafers simultaneously. The homogeneity and cleanliness of the entire wafer, as well as the consistency of different wafers within a batch, are demonstrated via morphology characterizations and spectroscopic measurements. Field-effect transistors fabricated using the grown MoS2 exhibit excellent electrical performances, confirming the high quality of the films obtained via this novel batch production method. Additionally, we successfully demonstrate the batch production of wafer-scale oxygen-doped MoS2 films via in situ oxygen doping. This work establishes a pathway towards mass preparation of two-dimensional materials and accelerates their development for diverse applications.

Modularized batch production of 12-inch transition metal dichalcogenides by local element supply

Two-dimensional (2D) transition metal dichalcogenides (TMDs) are regarded as pivotal semiconductor candidates for next-generation devices due to their atomic-scale thickness, high carrier mobility and ultrafast charge transfer. In analog to the traditional semiconductor industry, batch production of wafer-scale TMDs is the prerequisite to proceeding with their integrated circuits evolution. However, the production capacity of TMD wafers is typically constrained to a single and small piece per batch (mainly ranging from 2 to 4 inches), due to the stringent conditions required for effective mass transport of multiple precursors during growth. Here we developed a modularized growth strategy for batch production of wafer-scale TMDs, enabling the fabrication of 2-inch wafers (15 pieces per batch) up to a record-large size 12-inch wafers (3 pieces per batch). Each module, comprising a self-sufficient local precursor supply unit for robust individual TMD wafer growth, is vertically stacked with others to form an integrated array and thus a batch growth. Comprehensive characterization techniques, including optical spectroscopy, electron microscopy, and transport measurements unambiguously illustrate the high-crystallinity and the large-area uniformity of as-prepared monolayer films. Furthermore, these modularized units demonstrate versatility by enabling the conversion of as-produced wafer-scale MoS2 into various structures, such as Janus structures of MoSSe, alloy compounds of MoS2(1−x)Se2x, and in-plane heterostructures of MoS2-MoSe2. This methodology showcases high-quality and high-yield wafer output and potentially enables the seamless transition from lab-scale to industrial-scale 2D semiconductor complementary to silicon technology.

Ion-implanted triple-zone graded junction termination extension for vertical GaN p-n diodes

We demonstrate an ion-implanted triple-zone junction termination extension (JTE) for vertical GaN p-n diodes. Due to the spatial distribution of fixed charge in the triple-zone JTE structure, the peak electric fields at the contact metal edge and at the edge of the JTE are significantly reduced compared to conventional approaches. The forward and reverse characteristics of diodes with conventional single-zone JTE and the triple-zone JTE explored here have been studied and compared experimentally. GaN p-n diodes fabricated using the triple-zone JTE obtain an experimentally measured maximum breakdown voltage of 1.27 kV, appreciably higher than the 1.01 kV achieved using the single-zone JTE structure. The triple-zone JTE design also provides a wider window for fabrication processing and epitaxial wafer growth to achieve the high breakdown voltage compared to single-zone designs. The triple-zone JTE is promising for cost-effective fabrication of GaN power electronics.

Rotation Error Detection of Gallium Nitride (GaN) Substrate in MBE Utilizing Ensemble Learning

A rotating substrate is essential for achieving high-quality and uniform growth of gallium nitride (GaN) thin films in molecular beam epitaxy (MBE). By rotating the substrate during growth, the deposited material can be distributed more uniformly across the surface, resulting in a more uniform and defect-free film. However, the substrate may stop rotating during fabrication, and it is a challenge for engineers to detect the rotation of the substrate using information from reflection high-energy electron diffraction (RHEED). The current method for analyzing rotation using RHEED data is manual, time-consuming, and error-prone. Therefore, this research proposes an automated machine learning-based rotation error detection (RED) model to determine wafer rotation and then alert the engineers in case of an anomaly. The proposed approach consists of (1) ensemble learning models such as random forest classifier and extreme gradient boosting (XGBoost) for rotation error detection, (2) prepared novel intensity data from RHEED videos, (3) comparison to select the best ensemble learning model at a small scale, (4) training XGBoost at a large scale, (5) deployment in production using MLflow, (6) development of a REST application programming interface (API) for inference, and (7) integrated KakaoTalk API to generate and send a detailed alert message to engineers so that they can take appropriate actions in time. The experimental results achieved F1 scores for normal and rotational errors of 98.9 and 83.1%, respectively. The proposed method can make a valuable contribution to epitaxial wafer growth by enhancing production efficiency, improving product quality, and reducing costs.

Mechanical Control of Nonlinearity in Doubly Clamped MEMS Beam Resonators Using Preloaded Lattice-Mismatch Strain

We theoretically clarify the mechanism of the strain-tuning effect for control of the mechanical nonlinearity in doubly clamped MEMS beam resonators and experimentally demonstrate that nonlinearity can be effectively suppressed with a preloaded lattice-mismatch strain in the MEMS beam. Mechanical nonlinearity arises from the hardening- and softening-nonlinearity terms in the Duffing motion equation of the MEMS beam. By approaching the buckling condition of the MEMS beam, the substantially increased softening nonlinearity greatly compensates for the hardening nonlinearity, resulting in suppression of the total nonlinearity. Utilizing this knowledge, we fabricate ${\mathrm{In}}_{x}{\mathrm{Ga}}_{1\ensuremath{-}x}\mathrm{As}$ MEMS beams with a preloaded lattice-mismatch strain, which is achieved by adding a small amount (x = \ensuremath{\sim}0.4%) of indium to the $\mathrm{Ga}\mathrm{As}$ MEMS beam during wafer growth. The buckling condition in the experiment is achieved by carefully modulating the length of the ${\mathrm{In}}_{x}{\mathrm{Ga}}_{1\ensuremath{-}x}\mathrm{As}$ MEMS beams. As a result, mechanical nonlinearity is largely modulated from hardening to softening and reaches a quasizero value near the buckling condition, demonstrating the effectiveness of using lattice mismatch for controlling the mechanical nonlinearity of MEMS resonators.

High Power, Room Temperature InP-Based Quantum Cascade Laser Grown on Si

We report on the realization of an InP-based long wavelength quantum cascade laser grown on top of a silicon substrate. This demonstration first required the development of an epitaxial template with a smooth surface, which combines two methods of dislocation filtering. Once wafer growth was complete, a lateral injection buried heterostructure laser geometry was employed for efficient current injection and low loss. The laser emits at a wavelength of ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.8~\mu \text{m}$ </tex-math></inline-formula> and is capable of operation above 373 K, with a high peak power (>4 W) at room temperature. Laser threshold behavior with temperature is characterized by a T0 of 178 K. The far field beam shape is single lobed, showing fundamental transverse mode operation.

Dual Threshold and Memory Switching Induced By Conducting Filament Morphology in Ag/WSe2 Based ECM Cell

In recent years, two-dimensional (2D) materials-based RRAMs have gained high importance because of their thermal and mechanical stability, and better potentiation-depression controllability. 2D materials based conductive bridge random access memory (CBRAM) has been considered as promising approach for neuromorphic and image processing technology [1]. Despite much progress in CMOS technology, the growth and deposition technology of 2D materials for semiconductor integrated circuit are much complex and is generally available at wafer scale [2]. In addition, high growth temperature for high quality of 2D materials complicates direct wafer growth and makes transfer process desirable. At the device level, challenges are linked to controlled and uniform growth of 2D material for high density electronic structure.Recently, discreet 2D based memristor have been used in crossbar structure as synapse for neuromorphic computing. However, the plasma-assisted chemical vapor reaction (PACVR) based memristor for neuromorphic application are rarely demonstrated. Here, we report the co-integration of plasma-assisted chemical vapor reaction (PACVR) with silicon CMOS technology to provide brain-inspired computing device. PACVR offers compatibility with temperature limited 3D integration process and also provides much better thickness control over a large area. Furthermore, it an easy platform for direct and controlled synthesis of TMDs compared to conventional CVD approach. The PACVR grown WSe2 layer (~2 nm) on silicon substrate is realized, which exhibits both threshold and bipolar switching. The threshold and bipolar switching emulate integrate-fire neuron function and is obtained by modulating the compliance current in the device. The dynamics of the switching is closely related to the diffusive dynamics of the active metal (Ag or Cu) which can be controlled by device current. As a result, the WSe2/Si memristor shows synaptic behavior for neuromorphic system with learning accuracy of 96%.

Ultrathin single-crystalline perovskites: Toward large area wafers

The growth of large-area ultrathin single-crystalline wafers of methylammonium lead bromide is investigated on a hole transport layer using a diffusion-facilitated inverse temperature crystallization method. It is shown that, in addition to the hydrophobic confining layers, optimized precursor molar ratio and growth temperature are essential for realizing large-area single-crystalline wafers of device-friendly thickness in the range of 20–30 µm. The necessity of the hydrophobic layer for the realization of large-area wafers using the space confined crystal growth method is explained from consideration of the occurrence of heterogeneous nucleation. Space-charge limited current studies of the device fabricated with the synthesized single-crystal wafer show excellent charge transport mobility of 2.12 cm2/vs and a low trap-state density of 1.34 ⋅ 1011 cm−3.

In situ control of indium incorporation in (AlGa)1−xInxP layers

Metalorganic vapor phase epitaxy growth of red emitting laser structures based on (AlGa)1-xInxP (AlGaInP) compounds requires thorough control of In incorporation during growth of AlGaInP layers which heavily depends on growth parameters and reactor state. We established an in situ method to determine the In incorporation in AlGaInP layers during growth without any prior calibration based on ex situ characterization. This requires to model the lattice constants of substrate and growing layer and feed it with the in situ measured wafer temperature, growth rate and wafer curvature. The model makes use of the Stoney equation and Vegard’s law to calculate the In content of AlGaInP layers grown on GaAs substrates. Correlation of in situ results to ex situ results from X-ray diffraction confirmed the accuracy of our method. Our in situ method allowed us to study the influence of dopants on growth of AlGaInP layers. At high temperature Si doping from Si2H6 showed no influence on the In incorporation during growth, however, Zn doping from DMZn showed strong impact on In incorporation and growth rate. In particular, increasing the DMZn/III ratio during AlGaInP growth linearly decreases In incorporation and growth rate. Accordingly, the presence of Zn on the growth surface hinders In incorporation and causes enhanced In re-evaporation from the surface at high temperatures.

Layer-by-layer epitaxy of multi-layer MoS2 wafers.

The 2D semiconductor of MoS2 has great potential for advanced electronics technologies beyond silicon. So far, high-quality monolayer MoS2 wafers have been available and various demonstrations from individual transistors to integrated circuits have also been shown. In addition to the monolayer, multilayers have narrower band gaps but improved carrier mobilities and current capacities over the monolayer. However, achieving high-quality multi-layer MoS2 wafers remains a challenge. Here we report the growth of high-quality multi-layer MoS2 4-inch wafers via the layer-by-layer epitaxy process. The epitaxy leads to well-defined stacking orders between adjacent epitaxial layers and offers a delicate control of layer numbers up to six. Systematic evaluations on the atomic structures and electronic properties were carried out for achieved wafers with different layer numbers. Significant improvements in device performances were found in thicker-layer field-effect transistors (FETs), as expected. For example, the average field-effect mobility (μFE) at room temperature (RT) can increase from ∼80 cm2·V–1·s–1 for monolayers to ∼110/145 cm2·V–1·s–1 for bilayer/trilayer devices. The highest RT μFE of 234.7 cm2·V–1·s–1 and record-high on-current densities of 1.70 mA·μm–1 at Vds = 2 V were also achieved in trilayer MoS2 FETs with a high on/off ratio of >107. Our work hence moves a step closer to practical applications of 2D MoS2 in electronics.

Demonstration of Picosecond 4H-SiC Diode Avalanche Shaper With Voltage Rise Rate of 11.14 kV/ns and Peak Power Density of 62 MW/cm$^2$

In this letter, for the first time, a high-performance picosecond 4H-SiC diode avalanche shaper (DAS) with a novel <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${p^+/p^-/n^+}$</tex-math></inline-formula> multilayer epitaxial structure is experimentally demonstrated and characterized. For fabrication of our 4H-SiC DAS, the multilayer epitaxial stacks have been designed in detail and grown using continuous multilayer epitaxial wafer growth. To excite the delayed avalanche breakdown (DAB) effect, the electric field profile in multilayer epitaxial stacks has been numerically simulated in detail to suppress the surface electric field crowding and premature breakdown during the overvoltage pulse applied. A 2.5-kV, 1-ns pulsed power generator is adopted to drive our fabricated SiC DAS, the output on a 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> load is 1860 V, 100 ps, lead a voltage rise rate of 11.14 kV/ns, and a peak power density of 62 MW/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> . Furthermore, the fabricated SiC DAS operates stably in multipulse mode at 1 MHz. To the best of our knowledge, this is the first experimental result reported for picosecond DAS based on the 4H-SiC. This article is significant for developing 4H-SiC-based ultrafast closing switches.

Polycrystalline Silicon Membranes for Solar Cells Fabricated Using Water-soluble Sacrificial Layers

During the fabrication of crystalline silicon solar cells, kerf-loss caused by the wire-sawing of silicon ingots to produce thin wafers inevitably limits the reduction of electricity production cost. To avoid the kerf-loss, direct growth of crystalline silicon wafers of 50-150 μm with a porous separation layer that can be mechanically broken during the exfoliation process, has been widely investigated. However, several issues including flattening of the surface after the exfoliation remain unsolved. In this work an alternative method that utilizes a water-soluble Sr3Al2O6 (SAO) sacrificial layer inserted between the mother substrate and the grown crystalline silicon layers is introduced. Polycrystalline silicon layers were grown on SAO/Si by plasma-enhanced CVD process and silicon membranes could be successfully obtained after the dissolution of SAO in the water. Same process could be applied to obtain flexible amorphous silicon membranes. Further research is being conducted to increase the size of the exfoliated wafer, which expects to reduce the production cost of crystalline silicon solar cells effectively.

Study on Improving the Precise Machinability of Single Crystal SiC by an Ultrasonic-Assisted Hybrid Process.

Silicon carbide (SiC) devices have become one of the key research directions in the field of power electronics. However, due to the limitation of the SiC wafer growth process and processing capacity, SiC devices, such as SiC MOSFET (Metal-oxide-semiconductor Field-effect Transistor), are facing the problems of high cost and unsatisfied performance. To improve the precise machinability of single-crystal SiC wafer, this paper proposed a new hybrid process. Firstly, we developed an ultrasonic vibration-assisted device, by which ultrasonic-assisted lapping and ultrasonic-assisted CMP (chemical mechanical polishing) for SiC wafer were fulfilled. Secondly, a novel three-step ultrasonic-assisted precise machining route was proposed. In the first step, ultrasonic lapping using a cast iron disc was conducted, which quickly removed large surface damages with a high MRR (material removal rate) of 10.93 μm/min. In the second step, ultrasonic lapping using a copper disc was conducted, which reduced the residual surface defects with a high MRR of 6.11 μm/min. In the third step, ultrasonic CMP using a polyurethane pad was conducted, which achieved a smooth and less damaged surface with an MRR of 1.44 μm/h. These results suggest that the ultrasonic-assisted hybrid process can improve the precise machinability of SiC, which will hopefully achieve high-efficiency and ultra-precision machining.