Graphics Subsystem Research Articles

Обеспечение функционирования графических GLX приложений на промышленном оборудовании с использованием API EGL

This paper discusses the operation of engineering software on systems with graphics adapter drivers that provide limited to no support for certain graphics subsystems of Linux OS. The paper demonstrates that software with GLX API-based visualization subsystem needs modification to be ported to the embedded systems using graphics accelerators with drivers that support only the EGL API. The purpose of the study is to develop approaches for enabling the operation of software on industrial equipment and utilizing the GLX API via the EGL API of the Linux-based graphics subsystem. The paper discussed the method for translating GLX API calls to the EGL API and its applicability. A new algorithm has been developed for organizing interaction between user applications and the Linux OS graphics subsystem, which allows running applications with the GLX API in the absence of DRI support by the graphics accelerator driver. The correctness of the algorithm’s operation has been tested and compared with the results of the tests of open drivers with DRI2 support. The findings will make it possible to reduce the resources needed to support individual graphics driver subsystems and make a smooth transition to using the EGL API in the embedded systems.

Identification of Subscriber Terminals of Infocommunication Networks based on the Model of Forming Images in Modern Computer Systems

One of the important tasks of such theories as theories of pattern recognition and the theory of information security, is the task of identifying terminals of information and telecommunication networks.
 The relevance of the topic is due to the need to study methods for identifying computer network terminals and build information security systems based on the knowledge gained.
 The main parameters that allow uniquely identifying subscriber terminals in the network are address-switching information, as well as a number of parameters characterizing the software and hardware of the computer system. Based on the obtained parameters, digital fingerprints of subscriber terminals are generated.
 The using anonymous networks by users of subscriber terminals and blocking of the methods of generating and collecting digital fingerprint parameters, does not allow to achieve the required degree of identification reliability in some cases.
 Based on the peculiarities of digital image formation in modern computer systems, many transformation parameters make impact on the output graphic primitive, thereby forming a digital fingerprint of the subscriber terminal, which depends on the placement of samples in a pixel, the algorithms used to calculate the degree of pixels influence, and also the procedures used of smoothing images in the graphics subsystem.
 In this paper an original model of image formation by means of a subscriber terminal web browser that allows to increase the degree of reliability of identification under conditions of anonymization of users of information and telecommunication networks is propesed.
 Features of the digital images formation in the graphic subsystems of modern computer systems are substantiated. These features allow identification under a priori uncertainty regarding the modes and parameters of information transfer.

Development of a software platform for the design of district heating systems

The paper presents a new methodological approach to developing a universal platform for the design of district heating systems. The reasons for the development of the platform are considered and a scientific statement of the problem is given. The main methodological results obtained during the development of the platform are presented. The description of the scientific and practical significance of the results is given. A new methodological approach was developed using modern information technologies. The methodological approach is based on the paradigm of Model-Driven Engineering. The essence of this paradigm is that the software is generated on the base of formal description provided by the models. The proposed approach allows one to successfully solve the problem of separation of methods for solving applied problems and models of elements of a district heating system. The paper describes the developed architecture of the software platform. A description of the architectural subsystems of the platform is presented: the computing subsystem and the graphics subsystem.

The optimization of Transparent‐Desktop service mechanism based on SPICE

SummaryDesktop virtualization, which is to make the desktop virtual so that users can access any application through the network with any devices at any time and any place, is being widely used now as an emerging trend. However, it is important to further improve this approach while maintaining good user experience. Though the simple protocol for independent computing environments as a virtual desktop solution can achieve a user experience similar to an interaction with a local machine, there are still many deficiencies in it. For instance, it cannot apply to environment of high controllability of user, and the quality of graphic interactive experience is to be improved. In this paper, to meet QoE requirements of user, we build a feasible file transfer and sharing mechanism and propose a graphics subsystem optimization strategy based on simple protocol for independent computing environments (SPICE), namely Transparent Desktop. We also verify that the Transparent Desktop can provide users with ubiquitous desktop services of higher efficiency, stronger user‐controllability and better QoE through the experimental. Copyright © 2016 John Wiley & Sons, Ltd.

Прототип интегрированной программной платформы для сопровождения вычислительного эксперимента в комплексных задачах математического моделирования

The software platform for mathematical modeling support Temetos is decribed. The Temetos platform is the integrated graphical tool environment for the study of mathematical models of physical processes and technical systems. Temetos platform provides opportunities for preparation of geometric and physical models of the object; external or built-in problem-oriented modules configuration, including numerical method parameters configuration; computational module launch and executing control; calculations results visualization and analysis. The platform consists of three subsystems: the mathematical subsystem, including command-line utilities for the computational domain discretization and triangulation and software modules for the numerical solution of the mathematical model differntial equation systems; instrumental graphics subsystem, including tools for the 3D geometric design of the investigated object model; subject libraries subsystem containing structured knowledgebase for the simulated structures, constructions and physical processes (elements of the libraries are: 3D object models, meshes, material physical models and others.). The subject libraries subsystem is the base of platform information structure. It contains of free format XML files decribing knowledgebase elements. Hierarchical library architecture and universal data interfaces leads the platform to grow and to implement the new subject areas and mathematical models in easy way. As examples of platform implementation the simulation of plasma flow instability in astrophysical conditions and model of brittle material failure under heat load are considered.

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.

Exploring the Millennium Run - Scalable Rendering of Large-Scale Cosmological Datasets

In this paper we investigate scalability limitations in the visualization of large-scale particle-based cosmological simulations, and we present methods to reduce these limitations on current PC architectures. To minimize the amount of data to be streamed from disk to the graphics subsystem, we propose a visually continuous level-of-detail (LOD) particle representation based on a hierarchical quantization scheme for particle coordinates and rules for generating coarse particle distributions. Given the maximal world space error per level, our LOD selection technique guarantees a sub-pixel screen space error during rendering. A brick-based pagetree allows to further reduce the number of disk seek operations to be performed. Additional particle quantities like density, velocity dispersion, and radius are compressed at no visible loss using vector quantization of logarithmically encoded floating point values. By fine-grain view-frustum culling and presence acceleration in a geometry shader the required geometry throughput on the GPU can be significantly reduced. We validate the quality and scalability of our method by presenting visualizations of a particle-based cosmological dark-matter simulation exceeding 10 billion elements.

Evaluating the performance of single and multiple core processors with PCMARK®05 and benchmark analysis

PCMark®05 [4, 8] is a highly popular synthetic benchmark for evaluating the performance of personal computers (PCs) with millions of downloads via the Internet. Based on open source and commercial applications, it measures the execution time of highly representative code extracts of these applications and reports scores reflecting the overall system performance, the CPU performance, the memory subsystem performance, the graphics subsystem performance, and the disk subsystem performance. In this article, we focus on the PCMark®05 CPU test suite which is composed of 8 tests to measure the performance and scalability of various Intel single- and dual-core processors. Six of these tests run a single application each. One test runs 2 multitasked applications in parallel and another test runs 4 multitasked applications simultaneously. We present the results of executing this benchmark's CPU test suite on high end Intel-based PC platforms with top of the line single processor and dual core processors, present the results of our profiling and hotspot analysis, shed some light on this test suite's prominent microarchitecture events and its active threads' distributions, and characterize this suite's workload. These results help in understanding the performance characteristics of this popular benchmark and in guiding future processor design enhancements.

An Improved Adjacency Data Structure for Fast Triangle Stripping

To speed up the rendering of polygonal meshes, triangle strips are commonly used to reduce the number of vertices sent to the graphics subsystem by exploiting the fact that adjacent triangles share an edge. In this paper, we present an improved adjacency data structure for fast triangle stripping algorithms. There are three major contributions: first, the data structure can be created quickly and robustly from any indexed face set; second, its cache-friendly layout is specifically designed to efficiently answer common stripping queries, such as neighbor finding and least-degree triangle finding, in constant time; and third, the stripping algorithm operates in-place, since strips are created by simply relinking pointers. An implementation of a stripping algorithm shows a significant speed-up compared to other implementations. Our implementation is publicly available as part of OpenSG.

A virtual memory architecture for real-time ray tracing hardware

Real-time ray tracing offers a number of interesting benefits over current rasterization techniques. However, a major drawback has been that ray tracing requires access to the entire scene data base. This is particularly problematic for hardware implementations that only have a limited amount of dedicated on-board memory. In this paper we propose a virtual memory architecture for ray tracing that efficiently renders scenes many times larger than the available on-board memory. Instead of wasting large dedicated memory on a graphics card, scene data is stored in main memory, and on-board memory is used only as a cache. We show that typical scenes from computer games only require less than 8 MB of cache memory while 64 MB are sufficient even for scenes with GBs of geometry and textures. The caching approach also minimizes the bandwidth between the graphics subsystem and the host such that even a standard PCI connection is sufficient.

Cross-platform Qt-based implementation of low level GUI layer of ROOT

Abstract This paper describes an implementation of the low-level layer of the ROOT package based on the multi-platform graphics library. This approach allows ROOT developers and ROOT users to work with a code that has no X11/WIN32 graphics subsystem dependencies and at the same time opens an unrestricted access to a rich set of ready-to-use commercial and free GUI Qt-based widgets, which are available for download from http://root.bnl.gov Web site.

Visibility Driven Rasterization

We present a new visibility driven rasterization scheme that significantly increases the rendering performance of modern graphic subsystems. Instead of rasterizing, texturing, lighting, and depth‐testing each individual pixel, we introduce a two‐level visibility mask within the rasterization stage which facilitates the removal of groups of pixels and triangles from rasterization and subsequent pipeline stages.Local visibility information is stored within the visibility mask that is updated several times during the generation of a frame. The update can easily be accomplished by extending already available (in hardware) occlusion culling mechanisms (i.e. those of HP and SGI), where it is possible to integrate the additional functionality without any additional delay cycles. In addition to these existing hardware based occlusion culling approaches—which cull only geometry contained in bounding volumes determined as occluded—we are able to significantly accelerate the rendering of the geometry determined as visible. However, our approach does not specifically rely on such occlusion culling hardware.The proposed new rasterization scheme is well suited for hardware implementation, can easily be integrated into low‐cost rasterizers, and its scalability can vary upon available chip real estate. Only incremental modifications of modern graphics subsystems are required to achieve a significant improvement in rendering performance.

The design and testing of a force feedback dental simulator

The Iowa Dental Surgical Simulator is a haptic simulator to train dental students in the haptic skills of dentistry. The initial design emphasizes the detection of carious lesions. This work describes the software and implementation of the prototype system, the design tradeoffs’ and the technical issues associated with haptic and graphics subsystems. The work also describes the current system performance, including a formal evaluation by practicing dentists and performance measures. A discussion of the limitations of the current system is followed by an analysis of opportunities to improve the quality of the simulator. The results should be of interest to designers of medical haptic simulation systems and other simulation designers.

PC-based DTV architecture

This paper presents the first PC-based DTV architecture using an industry standard PCI bus to transfer decoded video data from a DTV decoder to the graphics subsystem of a multimedia PC. The proposed architecture eliminates: (1) the need for a dedicated video port cable between a PC-based DTV decoder and a graphics controller, and (2) the need for a nonstandard graphics controller video port. This paper also presents a novel concept of bursting the decoded DTV data over the PCI bus with no visible video artifacts due to bus latency or different video/graphics refresh rates. In normal operation, this architecture consumes only about 31% of the bandwidth of a 33 MHz 32-bit PCI bus.

The 82460GX server/workstation chip set

Designing a chip set for a new processor architecture like the IA-64 requires handling multiple aspects. They include implementing the processor interface; providing sufficient I/O bandwidth for servers; supporting accelerated graphics port (AGP) graphics; and providing sufficient memory bandwidth for the processor, I/O, and graphics. This article provides an introduction to the memory, I/O, and graphics subsystems of Intel's Itanium processor chip set and discusses several aspects of the processor bus.

Faster 3D game graphics by not drawing what is not seen

The increasing demands of 3D game realism - in terms of both scene complexity and speed of animation - are placing excessive strain on the current low-level, computationally expensive graphics drawing operations. Despite these routines being highly optimized, specialized, and often being implemented in assembly language or even in hardware, the ever-increasing number of drawing requests for a single frame of animation causes even these systems to become overloaded, degrading the overall performance. To offset these demands and dramatically reduce the load on the graphics subsystem, we present a system that quickly and efficiently finds a large portion of the game world that is not visible to the viewer for each frame of animation, and simply prevents it from being sent to the graphics system. We build this searching mechanism for unseen parts from common and easily implemented graphics algorithms.

Color recovery: true-color 8-bit interactive graphics

For many years, the only practical way to display high-quality true-color images was on a computer having a graphics subsystem with at least 24 color planes. The high cost of color graphics devices with 24 planes led many users to choose 8-, 12-, or 16-plane systems. Unfortunately, using a system with fewer color planes sacrifices some color capabilities to save money. The paper discusses an innovation called color recovery that provides a method for displaying millions of colors within the cost constraints of an eight-plane system. One of the primary design goals for color recovery was to supply the additional color capabilities without giving up interactive performance. Another goal was to be able to work with all types of applications running in a windowed environment. An implementation of color recovery described in this article meets these goals.

Perception of detail and greyscale range in X-ray fluoroscopy images captured with a personal computer and frame-grabber

Objective: To assess the dynamic range of radiological images captured with a personal computer frame-grabbing system coupled to an X-ray fluoroscopy machine. Methods: A 386DX-40 MHz, IBM compatible, computer with an SVGA monochrome graphics subsystem and a 387 co-processor, installed with a Screen Machine frame-grabber and controlled by a program specially written was used. Various systems were examined and the observer's perceptions of the results assessed. Results: The dynamic range available to an ordinary X-ray fluoroscopy system was found to be restricted to about 750 mV. Similar measurements showed that the dynamic range was always restricted to 3/4–1/2 of the full available signal because of a high value of the dark voltage of the TV camera's target on all seven systems measured. The dynamic range of the computer — frame grabber system was found to be significantly wider than the Image Intensifier — TV camera chain but, surprisingly, it was affected by the type of file format used for image storing on disk. Clinical images from a barium meal examination as well as CT images captured after optimisation of the frame-grabber were found to contain large quantities of noise in the first two least significant bit planes making them redundant and limiting the grey levels needed for image display to less than 64. This number was also less than the 80 grey levels that could be discriminated by the human eye on the computer monitor. Conclusions: It was concluded that 6 bit digitisation would have been sufficient for image capture. The advantages of the wider dynamic range of the frame-grabber and the processing capabilities of the computer were tested for the possibility of improving the perception of detail. However, the results were negative. The limiting spatial resolution measured with a variable density bar pattern at all magnifications was about 0.4 lp/mm lower from that measured directly on the fluoroscopic screen. A detail perception test had the same result. The perception success was significantly lower with the digital images at all but the highest of the exposure rates and despite the use of image processing filters.

The measured performance of personal computer operating systems

This article presents a comparative study of the performance of three operating systems that run on the personal computer architecture derived form the IBM-PC. The operating systems, Windows for Workgroups, Windows NT, and NetBSD (a freely available variant of the UNIX operating system), cover a broad range of system functionality and user requirements, from a single-address-space model to full protection with preemptive multitasking. Our measurements are enable by hardware counters in Intel's Pentium processor that permit measurement of a broad range of processor events including instruction counts and on-chip cache miss counts. We use both microbenchmarks, which expose specific difference between the systems, and application workloads, which provide an indication of expected end-to-end performance. Our microbenchmark results show that accessing system functionality is often more expensive in Windows for Workgroups than in the other two systems due to frequent changes in machine mode and the use of system call hooks. When running native applications, Windows NT is more efficient than Windows, but it incurs overhead similar to that of a microkernel, since its application interface (the Win32 API) is implemented as a user-level server. Overall, system functionality can be accessed most efficiently in NetBSD; we attribute this to its monolithic structure and to the absence of the complications created by hardware backward-compatibility requirements in the other systems. Measurements of application performance show that although the impact of these differences is significant in terms of instruction counts and other hardware events (often a factor of 2 to 7 difference between the systems), overall performance is sometimes determined by the functionality provided by specific subsystems, such as the graphics subsystem or the file system buffer cache.

Round-Up

Silicon Graphics has increased the power of its range of graphics supercomputers with the Silicon Graphics Power Onyx. When combined with Silicon Graphics Reality-Engine2 graphics subsystem, the result is the world's fastest interactive 3-D design system.