Gold-induced Crystallization Research Articles

Kinetics of gold-induced layer exchange crystallization of amorphous silicon suboxide films: Experimental and theoretical study

The kinetics of gold-induced crystallization (AuIC) of amorphous silicon suboxide (a-SiOx, x = 0.2) films in the layer exchange mode was detailed studied by variation of the annealing temperature in the range of 220–250 °C for the first time. In situ optical microscopy performed during annealing made it possible to study the processes of the nucleation and the growth of Si crystal structures. A decrease in the nucleation rate during annealing was shown, which is probably associated with coarsening of grains in the Au film which is confirmed by scanning electron microscopy. Obtained experimental data along with the simulations carried out within the framework of the Kolmogorov–Johnson–Mehl–Avrami (KJMA) theory made it possible for the first time to obtain the values of the activation energies for the nucleation, the growth, as well as the overall process of AuIC of a-SiO0.2 which amounted to 2.51 ± 0.80, 0.31 ± 0.10, and 1.62 ± 0.15 eV, respectively.

Activation energy of gold-induced crystallization of amorphous silicon suboxide films

• Au-induced crystallization of a-SiO 0.2 films was carried out at 210–275 °C. • The activation energy for AuIC of a-SiO 0.2 was determined for the first time to be 1.7 ± 0.1 eV. • Raman spectroscopy revealed the improvement of crystalline properties of poly-Si films with decreasing annealing temperature. • XRD revealed the formation of poly-Si with (1 1 1) crystallographic orientation. Polycrystalline silicon (poly-Si) films were fabricated by gold-induced crystallization (AuIC) of amorphous silicon suboxide (a-SiO x , x = 0.2) films at temperatures of 210–275 °C. The films were studied by in situ optical microscopy, Raman spectroscopy, and X-ray diffractometry. The activation energy for AuIC of a-SiO 0.2 was determined for the first time to be 1.7 ± 0.1 eV.

Erratum to: Gold-Induced Crystallization of Thin Films of Amorphous Silicon Suboxide

Erratum to: Gold-Induced Crystallization of Thin Films of Amorphous Silicon Suboxide

Gold-Induced Crystallization of Thin Films of Amorphous Silicon Suboxide

Gold-Induced Crystallization of Thin Films of Amorphous Silicon Suboxide

Fabrication of polycrystalline silicon thin films by gold-induced crystallization of amorphous silicon suboxide

In this work, polycrystalline silicon (poly-Si) thin films were synthesized using Au-induced crystallization of amorphous silicon suboxide for the first time. The structure and elemental composition of the substrate/Au/a-SiO0.4 stacked structure annealed at 500–700°C were investigated by transmission electron microscopy (TEM), Raman, and energy-dispersive X-ray spectroscopy (EDX). TEM and Raman methods confirmed the formation of a poly-Si thin film in the bottom layer (on the substrate) as a result of annealing. At the same time, TEM and EDX studies showed the formation of a thin (barrier) SiO2 layer with a thickness of ~5 nm located between the poly-Si thin film and the upper layer consisting of Au, Si, and O. Based on the results, a mechanism for the growth of poly-Si thin films is proposed which has features (dewetting of Au films and formation of a barrier SiO2 layer) that are not characteristic of the well-known layer exchange process.

Золото-индуцированная кристаллизация тонких пленок аморфного субоксида кремния

For the first time, polycrystalline silicon (poly-Si) was obtained as a result of the gold-induced crystallization of amorphous silicon suboxide (a-SiOx). It is shown that, during annealing of a sample with a “substrate/gold thin film/a-SiO0.2 thin film” structure at 335 ℃, poly-Si is formed in a bottom layer (on the substrate), while gold diffuses into the upper layer. With an increase in the temperature to 370 ℃, the mechanism of poly-Si formation remains unchanged, however, only the rate of the crystallization process increases. Apparently, the process of poly-Si formation proceeds through the formation of gold silicides, which almost completely decompose into crystalline phases of gold and silicon at 370 ℃ for 10 h.

Effect of gold layer thickness on the low-temperature crystallization process of germanium thin films by gold-induced crystallization

The effect of Au layer thickness (1, 2.5, 5, 7.5 and 10 nm) on the low-temperature crystallization of Ge thin films (30 nm) was examined. It is found that the best Ge crystallinity is achieved at an Au layer thickness of 2.5 nm. This finding will open up the possibility to reduce the amount of Au consumption in the low-temperature crystallization process of Ge thin films.

A crystalline germanium flexible thin-film transistor

We experimentally demonstrate a flexible thin-film transistor (TFT) with (111)-oriented crystalline germanium (Ge) layers grown by a gold-induced crystallization method. Accumulation-mode metal source/drain p-channel Ge TFTs are fabricated on a polyimide film at ≤400 °C. A field-effect mobility (μFE) of 10.7 cm2/Vs is obtained, meaning the highest μFE in the p-TFTs fabricated at ≤400 °C on flexible plastic substrates. This study will lead to high-performance flexible electronics based on an inorganic-semiconductor channel.

Gold‐induced crystallization of amorphous germanium deposited on glass: Bilayer and multilayer films

Gold‐induced crystallization (GIC) of amorphous germanium (a‐Ge) using bilayer and multilayer films was performed through electron beam evaporation on glass substrates. The GIC of a‐Ge was studied while the post‐annealing temperature was varied between 250 and 550 °C for a fixed annealing time. The structure of polycrystalline Ge films was investigated by employing X‐ray diffraction (XRD), Raman spectra and scanning electron microscopy (SEM). In both the bilayer and multilayer films the crystallization of a‐Ge took place from 250 °C. The amount of crystallization fractioning and film quality were improved as the annealing temperature increased. However, preferentially (220) oriented crystalline Ge was formed in the bilayer films, indicating a micro‐crystalline structure of the Ge. In the multilayer configuration (111) oriented crystalline Ge was observed indicating a poly‐crystalline structure of the Ge. Scanning electron microscopy (SEM) images clearly highlight the grain size difference between these structures, especially for annealing temperatures above 400 °C.

(Invited) Low-Temperature Growth of Orientation-Controlled Large-Grain Ge-Rich SiGe on Insulator at Controlled-Position for Flexible Electronics

I NTRODUCTION Germanium-rich silicon-germanium (Ge-rich SiGe) (Ge fraction: 50−100%) provides higher carrier mobility and superior optical properties compared with Si. In the field of large-scale integrated circuits, Ge-rich SiGe devices are being employed to break through the scaling limit. Such an approach is also very useful in the fields of advanced thin-film electronics, such as system-in-displays. In addition, to improve the usability of the system-in-displays, Ge-rich SiGe-based high-performance thin-film devices should be integrated on flexible plastic substrates (softening temperature: ~350°C). For this purpose, a technique for low-temperature (≤300oC) growth of orientation-controlled large-grain (≥10 μm) Ge-rich SiGe on insulator should be developed. In addition, position control of the orientation-controlled large-grains is useful to obtain high-performance devices without degradation by grain boundaries. Various growth techniques were investigated to achieve SiGe on insulator. For example, solid-phase crystallization enables growth of poly-SiGe films on insulator. However, high-temperature annealing at a temperature above 500oC is necessary to induce crystallization of SiGe.For low-temperature growth of SiGe on insulator, we have been investigating metal-induced crystallization using gold as catalyst [1-4]. These efforts enable low-temperature growth of orientation-controlled large-grain Ge-rich SiGe on insulator at controlled-positions. LOW-TEMPERATURE GROWTH OF ORIENTATION-CONTROLLED LARGE-GRAIN BY INTERFACE-NUCLEATION In order to obtain poly-SiGe films on insulator at low temperatures, we have developed gold-induced crystallization (GIC), where a-SiGe/Au stacked structures are employed, as shown Fig. 1 [1]. Owing to bond-modulation by catalysis, GIC proceeds at ~250oC for SiGe with the whole Ge fractions (0−100%). However, for these samples, layer-exchange of the stacked structures results in formation of randomly-oriented poly-SiGe films on insulator.To achieve orientation-controlled large-grains by GIC, randomly-oriented bulk nucleation in Au layers should be suppressed and instead, preferentially-oriented nucleation at Au/insulator interfaces should be dominated. This domination of interface nucleation can be achieved through retarding Si and Ge supply into Au layers by introducing diffusion barrier between a-SiGe and Au layers, because interface nucleation is energetically favorable compared to bulk nucleation. Use of anisotropy of free energy of SiGe nuclei is a key for orientation control. Based on these ideas, we have examined control of nucleation site by modulating atomic diffusion in the layer-exchange process, as shown in Fig. 2(a). As a result, orientation-controlled large-grain Ge-rich SiGe crystals are realized on amorphous insulator at a low temperature (≤300oC) [2]. The growth of orientation controlled large-grains (≥50 μm) on flexible substrates becomes possible, as shown in Figs. 2(b)-2(d) [3]. The large grains provide high carrier mobility (160 cm2/Vs) [3]. POSITION CONTROL BY SPATIALLY-MODULATED NUCLEATION In order to control the positions of large grains, micro-opening in diffusion barrier is examined, as shown in Fig. 3(a) [4]. By decreasing the diameter of the micro-opening below 3 μm, a single interface-nucleus is selectively generated. This enables growth of orientation-controlled large-grains (≥10 μm) at controlled positions, as shown in Figs. 3(b) and 3(c). This technique will facilitate fabrication of high-performance Ge-rich SiGe thin-film devices for flexible electronics.

Low-Temperature Formation of Large-Grain (≥10 μm) Ge at Controlled-Position on Insulator by Gold-Induced Crystallization Combined with Diffusion-Barrier Patterning

Formation of position-controlled large-grain (≥10 μm) Ge crystals on insulator is realized at low-temperature (300°C) by gold-induced-crystallization using a-Ge/Au stacked structures. By introduction of diffusion barriers, i.e., thin-Al2O3 layers (2 nm thickness), having open-windows (3–20 μm diameter) into the a-Ge/Au interfaces, Ge crystals are selectively grown from the open windows. For open-windows with diameter of 20 μm, the grown areas consist of several Ge (111) grains. This is attributed to that several nuclei acting as seed are generated around the perimeters of the open windows. The number of seeds is linearly decreased by decreasing of the open-window diameter. As a result, (111)-oriented large (∼10 μm) Ge single-crystals, without any grain boundary, are obtained at controlled positions for open-windows with diameter of 3 μm. This technique will facilitate realization of flexible electronics and 3-dimensional large-scale integrated circuits, where Ge-based functional high-performance thin-film devices are integrated on flexible plastic substrates and/or amorphous insulating layers.

Low-temperature (≤ 300 °C) formation of orientation-controlled large-grain (≥ 10 μm) Ge-rich SiGe on insulator by gold-induced crystallization

Low-temperature (≤300°C) formation of orientation-controlled large-grain (≥10μm) Ge-rich (≥50%) SiGe crystals on insulator are realized by the gold-induced layer-exchange technique. Stacked structures of a-Si1−xGex (0≤x≤1)/Au/SiO2 are employed as starting materials. Here, thin-Al2O3 layers are introduced as diffusion barrier at a-SiGe/Au interfaces to suppress random bulk-nucleation and make (111)-oriented interface-nucleation on SiO2 dominant. For samples with Ge fraction of 80%–100%, (111)-oriented large-grains (≥10μm) are obtained through layer-exchange during annealing at 250°C. On the other hand, layer-exchange for Ge fraction of 50% does not proceed at 250°C. This phenomenon is attributed to retardation of lateral growth by introduction of Si. To enhance lateral growth, increase of annealing temperature is examined. As a result, (111)-oriented large-grains (≥10μm) are realized for SiGe with Ge fraction of 50%–100%, having uniform composition profiles, by annealing at 300°C. This technique is very useful to realize high-performance flexible electronics, employing plastic substrates (softening temperature: ~350°C).

High carrier mobility in orientation-controlled large-grain (≥50 μm) Ge directly formed on flexible plastic by nucleation-controlled gold-induced-crystallization

High-carrier-mobility semiconductors on flexible-plastic are essential to realize flexible electronics. For this purpose, electrical properties of orientation-controlled large-grain Ge crystals on flexible-plastic directly formed by nucleation-controlled gold-induced-crystallization (GIC) are examined, and compared with those obtained by aluminum-induced-crystallization (AIC). The Ge crystals show p-type conductions. Here, hole concentrations are 2.2 × 1017 and 5.8 × 1020 cm−3 for GIC-Ge and AIC-Ge, respectively, which are explained on the basis of the solubility of Au and Al in Ge. Thanks to the low hole concentration, GIC-Ge shows high hole mobility (160 cm2 V−1 s−1) compared with AIC-Ge (37 cm2 V−1 s−1). These demonstrate significant advantage of GIC to realize high-performance flexible-electronics.

(111)-oriented large-grain (≥50 µm) Ge crystals directly formed on flexible plastic substrate by gold-induced layer-exchange crystallization

Orientation-controlled large-grain Ge crystals grown on plastic substrates (softening temperature: ∼300 °C) are desired to realize advanced flexible electronics, where various functional devices are integrated on flexible substrates. To achieve this, gold-induced crystallization (annealing temperature: 250 °C) using a-Ge/Au stacked structures is developed on plastic substrates, where thin-Al2O3 layers (thickness: ∼7 nm) are introduced at a-Ge/Au interfaces. Interestingly, (111)-oriented nucleation at the Au/plastic interface dominates over random bulk nucleation in Au layers. As a result, the formation of (111)-oriented large-grain (≥50 µm) Ge crystals directly on flexible plastic substrates is realized. This technique will pave the way for advanced flexible electronics.

(Invited) Low-Temperature Metal-Induced Crystallization of Orientation-Controlled SiGe on Insulator for Flexible Electronics

Low-temperature (≤250oC) formation of orientation-controlled large-grain (>10 μm) poly-SiGe on amorphous insulator is essential to realize flexible electronics. In line with this, metal-induced crystallization of SiGe is investigated. By employing Au and Sn as catalysts, SiGe crystallization at 250oC and 150oC, respectively, becomes possible. Moreover, a technique for formation of orientation-controlled large-grain crystals is examined by modulation of nucleation in gold-induced crystallization. This achieves selectively (100)- or (111)-oriented large-grain (≥20 μm) crystals on amorphous insulators. This technique is expected to facilitate integration of advanced functional devices onto flexible substrates.

Formation of Large-Grain Ge(111) Films on Insulator by Gold-Induced Layer-Exchange Crystallization at Low Temperature

A formation technique of orientation-controlled large-grain (< 10 μm) Ge crystals on insulator at low temperature ({less than or equal to} 350oC) has been investigated to realize advanced flexible electronics. Previously, we proposed a gold-induced crystallization technique, and demonstrated low temperature crystallization (250oC) of Ge on insulator. In the present study, we intentionally inserted thin Al2O3 layers between gold and a-Ge layer, to control crystal nucleation. Consequently, (111)-oriented large-grain (< 20 μm) Ge crystals are obtained at 350oC by optimizing interfacial oxide layer thickness. It is speculated that this phenomena is attributed to suppression of random bulk nucleation of Ge in Au films and resultant dominance of interfacial nucleation at Ge/SiO2 interfaces.

Au誘起層交換成長法によるGe結晶/絶縁膜の極低温形成(∼250o)

Au誘起層交換成長法によるGe結晶/絶縁膜の極低温形成(∼250o)

Au-Catalyst Induced Low Temperature (∼250 ºC) Layer Exchange Crystallization for SiGe On Insulator

The gold-induced crystallization technique has been investigated to achieve poly-SiGe films on insulators at low temperatures (300ºC). By annealing of the amorphous SiGe (Ge concentration: 0-100%)/Au stacked structures formed on insulating substrates, positions of the SiGe and Au layers are inverted, and the Au/SiGe stacked structures are obtained. Crystallization of the SiGe layers in the inverted samples is confirmed by the Raman scattering spectroscopy analysis. Moreover, the Raman measurements reveal that the Ge fractions in the crystallized SiGe layers are almost the same as those of the initial amorphous SiGe layers. This gold-induced layer-exchange crystallization technique of SiGe layers at a low temperature (~250ºC) will be very useful to obtain poly-SiGe layers on plastic substrates, which are essential to realize flexible high-speed thin-films transistors and high-efficiency solar cells.

Low-Temperature Wafer Bonding Based on Gold-Induced Crystallization of Amorphous Silicon

Low-temperature wafer bonding based on gold-induced crystallization of amorphous silicon has been investigated for the first time in this letter. A bonding yield of 97% and a shear strength of 10.5 MPa were achieved when bonding the oxide wafers by the bonding method at 400°C applying 0.8-MPa pressure for 30 min. The microstructure analysis indicated that the gold-induced crystallization process leads to big Si grains extending across the bonding interface and Au filling the other regions of the bonding interface, which result to a strong and void-free bonding interface. More importantly, this bonding method can be used for other substrate materials.