Global Clock Distribution Research Articles

Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC

Automatic clock gating (ACG) is a clock-gating architecture with near zero waste on dynamic power dissipation on global clock distribution network. ACG models global clock structure as a graph with nodes and arcs representing clock components and their interconnections, respectively. Unlike conventional clock structure, where arcs are nothing more than clock nets, ACG adds control mechanism on the arc so that clock gating decision on each clock component can be automated. In this structure, each clock component can understand activities on its fan-outs and can be configured to cut off its output clock when there is no activity. The framework also allows clock consumers to define a period in time where their clock is guaranteed to be present. Combination of these features results in global clock structure, where unnecessary transition on any clock net is automatically avoided. The overall power benefit from this architecture is measured to be 17%–50%.

A mm-Wave Switched-Capacitor RFDAC

This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {{P_{\mathrm{ out}}}}&gt;21$ </tex-math></inline-formula> dBm, drain efficiency >36%, and system efficiency >22% while operating in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Background/Objectives: Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power and clock distribution networks consume a large portion of the limited on-chip metal resources. In order to reduce the metal overhead associated with the power, global clock, and local clock distribution networks, the concept of an integrated power and clock distribution network (IPCDN) was investigated and correct functionality of combinational and sequential elements verified. This study discusses potential power savings in IPCDNs achieved by reducing the central voltage at which the signal oscillates. Methods/Statistical analysis: In this paper, an IPCDN with differential power-clock signals centered at half the supply voltage is proposed to further reduce the power consumption. The elements of the proposed scheme including the LC differential power-clock driver, clamping circuit, clock buffer, and voltage doubler have been simulated using Tanner 0.25 um CMOS technology at a frequency of 50 MHz and a supply voltage of 2.5 V. Findings: Simulation results indicate that the proposed scheme achieves 75.32% and 76.47% power reduction in the LC differential powerclock driver and clock buffer, respectively. The effects of process, voltage supply, and temperature (PVT) variations on the proposed scheme were also investigated. Discussion: The IPCDN has a large capacitance and is heavily loaded, thus reducing the central voltage of the resonant sinusoidal signal flowing in this network enables significant reduction in power consumption. Novelty/Applications: The proposed scheme enables power reductions in the LC differential power clock driver and clock buffer. The effects of process, voltage supply, and temperature (PVT) variations on all circuit elements of the proposed scheme was investigated. Keywords: resonant clocking; power reduction; routing complexity; LC clock driver; clock buffer; clamping circuit; voltage doubler Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power and clock distribution networks consume a large portion of the limited on-chip metal resources. In order to reduce the metal overhead associated with the power, global clock, and local clock distribution networks, the concept of an integrated power and clock distribution network (IPCDN) was investigated and correct functionality of combinational and sequential elements verified. This study discusses potential power savings in IPCDNs achieved by reducing the central voltage at which the signal oscillates. Methods/Statistical analysis: In this paper, an IPCDN with differential power-clock signals centered at half the supply voltage is proposed to further reduce the power consumption. The elements of the proposed scheme including the LC differential power-clock driver, clamping circuit, clock buffer, and voltage doubler have been simulated using Tanner 0.25 um CMOS technology at a frequency of 50 MHz and a supply voltage of 2.5 V. Findings: Simulation results indicate that the proposed scheme achieves 75.32% and 76.47% power reduction in the LC differential powerclock driver and clock buffer, respectively. The effects of process, voltage supply, and temperature (PVT) variations on the proposed scheme were also investigated. Discussion: The IPCDN has a large capacitance and is heavily loaded, thus reducing the central voltage of the resonant sinusoidal signal flowing in this network enables significant reduction in power consumption. Novelty/Applications: The proposed scheme enables power reductions in the LC differential power clock driver and clock buffer. The effects of process, voltage supply, and temperature (PVT) variations on all circuit elements of the proposed scheme was investigated. Keywords: resonant clocking; power reduction; routing complexity; LC clock driver; clock buffer; clamping circuit; voltage doubler

On SFC Low Power Hardware Implementation in FPGAs

The paper presents an idea of automatic synthesis to an FPGA device of a program developed with use of the SFC including actions. The synthesis is oriented to achieve power reduction by creating multiple clock domains and controlling switching activity. A circuit is selectively clocked based on processing activity. Global clock distribution networks are used in order to assure proper operation of a system. Proposed methods automatically split a controller into clock domains and implements all necessary circuitry. The paper is concluded with benchmark experiments that proves energy consumption reduction for proposed methods in reference to standard approach using fully synchronous implementation methodology.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range

A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency (F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> ) adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect VDD droops across a wide range of operating conditions. The auto-calibration circuit maximizes the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> -droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively.

Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous

3D Stacked IC (3D-SIC) technology is becoming increasingly popular due to its improved design density and performance. However, single global clock distribution to a 3D-SIC can be very challenging and is far more prone to process and environmental non-idealities, which somewhat limits the scope of 3D-SICs. A possible solution to this problem is to perform inter-logic-layer communication in 3D-SICs using clock domain crossing (CDC) techniques. In this paper, we investigate the two classes of CDC techniques; the semi Quasi Delay Insensitive QDI-based asynchronous and loosely synchronous CDC. In particular, the paper explores the main challenges faced by these CDC techniques in utilizing through-silicon vias (TSVs). Representative designs from each technique are used for performing proof of concept electrical simulations. Our experimental results are expected to facilitate the 3D-SIC logic designers to choose the most appropriate CDC technique for a given design context. For example, one of the key findings of this paper is that although semi QDI-based asynchronous design provides an attractive solution because of its relaxed constraint on clock distribution network, but it has more timing overhead for TSV failures than the counterpart loosely synchronous design.

A 780 mW 4 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\times$&lt;/tex&gt;&lt;/formula&gt; 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS

This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.

An 8&amp;#x2013;16 Gb/s, 0.65&amp;#x2013;1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning

Serial link transmitters which efficiently incorporate equalization, while also enabling fast power-state transitioning to leverage dynamic power scaling, are necessary to meet future systems' I/O requirements. This paper presents a scalable voltage-mode transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Topologies that allow for rapid power-up/down, including a replica-biased voltage regulator to power the output stages of multiple transmit channels and per-channel quadrature clock generation with injection-locked oscillators (ILO), enable fast power-state transitioning. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300 mV with up to 12 dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency and sub-3 ns power-up/down times.

A 4.8-mW/Gb/s 9.6-Gb/s 5 &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$+$&lt;/tex-math&gt;&lt;/inline-formula&gt; 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

A low-jitter and low-power source-synchronous serializer/deserializer transmitter (TX) with a data rate of 9.6 Gb/s is presented. The TX consists of five data channels plus one forwarded-clock channel and features a total jitter of 20.39 ps p-p at 10-12 bit error rate. Low jitter is achieved through the use of a phase-locked loop with bandwidth linearization that has a random RMS jitter of 0.66 ps. A global clock distribution network is proposed to minimize the power-supply-induced jitter and the power consumption. The TX transmits preemphasized data through a current-mode logic driver with a four-tap feedforward equalizer. The on-chip output impedance and the signal amplitude can be accurately calibrated by a successive approximation register logic separately. The total power consumption for the 5 +1-lane TX physical core fabricated in 65-nm bulk CMOS running at 9.6 Gb/s is 230 mW or 4.8 mW/Gb/s.

Integrated Power and Clock Distribution Network

In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a differential power-clock signal (Pwr_Clk) with a suitable dc voltage level and sinusoidal voltage-swing feeds the VDD ports in combinational and sequential elements. A clock buffer is used for sequential elements in order to extract a full-swing clock from the differential Pwr_Clk+ and Pwr_Clk- signals. IPCDN does not require any change to be made to the conventional combinational and sequential circuit design. The proposed elements of IPCDN, including the LC differential Pwr_Clk driver and the clock buffer, have been simulated using Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology with a Pwr_Clk signal, a 1-V dc component, and 400-mV sinusoidal swing at a frequency of 5 GHz. In addition, the behavior of a master-slave flip-flop with IPCDN was investigated at extreme corners. Simulation results demonstrate correct functionality of all elements of the IPCDN. Comparing IPCDN to a buffered square-wave clock distribution network illustrates that, with a heavily loaded network, IPCDN achieves around 20% reduction in power. This percentage increases when the network capacitance is dominating.

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation

This paper presents an adaptive far-end crosstalk cancellation scheme for a single-ended parallel receiver. The adaptation engine is embedded in a single representative channel CDR, and the receiver efficiently reduces the crosstalk noise with a minimal cost in hardware and power consumption. In addition, the proposed scheme can be applied to any given CDR and equalizing circuits. The receiver is fabricated in 0.13 μm CMOS technology and achieves a reduction of FEXT-induced jitter up to 75%. The receiver consumes 65 mW at 5 Gb/s (4.3 mW/Gb/s/pin) including a PLL for global clock distribution.

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance

An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> ) droops on microprocessor performance and energy efficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in critical paths during a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> droop. The tunable-length delay prevents critical-path timing-margin degradation for multiple cycles after the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> droop occurs, thus allowing a sufficient response time for dynamic adaptation. An on-die dynamic variation monitor detects the onset of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> droop to proactively gate the clock at the end of the tunable-length delay to eliminate the clock edges that would otherwise degrade critical-path timing margin. In comparison to a conventional clock distribution, silicon measurements from a 22 nm test chip demonstrate simultaneous throughput gains and energy reductions of 14% and 3% at 1.0 V, 18% and 5% at 0.8 V, and 31% and 15% at 0.6 V, respectively, for a 10% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> droop.

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

AMD's 32-nm x86-64 core code-named “Piledriver” features a resonant global clock distribution to reduce clock distribution power while maintaining a low clock skew. To support a wide range of operating frequencies expected of the core, the global clock system operates in two modes: a resonant-clock (rclk) mode for energy-efficient operation over a desired frequency range and a conventional, direct-drive mode (cclk) to support low-frequency operation. This dual-mode feature was implemented with minimal area impact to achieve both reduced average power dissipation and improved power-constrained performance. In Piledriver, resonant clocking achieves a peak 25% global clock power reduction at 75 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C, which translates to a 4.5% reduction in average application core power.

Design of silicon-based fractal antennas

This article presents Sierpinski carpet fractal antennas implemented in conventional low resistivity (ρ =10 Ω cm) as well as high resistivity (ρ =1500 Ω cm) silicon mediums. The fractal antenna is 36% smaller as compared with a typical patch antenna at 24 GHz and provides 13% bandwidth on high resistivity silicon, suitable for high data rate applications. For the first time, an on-chip fractal antenna array is demonstrated in this work which provides double the gain of a single fractal element as well as enhanced bandwidth. A custom test fixture is utilized to measure the radiation pattern and gain of these probe-fed antennas. In addition to gain and impedance characterization, measurements have also been made to study intrachip communication through these antennas. The comparison between the low resistivity and high resistivity antennas indicate that the former is not a suitable medium for array implementation and is only suitable for short range communication whereas the latter is appropriate for short and medium range wireless communication. The design is well-suited for compact, high data rate System-on-Chip (SoC) applications as well as for intrachip communication such as wireless global clock distribution in synchronous systems. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:180–186, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27245

Effect of process variations in 3D global clock distribution networks

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a per-data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER <; 10-12 across a 20-cm FR4 PCB channel.

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the × 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps.

Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees

Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic operations between sequential elements. Moreover, time-varying supply noise injected in global clock drivers can worsen the timing margin of critical paths by modulating period jitter. In the planning stage of global clock distribution for a high-end microprocessor, it is very critical to differentiate and understand the impacts of different design parameters on period jitter. However, it is hard to achieve due to complex relationship among different independent/dependent design parameters: supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, temperature, process corners, etc.

A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors

A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90 nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7 more energy per packet and 2.8-6.4 greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and identical throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixed-timing (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement.