GHz Output Frequency Research Articles

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ABSTRACT This paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of −77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves −59.7 dBc. It measures the 1.2 s settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 s settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is −105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.

A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique

This paper presents a low-jitter and low-phase noise type-II charge pump and switched-loop filter-based (SLF) phase-locked loop (PLL) with a fast phase error correction technique (FPEC) and a newly proposed dual-edge phase comparator (DEPC). To improve the phase noise, the bandwidth of the proposed PLL is extended to fREF/5 using the proposed DEPC. It consists of four D flip-flops in true single-phase clock (TSPC) logic, four current-mode logic-based inverters, and two logic OR gates. Unlike conventional DEPCs, the proposed DEPC has a small reset pulse width duration and negligible blind zone, and due to this, it can perform at higher frequencies along with an increased phase detection range. The proposed architecture is implemented for a 2.4 GHz output frequency that embodies DEPC and SLF using the FPEC technique in an 180-nm Semi-Conductor Laboratory (SCL) CMOS process. The proposed DEPC can work up to a maximum of 3.45 GHz frequency with 145 ps of reset delay. The proposed PLL accomplishes the 40 MHz bandwidth with a 200 MHz reference clock. The simulated rms jitter integrated from 10 kHz to 100 MHz and the phase noise of the output signal at an offset of 1 MHz are 860 fs and −122 dBc/Hz respectively. The proposed architecture occupies an area of 0.032 mm2 and consumes 8.2 mW from 1.8 V power supply.

A Tunable Dielectric Resonator Oscillator with Phase-Locked Loop Stabilization for THz Time Domain Spectroscopy Systems

Precision microwave measurement systems require highly stable oscillators with both excellent long-term and short-term stability. Compared to components used in laboratory instruments, dielectric resonator oscillators (DRO) offer low phase noise with greatly reduced mechanical complexity. To further enhance performance, phase-locked loop (PLL) stabilization can be used to eliminate drift and provide precise frequency control. In this work, the design of a low-cost DRO concept is presented and its performance is evaluated through simulations and measurements. An open-loop phase noise of −107.2 dBc/Hz at 10 kHz offset frequency and 12.8 GHz output frequency is demonstrated. Drift and phase noise are reduced by a PLL, so that a very low jitter of under 29.6 fs is achieved over the entire operating bandwidth.

A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS

This paper presents a 208-MHz, 0.75-mW selfcalibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency.

A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique

This paper proposes a self-aligned sub-harmonically injection locked phase locked loop (SILPLL) in 180-nm Semi Conductor Laboratory (SCL) CMOS technology. In this work, an aperture phase detector (APD) based delay locked loop (DLL) with windowing technique is proposed to dynamically align the injection timing of pulse with the rising edge of sub-harmonically injection locked voltage controlled oscillator. In contrast to classical self-aligned SILPLL, this work replaces the commonly deployed tri-state based phase frequency detector (PFD) in DLL by an APD, which becomes active over a pulse-window. The APD deployed in DLL reduces the in-band phase noise due to the charge pump by 12 dBc at 200 KHz offset in comparison with the classical self-aligned DLL. A detailed mathematical model of the self-aligned injection with noise sources is presented for the proposed architecture. Additionally, this work includes noise analysis with the effect of different design aspects such as locking range, and realignment factor. The proposed architecture operates at 1.8 GHz output frequency, and the simulated phase noise is −120.6 dBc/Hz at 1 MHz offset with an integrated root-mean-square jitter of 0.96 ps from 10 kHz to 30 MHz. The implemented PLL consumes 6.6 mW from 1.8 V power supply.

A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-based Cascaded Fractional-N PLL with Burst-Mode Sampling

This brief presents a compact and power-efficient full ring-oscillator (RO)-based cascaded fractional-N PLL. The proposed cascaded PLL consists of a RO-based DLL and type-II PLL as the first and second stages, respectively. The first stage serves as a frequency multiplier that increases the operating frequency of the delta-sigma modulator (DSM) in the second stage, thereby suppressing its quantization noise. A burst-mode sampling (BMS) scheme is introduced to improve the phase noise (PN) of the frequency multiplier and achieves a PN multiplication factor removal. Implemented in a 28nm CMOS technology, the PLL prototype occupies a 0.016 mm2 active area, achieving a 686 fs integrated rms jitter from 10KHz to 40MHz at a 4 GHz output frequency; while consuming 10.21mW with -233.6 dB FoMjitter. The measured fractional and reference spurs are -59.8 dBc and -54.5 dBc, respectively.

A 2.5–5.0-GHz Clock Multiplier With 3.2–4.5-mUIrms Jitter and 0.98–1.06 mW/GHz in 65-nm CMOS

We present a two-stage cascaded clock multiplier with roughly constant energy consumption across 2.5-5.0GHz frequency range. The proposed clock multiplier consists of a reconfigurable delay-locked loop and edge combiner in the first stage while generating a 156.25-312.5MHz clock from 39.0625MHz reference clock frequency. An injection-locked clock multiplier with a frequency tracking loop in the second stage implements a 2.5-5.0 GHz output clock. The clock generation architecture is optimized for the clock multiplication ratio in the two stages and overall power consumption. Designed in TSMC 65nm CMOS process and characterized with post-layout simulations, the first-stage clock multiplier achieves an integrated jitter 1.396-0.607ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 156.25-312.5MHz frequency range at 1.15-2.82mW power consumption. The two-stage clock multiplier gives the total output jitter 1.5-0.9ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 2.5-5.0 GHz output frequency with 0.98-1.06mW/GHz power dissipation.

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications.

The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of −112.43 and −133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V.

A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT

A reconfigurable LO-generator (LOG) using an integer divider and a mixed-mode fractional divide-by-2.5 (Div2.5) is presented to generate a spurious and oscillator pulling free output spectrum without additional digital calibration for cellular narrowband Internet of Things (NB-IoT). The proposed LOG includes a fractional divider to mitigate the pulling effect between the oscillator and the power amplifier. The designed fractional Div2.5 consists of a digital Div2.5 core, a duty cycle corrector (DCC), and an I/Q generator (I/Q-GEN). An adaptive bias circuit (ADB) is applied to compensate for process, voltage, and temperature (PVT) variations on delay circuits of the DCC and the I/Q-GEN by adjusting the supply voltage. The designed LOG is fabricated in the 28-nm CMOS process while consuming 40 mW, including ADPLL, digitally controlled oscillator (DCO), local oscillator (LO) distribution buffers, and dividers at 2 GHz. The measured phase noise of the Div2.5 LOG generating 2-GHz carrier frequency is −146.3 dBc/Hz at a 10-MHz offset. The measured fractional spurious tones are below −90 dBc without oscillator pulling effects for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\sim 2.1$ </tex-math></inline-formula> -GHz output frequency.

A soft-error-tolerant, 1.25 GHz to 3.125 GHz, 3.18 ps RMS-jitter CPPLL in 40 nm CMOS process

This paper analyzes the mechanism by which Single-Event-Upsets (SEUs) and Single-Event-transients (SETs) impact on the working condition of the charge-pump-phase-locked-loop (CPPLL) and relevant hardened techniques, and also presents a soft-error-tolerant CPPLL in 40 nm CMOS process. It employs dual-mode interlocking (DMI) and divider-resistance techniques to reduce the soft-error rate caused by natural irradiation. Simulation and laser test results reveal that the DMI and divider resistance techniques could effectively decrease the number of SEU-sensitive nodes in digital parts (frequency divider, phase, and frequency detector) and SET-sensitive nodes in charge pumps. Under 960pJ laser energy, the number of SEU-sensitive nodes in digital parts decreases 96.1%; the number of SET-sensitive nodes in charge pump decline by 83.1%. The proposed soft-error-tolerant CPPLL operates under a 1.1 V power supply, consumes 16.6 mW of power, and achieves 1.25 GHz - 3.125 GHz working frequency range, 3.18 ps RMS-jitter at a 2.5GHz output frequency.

A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology

In this paper, a new low-power charge pump (CP) is presented, which includes a switched-capacitor CP (SC-CP) as the main CP and an auxiliary current-steering CP (ACS-CP) to accelerate the lock process. By using a pulse width controller unit, the ACS-CP activates in predefined phase differences and turns off near the lock region. By utilizing the proposed CP, the issue of traditional current-mismatch error is removed. Also, a new glitch-free phase frequency detector (PFD) with removed reset feedback path to drive the proposed charge pump is presented. Post-layout simulation results in TSMC 65 nm CMOS technology with a 1.2 V supply voltage indicate that the proposed CP consumes 5.4 µW at 125 MHz in the lock state. Also, the proposed PFD illustrates ± 2π detection range and consumes 26.33 µW at 125 MHz. When the proposed CP and PFD are applied to a PLL system, settling time is decreased by more than 50 percent. Also, reference spur at 125 MHz frequency offset and at 8 GHz output frequency is −69 dB. The proposed PFD and CP together occupy an area of 0.0058 mm2.

Design of PWM-Based Digital Receiver for 5G

The next generation, 5G and 6G standards, are allocated different bands for the same standard due to the worsening shortage of available spectrum. This has led to significant research interest in digitizing the RF signal as close as possible to the antenna motivated by flexibility and high performance allowed by cognitive radio and software defined radio. In this paper, a PWM-based all digital receiver is Presented. A system level simulation of the pulse-width modulator is performed using cadence software. In addition, a high-speed two-stage dynamic CMOS-latched comparator is proposed. In addition, a high-speed ring oscillator for clock generation is given. The proposed pulse-width modulator is implemented with a target technology TSMC 65nm process. The comparator achieves sampling frequency up to 10 GHz with resolution of 10.11 bits and 13.28 bits at 1 GHz sampling clock while keeping the propagation delay less than 64 psec. for 1 mV input voltage difference. Furthermore, the oscillator achieves a 10.025GHz output frequency.

A reference frequency quadrupler for high performance frequency synthesizers

A low noise frequency quadrupler for differential crystal oscillators (XOs) with an integerated jitter of 67 fsrms is proposed in this paper. A digitally duty cycle correction loop with fast convergence time is proposed to decrease the periodic deterministic jitter of the quadrupled reference clock. A ring-based injection-locked clock multiplier (ILCM) is implemented to show the effectiveness of the reference quadrupler. The output clock of ILCM achieves an integrated jitter of 387 fsrms at 2.8 GHz output frequency with a total multiplication factor of 56 and 6.2 mW consumed power from 1.2 V supply. The proposed design was implemented using 130-nm CMOS process.

A Supply-Noise-Insensitive Digitally-Controlled Oscillator

A digitally controlled oscillator (DCO) is presented that utilizes the non-linearity of a resistor-triode combination in conjunction with a weak latch to mitigate the supply sensitivity of inverter-based delay cells and remain supply noise insensitive over a wide range of supply variation. A proof-of-concept prototype for the DCO in 65 nm-CMOS process occupies $90\times 210\,\,\mu \text{m}\,\,^{\mathrm{ 2}}$ area and consumes 2.25 mW operating over a range of 0.9–1.4 GHz output frequency. At 850 Mv-supply voltage, the frequency pushing of DCO is zero at the optimal point and remains less than 10% over a large excursion of 50 mVpp. When embedded into an all-digital phase locked loop, closed-loop measurements demonstrate that supply noise with 50 mVppmagnitude does not impact the loop dynamics.

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital ΣΔ modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

Phase noise reduction in LC cross coupled oscillators using sinusoidal tail current shaping technique

In this paper, using the concept of impulse sensitivity function (ISF) in Hajimiri's phase noise model, a novel circuit method for phase noise reduction in LC cross coupled oscillators is proposed. Based on the proposed technique, at outputs zero crossing points, where ISF is maximum, current supplying to the transistor pair is stopped by two added transistors. Due to the shaped effective ISF waveform and also reduction of its RMS value, phase noise is decreased. In addition, the cascode structure of the proposed technique leads to more phase noise reduction due to the suppression of the transistors noise power. The proposed circuit is designed for 10 GHz output frequency and inductor quality factor of 12, and simulated in a standard 0.18 µm CMOS technology with a 1.8 V supply. Compared to the simple cross coupled oscillator, phase noise at 1 MHz and power consumption are reduced by 8 dB and 26%, respectively. The phase noise and FOM for the proposed oscillator at 1 MHz offset frequency are ýý107.8 dBc/Hz and 186.2 dB, respectively.

A Low-Power Frequency Multiplier for Multi-GHz Applications

A programmable frequency multiplier operating in GHz frequency range is proposed in this paper. The architecture is based on the combination of a multi-segment programmable and power efficient phase interpolator with an edge combiner. The system is designed in a 65 nm process with 1.0 V supply voltage offering a multiplication factor ranging from 1 to 8 with integer step. The layout area is 104 μm × 96 μm and the power consumption is 6.6 mW for 4.992 GHz output frequency. Post-layout simulation results including the multi-phase ring oscillator verify −91.6 dBc/Hz phase noise at 4.992 GHz for 1 MHz frequency offset.

A 0.0021 mm21.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Modern multicore processors employ multiple phase-locked loops (PLLs) to operate individual cores at a power-optimal frequency. This paper presents techniques to implement such PLLs in a small area. The area occupied by classical charge-pump-based analog PLLs is mostly due to the large loop filter capacitor needed to implement the integral control portion of type-II response. Digital PLLs (DPLL) can eliminate the capacitor by implementing the integral control in digital domain but their jitter performance is degraded by the quantization error introduced by DPLL building blocks such as a time-to-digital converter (TDC). We seek to combine the advantages of analog (no quantization error) and digital (small area) PLLs by implementing the integral control using time-based techniques. To this end, a ring oscillator-based integrator (ROI) is used to implement the integral control. ROI integrates its input and generates an output in the form of a pulse-width modulated (PWM) signal. While the ROI does not introduce quantization error, controlling the voltage controlled oscillator with the PWM signal introduces undesirable spurious tones. We propose to use a pseudo-differential ROI to mitigate these tones and achieve good jitter performance. Fabricated in 65 nm CMOS LP process, the prototype PLL occupies an active area of only 0.0021 mm2 and operates across a supply voltage range of 0.6 V to 1.2 V providing 0.4–2.6 GHz output frequencies. At 2.2 GHz output frequency, the PLL consumes 1.82 mW at 1 V supply voltage, and achieves 3.73 psrms integrated jitter. This translates to an FoMJ of −226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area.

A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.