Germanium-on-insulator Substrates Research Articles

Enhanced light emission of germanium light-emitting-diode on 150 mm germanium-on-insulator (GOI).

Germanium-on-insulator (GOI) has emerged as a novel platform for Ge-based electronic and photonic applications. Discrete photonic devices, such as waveguides, photodetectors, modulators, and optical pumping lasers, have been successfully demonstrated on this platform. However, there is almost no report on the electrically injected Ge light source on the GOI platform. In this study, we present the first fabrication of vertical Ge p-i-n light-emitting diodes (LEDs) on a 150 mm GOI substrate. The high-quality Ge LED on a 150-mm diameter GOI substrate was fabricated via direct wafer bonding followed by ion implantations. As a tensile strain of 0.19% has been introduced during the GOI fabrication process resulting from the thermal mismatch, the LED devices exhibit a dominant direct bandgap transition peak near 0.785 eV (∼1580 nm) at room temperature. In sharp contrast to conventional III-V LEDs, we found that the electroluminescence (EL)/photoluminescence (PL) spectra show enhanced intensities as the temperature is raised from 300 to 450 K as a consequence of the higher occupation of the direct bandgap. The maximum enhancement in EL intensity is a factor of 140% near 1635 nm due to the improved optical confinement offered by the bottom insulator layer. This work potentially broadens the GOI's functional variety for applications in near-infrared sensing, electronics, and photonics.

Manufacturing of Optimized Ge Substrates Using a Covalent Bonding Process

Germanium is an interesting material for applications ranging from nanoelectronics to solar cells, near infrared detectors, gamma spectroscopy detectors or optical components [1]. Previous studies demonstrated the interest of thick germanium-on-insulator (GeOI) substrates for the manufacturing of advanced photonics devices [2].Two methods are commonly used to manufacture GeOI substrates for photonic applications. First, a rather thick, slightly tensily strained Germanium layer can be grown on top of a 200mm Si(001) wafer and the top part transferred, thanks to the Smart CutTM approach, onto oxidized Si. The threading dislocation density in that Ge layer will be of the order of a few 106 cm-2, then, which could be a drawback for future applications. To manufacture GeOI with, on top, a higher quality Ge film, another approach is to start from bulk Ge, which has a much better crystalline quality [3, 4]. The drawback of this approach is that the thin Ge film on top of the GeOI substrate does not have any internal strain, then. In order to fabricate high quality strained GeOI substrates, in the end, one could start from Ge films coming from bulk Ge donors and strain while bonding them on top of 200mm Si(001) substrates.Covalent bonding is an interesting candidate in order to obtain high quality Ge films on Si while managing, at the same time, the internal stress. Indeed, stress can be tailored with the proper temperature control during the bonding process itself. The EVG®Combond® equipment used in this study enables to bond at “high” temperature Si/Ge heterostructures with a very high bond strength. In this paper, the bonding process performed will be described and characterized.A bonding at temperatures higher than Room Temperature is adopted to generate tensily strained Ge films. The choice of the right temperature depends on two criteria, however: (i) have the highest stress possible in the future Ge film and (ii) allow the Si/Ge heterostructure with thick substrates to withstand the stress without breaking at room temperature just after bonding. Point (i) requires high temperatures, while low temperatures are better for point (ii); a tradeoff will thus have to be identified. Simulations were performed in order to evaluate the bow of the structure after bonding and will be presented in the paper.Si/Ge heterostructures were fabricated at 100°C. A very high bond strength (> 5 j/m2) was measured using the classical double cantilever beam (DCB) technique on an equivalent Si/Ge/Si structure. Indeed, the bow with a Si/Ge heterostructure was too important to allow a correct bond strength measurement. Thus, an epitaxy of a few µm of Ge was performed on top of a Si wafer and the Si/Ge stack bonded to another Si wafer with the same covalent bonding process prior to measurements of the bonding interface strength. Bow in temperature of the Si/Ge heterostructure was also measured. A heating ramp and then a cool down phase were applied to the bonded pair in an atmospheric pressure chamber with a curvature radius measurement done with a laser beam. The bonded pair reached an equilibrium point with a bow of 0 µm for a temperature close to 100°C, in line with the bonding temperature adopted (figure 1).Using this newly qualified bonding process, a strained Ge film was transferred onto an Si wafer. The process flow will be described in the paper, as well as the characterization of the thin Ge film transferred at the end of the process. The quality of the Ge film will be characterized using a SP2 equipment in haze mode. Transmission Electron Microscopy will be performed to observe the amorphous zones at the bonding interface, and Focused-Ion-Beam Scanning Electron Microscopy will yield the thickness of the Ge film transferred. Figure 1: Bow measurement in temperature of a Si/Ge heterostructure, bonded using a covalent bonding process at 100°C [1] R. King et al., ‘Pathways to 40% efficient concentrator photovoltaics’. 20th European Photovoltaic Solar Energy Conf., Barcelona, Spain, 2005, p. 118[2] V. Reboud et al., “Structural and optical properties of 200 mm germanium-on- insulator (GeOI) substrates for silicon photonics applications,” Proc. SPIE 936714, 1–6 (2015). [3] F. Letertre et al., ‘Germanium-on-insulator (GEOI) structure realised by the Smart CutTM technology’, Mater. Res. Soc. Proc., 2004, 809, (B4.4), p. 153[4] C. Deguet et al., ‘200 mm germanium-on-insulator (GEOI) structures realized from epitaxial wafers using the smart cut technology’, Electrochem. Soc. Proc., 2005, 2005-06, p. 78 Figure 1

Performance of AlGaInP LEDs on silicon substrates through low threading dislocation density (TDD) germanium buffer layer

Performance of GaInP/AlGaInP multi-quantum wells light-emitting diodes (LEDs) grown on low threading dislocation density (TDD) Germanium-on-Silicon (Ge/Si) substrates are compared and studied. Three approaches are used to realize the low TDD Ge/Si substrates. The first approach is the two-step growth of Ge/Si substrate with TDD of ∼5 × 107 cm−2. The second approach is through doped the Ge seed layer with arsenic (As) and TDD of <5 × 106 cm−2 can be achieved. The third approach is through wafer bonding and layer transfer techniques, germanium-on-insulator (GOI) substrate with TDD of ∼1.2 × 106 cm−2 can be fabricated. To demonstrate the quality of these Ge/Si substrates, LEDs fabricated on commercially available Ge/Si and bulk Ge substrates were also included for comparison purposes. The LEDs fabricated on the As-doped Ge/Si and GOI substrates exhibit superior performances, with output light intensity at least 2× higher compared to devices fabricated on commercially available Ge/Si substrate. These findings enable the monolithic integration of visible-band optical sources with Si-based control circuitry.

High-performance AlGaInP light-emitting diodes integrated on silicon through a superior quality germanium-on-insulator

High-performance GaInP/AlGaInP multi-quantum well light-emitting diodes (LEDs) grown on a low threading dislocation density (TDD) germanium-on-insulator (GOI) substrate have been demonstrated. The low TDD of the GOI substrate is realized through Ge epitaxial growth, wafer bonding, and layer transfer processes on 200 mm wafers. With O2 annealing, the TDD of the GOI substrate can be reduced to ∼1.2×106 cm−2. LEDs fabricated on this GOI substrate exhibit record-high optical output power of 1.3 mW at a 670 nm peak wavelength under 280 mA current injection. This output power level is at least 2 times higher compared to other reports of similar devices on a silicon (Si) substrate without degrading the electrical performance. These results demonstrate great promise for the monolithic integration of visible-band optical sources with Si-based electronic circuitry and realization of high-density RGB (red, green, and blue) micro-LED arrays with control circuitry.

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

Germanium-on-insulator virtual substrate for InGaP epitaxy

In this work, we investigate the bonding processes to improve Germanium-on-insulator (GOI) quality for III–V integration, and an InGaP LED has been grown and characterized on this GOI substrate. The threading dislocation density (TDD) of GOI was reduced from 5.1±0.8×108cm−2 to 4.3±0.4×107cm−2 by chemical mechanical polishing (CMP) processes. The thermal and mechanical properties of the CMPed GOI have been characterized. It showed that a 200nm thermal oxide layer effectively absorbed the hydrogen generated from the bonding by-product reactions, which avoided the formation of thermal bubbles and provided sufficient stability during high temperature epitaxy processes. After post-bonding annealing, a high bonding strength of 1720.6mJ/cm2 was achieved. Then, an AlInGaP/InGaP multi-quantum well (MQW) LED was grown on GOI substrate. Compared to LED on bulk Ge substrate, LED on GOI showed high leakage current due to the presence of high TDD in the Ge layer and the LED junctions. The electroluminescence of LED on GOI was approximately 50% of the light output of LED on bulk Ge.

Highly n-doped germanium-on-insulator microdisks with circular Bragg gratings.

We demonstrate germanium (Ge) microdisks surrounded by highly reflective circular Bragg gratings on highly n-doped germanium-on-insulator (GOI) substrate. The GOI substrate is fabricated by wafer bonding from Ge grown on Si substrate, and n-type doping concentration of 2.1×1019 cm-3 is achieved by phosphorus diffusion from a spin-on-dopant source. Very sharp Fabry-Perot resonant peaks with high contrast fringes and Q-factors up to 400 are observed near the direct band gap of Ge in photoluminescence spectra. The reflectivity of gratings are enhanced by a factor larger than 3 in a wide wavelength range from 1.57 to 1.82 µm, compared with that of Ge/SiO2 interfaces in normal microdisks without circular Bragg gratings. The surface emission intensity of the devices is found to be increased by the grating period. Our results indicate that GOI microdisk with circular Bragg grating is a promising optical resonator structure suitable for realizing low threshold, compact Ge lasers integrated on Si substrate.

Germanium-on-insulator virtual substrate for InGaP epitaxy

In this work, we investigate the bonding processes to improve Germanium-on-insulator (GOI) quality for III–V integration, and an InGaP LED has been grown and characterized on this GOI substrate. The threading dislocation density (TDD) of GOI was reduced from 5.1±0.8×108cm−2 to 4.3±0.4×107cm−2 by chemical mechanical polishing (CMP) processes. The thermal and mechanical properties of the CMPed GOI have been characterized. It showed that a 200nm thermal oxide layer effectively absorbed the hydrogen generated from the bonding by-product reactions, which avoided the formation of thermal bubbles and provided sufficient stability during high temperature epitaxy processes. After post-bonding annealing, a high bonding strength of 1720.6mJ/cm2 was achieved. Then, an AlInGaP/InGaP multi-quantum well (MQW) LED was grown on GOI substrate. Compared to LED on bulk Ge substrate, LED on GOI showed high leakage current due to the presence of high TDD in the Ge layer and the LED junctions. The electroluminescence of LED on GOI was approximately 50% of the light output of LED on bulk Ge.

Demonstration of ultra-thin buried oxide germanium-on-insulator MOSFETs by direct wafer bonding and polishing techniques

The ultra-thin body and ultra-thin buried-oxide (UTBB) Germanium-on-Insulator (GeOI) substrates have been fabricated by direct wafer bonding and polishing techniques. The Ge and BOX layer thicknesses are as thin as 9 and 13 nm, respectively. The UTBB GeOI substrates exhibit superior crystal quality (similar to the bulk single crystalline Ge) and sufficiently reduced surface roughness. As a result, the Hall hole mobility of UTBB GeOI reaches 1330 cm2/V s with a carrier concentration of 2 × 1016 cm−3. The inversion mode UTBB GeOI nMOSFETs have also been demonstrated with suppressed mobility degradation during Ge layer thinning, indicating the feasibility of this GeOI substrate formation technique in future CMOS technologies.

Characterization of ultrathin-body Germanium-on-insulator (GeOI) structures and MOSFETs on flipped Smart-Cut™ GeOI substrates

A novel way to realize UTB GeOI substrates, where the high quality surface layers of Smart-Cut™ GeOI is utilized for UTB structure through a layer transfer technology by direct wafer bonding and a GeOI thinning process by the combination of RIE and thermal oxidation, is proposed and demonstrated. The physical properties of the proposed GeOI are systematically evaluated with the thickness down to around 10nm. The proposed GeOI fabricated and thinned by the present method exhibits better crystal quality than the original one, with preserving the good GeOI thickness uniformity down to the UTB region. The electrical properties of the GeOI structures are also examined by using GeOI pMOSFETs, which are realized with the GeOI thickness down to 11nm. It is found that the hole mobility of the flipped GeOI is higher at a given GeOI thickness than that of the original GeOI.

Impact of back interface passivation on electrical properties of ultrathin-body Germanium-on-insulator (GeOI) MOSFETs

High mobility ultrathin-body GeOI MOSFETs with improved interfacial quality of the buried oxide interfaces are demonstrated in this study. We have realized these devices by flipping the Smart-Cut™ GeOI substrates with MOS interface passivation, directly bonding them to a Si substrate, removing the supporting Si substrate of the Smart-Cut™ GeOI and thinning the flipped GeOI films. The electrical properties of ultrathin-body GeOI MOSFETs with different Ge/BOX back interfaces and the GeOI thickness dependence have been evaluated in order to study the impact of the back interface passivation on the electrical properties. It is found that the hole mobility of the flipped GeOI is higher at a given GeOI thickness than that of the original GeOI thanks to the improvement of the back interfacial quality.

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

A method to remove the misfit dislocations and reduce the threading dislocations density (TDD) in the germanium (Ge) epilayer growth on a silicon (Si) substrate is presented. The Ge epitaxial film is grown directly on the Si (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) handle wafer to form a germanium-on-insulator (GOI) substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to &amp;lt;5 × 106 cm−2.

Fabrication and characterization of germanium-on-insulator through epitaxy, bonding, and layer transfer

A scalable method to fabricate germanium on insulator (GOI) substrate through epitaxy, bonding, and layer transfer is reported. The germanium (Ge) epitaxial film is grown directly on a silicon (Si) (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) wafer to form the GOI substrate. The Ge epilayer on GOI substrate has higher tensile strain (from 0.20% to 0.35%) and rougher surface (2.28 times rougher) compared to the Ge epilayer before transferring (i.e., Ge on Si wafer). This is because the misfit dislocations which are initially hidden along the Ge/Si interface are now flipped over and exposed on the top surface. These misfit dislocations can be removed by either chemical mechanical polishing or annealing. As a result, the Ge epilayer with low threading dislocations density level and surface roughness could be realized.

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

Germanium with higher electron and hole mobilities has been considered as a potential material for replacement of Si in CMOS transistors. However, due to the lower band gap of Ge compare to Si, bulk Ge devices suffer a high leakage current, which could be suppressed by employing a germanium on insulator (GeOI) substrate. High-κ-all-around asymmetrically-strained germanium nanowire trigate p-MOSFETs have exhibited the highest hole mobility recorded (1490 cm2/V.s) [1]. There are several approaches for the fabrication of GeOI substrates including separation-by-implanted-oxygen (SIMOX) [2], Ge condensation [3], liquid phase epitaxy [4], and wafer bonding [5]. Wafer bonding technique is advantageous among the other techniques due to its simplicity and potential for achieving high quality crystalline Ge layer.In this work we present a method to fabricate relaxed and strained GeOI substrates using heteroepitaxy and layer transfer techniques. The goal is to produce high quality wafer scale GeOI platform for relaxed and strained Ge nanowire CMOS fabrication. GeOI substrates are designed and fabricated via wafer bonding and etch back process without intermediary chemical mechanical polishing (CMP) step. Low temperature bonding avoids strain relaxation, Ge diffusion and detaching due to thermal expansion coefficient differences. In this design, GeOI structure is achieved by epitaxial growth and conventional dry and wet-etch techniques. All the epitaxial layers in the process are grown using RPCVD Epsilon 2000 ASM reactor. The fabrication process for both structures starts with the epitaxial growth of a roughly 1 µm Si0.96Ge0.04 etch stop layer. In the strained GeOI design the process is followed by epitaxial growth of an intermediate relaxed SiGe buffer with a Ge content of 40-50 percent, then a strained Si etch-stop layer and finally pseudomorphic growth of a thin strained Ge layer on top (Fig. 1). In relaxed GeOI structure on 1 µm Si0.96Ge0.04 etch stop layer a rather thick Ge layer (~300 nm) is grown in two steps, first a low temperature (LT) Ge is grown with high defect density and then a high temperature (HT) high quality Ge layer is grown on top (Fig. 2). Once the epitaxial growth of the structures is finished, 10 nm Al2O3 is deposited on top the Ge layer using atomic layer deposition (ALD). Then the wafers are brought together in the atmosphere pressure for room temperature bonding. The etch-back process begins by thinning down the donor wafer using Applied Materials Centura deep trench Si etch chamber (etch rate ~7 µm/min ). The etching process stops on the Si0.96Ge0.04 etch stop layer using endpoint detection system. At that point, the Si0.96Ge0.04etch-stop layer is selectively etched in TMAH solution. Then in relaxed GeOI structure the 300 nm Ge layer is oxidized and chemically thinned, up to the desired thickness (Fig. 2). In the strained GeOI structure SiGe relaxed buffer layer is selectively wet etched using dHF(100H2O:1HF):HNO3:CH3COOH (0.15:0.20:0.30) solution, and the strained Si layer is selectively removed in TMAH solution, leaving the strained Ge layer on Al2O3 (Fig. 1). Infrared (IR) image of the bonded wafers shows few voids at the interface and the bonding can withstand fast deep Si dry etching. X-ray analysis shows high quality well separated peaks for both structures and demonstrates the strain in top Ge layer (for the strained GeOI). The bonding strength will be measured using stress tester. The bonded interfaces will be observed by high resolution transmission electron microscopy (HRTEM). Topology of both Ge surfaces will be shown by atomic force microscopy (AFM).In summary, processes for the fabrication of high quality, low defect, monocrystalline, relaxed and strained germanium on insulator substrates are developed and optimized. This technique can serve as a platform for the fabrication of high performance Ge devices. AcknowledgmentThis work was supported by European Union ERC Advanced Grant 228229 OSIRIS.Fig. 1) schematic image of the bond and etch back process for strained GeOIFig. 2) schematic image of the bond and etch back process for relaxed GeOI[1] J. L. H. et al., IEEE, p. 4, 2012.[2] T. Mizuno, et al., IEEE Electron Device Lett., no. 5, pp. 230–232, May 2000.[3] T. Tezuka, et al., Appl. Phys. Lett., no. 12, p. 1798, 2001.[4] M. Miyao, et al., Appl. Phys. Express, p. 045503, Apr. 2009.[5] G. Taraschi, et al., Solid. State. Electron., no. 8, pp. 1297–1305, Aug. 2004.

(Invited) GOI Substrates: Fabrication and Characterization

Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized.

Fabrication of bonded GeOI substrates with thin Al2O3/SiO2 buried oxide layers

Fabrication of bonded Germanium on insulator (GeOI) substrates with thin Al2O3/SiO2 buried oxide layers was demonstrated for the first time. Thin Al2O3 layers grown by an atomic-layer deposition method, which have hydroxyl groups on their surfaces, were inserted to Ge/SiO2 interfaces to strengthen the adhesion between them. The interface bonded in the atmosphere at room temperature without post-anneal processes is flat and exhibits no additional interface. After the wafer bonding, thick GeOI layers were thinned by mechanical polishing, chemical mechanical polishing and O3 water etching. The flatness of the surface is equivalent to that of commercially available Ge substrates. The interface state density (Dit) of the Ge/Al2O3 interface is estimated with low-temperature conductance technique and the Dit of as low as 3.9×1011eV−1cm−2 at the interface is obtained. This value is almost one order of magnitude lower than previously reported Dit of Ge/SiO2 interfaces. These results suggest that negligible negative impact on carrier mobility and sub-threshold characteristics is expected for the back-side interface in the GeOI substrate with thin Al2O3/SiO2 BOX layers.

High-Performance Germanium $\Omega$ -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack

We report high-performance p-channel Ω-gate germanium (Ge) p-channel multigate field-effect transistor (MuGFET) with low-temperature Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> surface passivation and Schottky-barrier nickel germanide (NiGe) metallic source/drain, fabricated on high-quality germanium-on-insulator (GeOI) substrates using sub-400°C process modules. As compared with other reported p-channel multigate Ge devices formed by top-down approaches, the Ge MuGFETs in this letter have a record-high ON-state current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of ~450 μA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> = -1 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = - 1 V. High peak intrinsic saturation transconductance of ~740 μS/μm and low OFF-state current are reported. We also study the effect of fin or channel doping on Ge MuGFET performance. The simple MuGFET process developed using GeOI substrate would be a good reference for future 3-D Ge device fabrication.

Electrical Characterization of Wafer-Bonded Germanium-on-Insulator Substrates Using a Four-Point-Probe Pseudo-Metal–Oxide–Semiconductor Field-Effect Transistor

The electrical characteristics of wafer-bonded non-doped germanium-on-insulator (GOI) substrates were investigated using a four-point-probe pseudo-metal–oxide–semiconductor field-effect transistor. Annealing the wafer-bonded GOI substrates in vacuum strongly influenced their electrical characteristics. GOI samples annealed at temperatures below 500 °C exhibited n-channel depletion transistor operation, whereas GOI samples annealed at temperatures between 550 and 600 °C exhibited p-channel depletion transistor operation. The carrier mobility strongly depended on the sweep direction of the gate voltage; this characteristic disappeared after annealing at temperatures above 550 °C. The dependence of the electrical characteristics on the annealing temperature is explained in terms of the influence of the defect states on energy band bending near the interface.

Impacts of Thermal Annealing on Hydrogen-Implanted Germanium and Germanium-on-Insulator Substrates

Smart-cut and wafer bonding technology has been widely used in the germanium-on-insulator (GOI) fabrication. In this study, the damages formed in hydrogen implanted Ge, the surface blistering, and the GOI post-annealing processes were thoroughly investigated. The blistering of the hydrogen implanted Ge was carried out and compared with various thermal annealing temperatures ranging from 350 to 500°C. For the annealing temperature lower than 500°C, the Ge surface layer was found fully exfoliated with planar crack propagation. But at higher temperatures, discrete blisters were observed because of the very fast diffusion of the implanted hydrogen. Various post-annealing treatments, including annealing in vacuum or in N2 atmosphere were performed on the as-prepared GOI substrates. It was found that post-annealing in vacuum at 500°C improves the crystal quality of the GOI most effectively. As shown by X-ray diffraction (XRD) measurement, the full width at half maximum (FWHM) of the Ge peak was about 72.6 arc sec and almost all the residual stress was released.

Study of the surface cleaning of GOI and SGOI substrates for Ge epitaxial growth

An effective wet cleaning process, optimized for low temperature Ge epitaxial growth on thin Ge or SiGe structures with reduced surface roughening, is proposed. It is found that HF + HCl cleaning is the most effective wet cleaning method that is applicable to the low temperature thermal cleaning. It is also found that temperature of the thermal cleaning appropriate to 25–30 nm thick germanium on insulator (GOI) or silicon–germanium on insulator (SGOI) substrates is approximately 450 °C. Moreover, it is also found that the temperatures of Ge epitaxial growth even in lattice-matched systems must be reduced to around 400 °C to prevent surface roughening and those in lattice-mismatched systems also must be reduced sufficiently (300 °C for strained Ge growth on SGOI ( X eff = 0.6)) to prevent lattice relaxation as well as surface roughening. Finally, the successful formation of the compressively strained GOI structures is demonstrated by applying these wet cleaning and low temperature thermal cleaning processes and low temperature Ge epitaxy to thin SGOI substrates.