Geometric Arithmetic Parallel Processor Research Articles

Performance evaluation in image processing with GAPP array processor

The application of parallelism considering the field of image processing is an alternative to implement real time image processing. The data parallelism found in array processors simplify the mapping of this kind of problem as each processing element works on part of the image. The GAPP board (Geometric Arithmetic Parallel Processor) is a near-neighbor mesh architecture with 144 processors interconnected as a 12 × 12 bidimensional array. This work analyzes the performance of the GAPP board regarding image processing. The implementation of two image convolution algorithms and the analyses of the obtained results, as well as the utilization of the GAPP board in this kind of application and the performance achieved are discussed. The results found in this work are also compared to the results presented in [11]. Some ways to achieve a better performance of the GAPP array in this kind of application are also presented.

A fast algorithm for gaussian elimination over GF(2) and its implementation on the GAPP

A fast algorithm for Gaussian elimination over GF(2) is proposed. The proposed algorithm employs binary search technique to locate is along the columns of the large binary matrix being triangularized. The algorithm requires 2 m 2 + m log 2 n - 2 m bit operations to triangularize an n × m matrix on a bit-array with n processors and m + 2 + [log 2 n] bits of vertical memory per processor. Details of an implementation on the Geometric Arithmetic Parallel Processor are also presented.

A preliminary evaluation of a massively parallel processor: GAPP

The Geometric Arithmetic Parallel Processor (GAPP) is a systolic planar array processor with 72 (6 × 12) processing elements arranged in a mesh network. It runs at a clock speed of 10 MHz. The greatest advantage of such a design is that as many processor chips as are needed can be implemented without the loss of processing speed as interprocessor communication has been designed into the hardware architecture. It is therefore particularly suitable for processing of large image files with SIMD type of program execution. In this paper we report our study of the GAPP's performance in comparison with a number of other array processor systems, including: CLIP4, ICL DAP and Goodyear MPP. We also compare GAPP with some DSPs such as TMS32020, INMOS Transputer. We have found that GAPP's performance is in the same order of magnitude as these processors.

Detection of weak, subpixel targets using mesh-connected cellular automata

Effective use of military cellular automata such as military data array processor (MilDAP) and geometric arithmetic parallel processor (GAPP), in weak, subpixel target detection is shown to be possible by using new signal processing regimes based on binary ranking filter theory. By using binary ranking filters, the MilDAP can furnish 6 dB of processing gain against white Gaussian noise while monitoring from one to four million potential target tracks at 10-40 frames/s. GAPP is shown to be capable of monitoring 3.7 million tracks over 216*384 detectors at 14000 frames/s and, in a time sharing mode, 15 million tracks over 432*768 detectors at 24 frames/s. The special case of threatening targets is discussed, as well as alternate cellular architectures which use multidimensional binary ranking filters in multidimensional coordinate systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Neural Net Associative Memory for Real-Time Applications

A parallel hardware implementation of the associative memory neural network introduced by Hopfield is described. The design utilizes the Geometric Arithmetic Parallel Processor (GAPP), a commercially available single-chip VLSI general-purpose array processor consisting of 72 processing elements. The ability to cascade these chips allows large arrays of processors to be easily constructed and used to implement the Hopfield network. The memory requirements and processing times of such arrays are analyzed based on the number of nodes in the network and the number of exemplar patterns. Compared with other digital implementations, this design yields significant improvements in runtime performance and offers the capability of using large neural network associative memories in real-time applications.

Parallel rule-based fuzzy inference on mesh-connected systolic arrays

The authors describe a scheme for performing fuzzy-reasoning and fuzzy-inference operations in parallel on mesh-connected array processors such as the geometric arithmetic parallel processor (GAPP) and the advanced systolic array processor (ASAP). The reasoning mechanism is a general, fuzzy, rule-based inference network. The array is configured into stages, and the scheme operates in a pipeline configuration, where different sets of data move sequentially between the stages. The authors investigated the tradeoff between space and time complexity of the proposed technique and achieved a fast, space-efficient implementation of the approach. Before presenting the proposed system, they review briefly the concepts of inexact reasoning, fuzzy inference, and mesh-connected fine-grain parallel computer architecture.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SPL - A different high level language for systolic processors

The Systolic Processors Language, SPL, is a C-based high-level language for systolic processors. This language and its development environment, are designed especially, but not solely, for both the European Wafer Scale Integration Systolic Array Processor (ASAP: ESPRIT-824B), and the NCR Geometric Arithmetic Parallel Processor (GAPP). SPL enhances the software development capability for programmable systolic processors, and aims at simplifying program writing without decreasing the run-time performance. The contribution of SPL, presented in this paper, is the novel memory allocation for each Processing Element (PE), along with a balanced support of data—types, instruction—set, and a rich library of subroutines embedded in it. Altogether, these features provide an efficient back-end code.

Hough transform algorithms for mesh-connected SIMD parallel processors

Hough transform techniques for straight line detection play a key role in the road following algorithms developed by the University of Maryland for the DARPA Autonomous Land Vehicle Project. This report compares several methods of Hough transform computation suitable for implementation on a mesh-connected SIMD parallel processor, such as Goddard Space Flight Center's Massively Parallel Processor (MPP) or Martin Marietta Corp.'s Geometric Arithmetic Parallel Processor (GAPP).