Partial Product Generation Research Articles

Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier

This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone Adder (KSA), and the Carry Look-Ahead Adder (CLA), each of which presents unique advantages and trade-offs in terms of speed, area utilization, and power consumption. The results of our analysis demonstrate that the Kogge Stone Adder provides the best overall performance in terms of speed and area efficiency, making it the most suitable choice for optimizing Radix-8 Booth Multipliers, particularly in scenarios where high performance and efficient resource use are critical. By emphasizing these findings, this study contributes valuable insights into the design of more efficient multipliers that can meet the increasing demands of contemporary digital applications. Key Words: Radix-8 Booth Multiplier, approximate computing, delay optimization, area optimization, Carry Save Adder (CSA), Kogge Stone Adder (KSA), Carry Look-Ahead Adder (CLA), digital systems, arithmetic operations, performance enhancement, error-tolerant applications, partial product generation, hardware description languages (HDLs), digital signal processing, machine learning, approximation techniques, simulation and testing, power consumption, ASIC design.

An optimized design of delay-and energy-efficient Booth multiplier

Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. The design optimization focuses on all three multiplier stages: partial product generation, reduction, and summation. To enhance delay and energy efficiency in the partial product generation stage, we first employed a simplified configuration comprising inverters and a sign selection unit instead of complex binary-to-two's complement circuitry. Next, to achieve further delay and area efficiency at this stage, logic optimization is applied at the partial product's generation circuitry by designing Booth encoders to remove redundant logic in multiplexers circuitry. Moreover, we introduced specialized sign compressors tailored for carry-save compression in the compression stage. Compared to conventional counterparts, these compressors offered lower power consumption and reduced critical path delay with only two XOR logic gates. Finally, in the summation stage, we proposed an optimized design segment for Carry Look-Ahead Adder for the final summation stage, designed to deliver swift throughput with minimal fan-in logic gates, even in the context of high bit-width configurations. This segment is cascaded to make a 13-bit final adder for the summation stage in the proposed design. The proposed architecture undergoes ASIC-targeted synthesis in Cadence Genus employing FreePDK CMOS 45 nm process technology. Synthesized results, along with theoretical design complexity comparison, demonstrate that the proposed design surpasses state-of-the-art 8 × 8 multiplier designs by critical metrics, including delay, power consumption, area utilization, power delay product, and area delay product.

DESIGN AND IMPLEMENTATION OF RADIX-4-8 MODIFIED BOOTH’S ENCODER USING FPGA

We describe a unique design methodology of approximate radix-4 Booth multipliers that can be produced at a reasonable cost and that can greatly lower the power consumption of signal processing activities that are error-resilient. The suggested method takes into account two important processing steps simultaneously by requiring the generated error directions to be opposite to each other, in contrast to previous studies that only concentrate on the approximation of either the partial product generation with encoders or the partial product reductions with compressors. In comparison to the previous designs, the suggested approximation Booth multiplier can minimize the needed processing energy under the same number of approximate bits since the internal mistakes are naturally balanced to have zero mean. This suggested multiplier design was created in Verilog HDL, simulated using Xilinx and Modelsim 6.4c.

Digit-Serial DA-Based Fixed-Point RNNs: A Unified Approach for Enhancing Architectural Efficiency.

The next crucial step in artificial intelligence involves integrating neural network models into embedded and mobile systems. This requires designing compact and energy-efficient neural network models in silicon for optimized performance. This article introduces a unified approach for enhancing the architectural efficiency of long short-term memory (LSTM) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two's complement (TC) digit-serial distributed arithmetic (DSDA) technique are presented. The block-circulant matrix-vector multiplications (MVMs) and element-wise multiplications (EWMs) are formulated using TC DSDA. In addition, a fixed-point (FxP) training procedure for quantized LSTM RNNs is considered and validated for speech recognition tasks. Both structures leverage the circular rotation of weights and generate partial products with input digit slices. A new partial-product generator (PPG) and partial-product selector (PPS) designed to work with both unsigned and signed digits is introduced. In Structure I, a nonpipelined MVM is realized with a few PPGs and PPSs, followed by a shift-accumulate unit (SAU). Conversely, in Structure II, a suitably chosen depth-pipelined MVM is achieved with multiple PPGs and PPSs, followed by a shift-to-add tree (SAT). A critical path delay (CPD) analysis for both the proposed structures is also presented. Compared with previous works, post-synthesis results on 28 -nm fully depleted silicon-on-insulator (FDSOI) technology reveal that for a model size of 128 × 128 , Structures I and II provide 39.87% , 95.63% , and 30.95% , 91.18% more area and energy efficiencies, respectively.

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication

Inexact computing, is a modern approach for the development of low power and high-performance digital circuits, which involves approximation stages to get the utmost accurate result and are very much applicable in some error-tolerant applications like image processing. Such applications are limited to human eyesight ability, which gives us the freedom to make the approximate output. In this manuscript, two inexact partial product generators, viz. IPPG1, IPPG2 are proposed for the design of radix-4 based 8 × 8 Booth multipliers IRBM1.1, IRBM1.2, respectively. Moreover, an inexact 4:2 compressor is also proposed to add such partial product bits generated by IPPG1 and IPPG2, and nomenclate them as IRBM2.1 and IRBM 2.2, respectively. IPPG1 and IPPG2 are designed by introducing errors in the Karnaugh’s map to reduce the circuit complexity and errors, respectively. Similarly, errors are introduced in the truth table of the exact 4:2 compressor to design a low power, high speed inexact 4:2 compressor. Error metrics estimation of such proposed inexact Booth multipliers and the state-of-the-art designs are performed using MATLAB and circuit performance parameters like area, computational delay and power dissipation are extracted using gpdk45 nm technology. While comparing, IRBM1.2 offers minimum error metrics than all other reported design so far. Moreover, in the circuit level prospect, IRBM1.1 consumes minimum power and IRBM2.2 is the fastest among its reported counter-parts. IRBM2.2 offers minimum power-delay-area (PDA) product over all of its reported counter-parts. For the validation of the proposed designs, an image multiplication, edge-detection using Sobel operator, and convolutional neural network-based application is incorporated and quality assessment parameters are measured using MATLAB.

Design and realization of area-efficient approximate multiplier structures for image processing applications

The multiplier is a vital element in real-time applications. This work intends to build area-efficient multipliers based on the approximation concept. The approximate computing scheme receives considerable attention generally in error-resilient applications like image processing which reduce the design parameters at the expense of slightly sacrificing the precision of the performance. This paper proposes the two approximate multipliers (PAM-1 & PAM-2) using the modified 4:2 compressor, full-adder, and sum generation component. The main essence of the proposed approximate multiplier structures is to divide the partial product generation rows into (n/2) stages. The proposed approximate compressors are employed to compress partial products on the LSB side of the multiplier, while accurate compressors are utilized on the MSB side. By effectively combining approximate and exact compressors, the developed approximate multipliers achieve better results in terms of circuit parameters and acceptable error metrics compared to existing imprecise designs. These improvements are reflected in the implementation tables reported in the paper. Compared with the accurate multiplier, the proposed multiplier (PAM-2) reduce the area requirement, delay and power consumption by 38%, 46%, and 50%, respectively. In addition, while extending to image processing applications like multiplication, smoothing, and sharpening, the proposed approximate multipliers attain a better image quality than existing designs, which measure in terms of the mean structural similarity index metric.

Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing

Nowadays, quantum computing plays a significant role in reducing the execution time in complicated computations. There are different reversible algorithms for quantum computation and many quantum circuits theoretically designed until now. These designs are only built from reversible gates because reversibility is a necessary logic in quantum circuits. Additionally, ternary representation can allow designing a circuit with fewer inputs and outputs, leading to a considerable decline in size or number of qutrits. Although other papers in quantum ternary reversible logic are in unbalanced representation, this paper, for the first time, considers balanced ternary advantages to achieve a more efficient design for quantum multipliers as the main component in arithmetic blocks. Six criteria are introduced to show how balanced representation increases the overall performance. In this work, two general balanced ternary adder blocks (full-adder and half-adder) and two balanced ternary partial product generators (BTPPGs) are proposed, and also a 2 × 2 and a 3 × 3 balanced ternary multipliers built from these components. The quantum costs of proposed balanced ternary multipliers enhanced 17% for a 2 × 2 multiplier and 34% for a 3 × 3 multiplier.

Improved approximate multiplier architecture for image processing and neural network applications

This paper proposes new approximate unsigned multiplier architecture which aims to reduce the power consumption and area with better accuracy. In our proposed design, the approximation is applied in partial product generation (PPG) and partial product reduction (PPR) stages. In PPG, we proposed two approximate sub-multipliers to reduce the number of partial product rows. For the 8-bit multiplier design, experimental results show an improvement of 38.78% and 50.53% in power and power-delay-product respectively, when the proposed design is compared against the exact design, and 26.11% and 33.17% respectively when compared to existing Ax8-1 design, without compromising on the accuracy. Finally, proposed designs are validated using image processing and neural network applications.

Design and VLSI Implementation of Vedic Multiplier using 45nm Technology

Abstract: This paper proposes low-power multiplier architectures based on Vedic mathematics, which is a set of ancient Indian techniques for performing arithmetic operations. The proposed architectures use the Urdhva-Tiryagbhyam sutra from Vedic mathematics, which enables the efficient multiplication of numbers with fewer partial products. The proposed architectures have been implemented and simulated using the 45-nm CMOS technology. The simulation results demonstrate that the proposed architectures achieve significant power savings compared to conventional multipliers while maintaining reasonable area and delay. Therefore, the proposed architectures are suitable for use in low-power and high-performance applications. The Vedic multiplier consists of several sub-modules, each of which performs a specific function in the multiplication process. These submodules include the partial product generator, the multiplier, and the adder. The partial product generator generates partial products based on the input numbers and the Vedic sutras. The multiplier module then combines these partial products to create the final product. Finally, the adder module adds the product to the previous state of the circuit to generate the final result.

Towards Globally Optimal Design of Multipliers for FPGAs

The design of a multiplier typically consists of three steps: (1) partial product generation, (2) compressor tree design and (3) the selection of the final adder. Conventionally, these three steps are performed consecutively. However, when targeting FPGAs, there are many possibilities in all three design steps that heavily influence each other. This proposal presents for the first time a holistic optimization, combining all three optimization steps yielding a minimum amount of look-up-tables (LUTs) while it can also guarantee the minimal number of (pipeline) stages. An ILP-formulation for the determination of a combined, globally optimal solution for the multiplier tiling, compressor tree generation and final adder selection is proposed. With globally optimal we mean that the best solution is found for a given set of sub-multipliers for partial product generation, compressors and final adder.This allows to improve the quality and evaluate the limitations of existing heuristic 3-step approaches. It is shown experimentally for the example of Xilinx FPGAs, that globally optimal solutions can be obtained for multiplier sizes of practical relevance, leading to significant LUT reductions. Additional packing density experiments show that a significantly larger number of multiplier instances can be mapped to the same device.

Implementing and Analysing the Performance of Dadda Multiplier on FPGA

Abstract: Multiplication is an arithmetic operation where we will perform some arithmetic operations on the input operands and obtains the final result. Natural multiplication involves partial products generation and adding the obtained partial products to get the final result. But it consumes more power and time if the bit-width increases. Hence, we will use a Dadda Multiplier which results in increasing the execution speed and power efficiency and we will observe the same on FPGA. Hence this arithmetic technique can be used in various error tolerant applications such as image processing, digital processing and FFT.

Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier

In this brief, we present a novel design methodology of cost-effective approximate radix-4 Booth multipliers, which can significantly reduce the power consumption of error-resilient signal processing tasks. In contrast that the prior studies only focus on the approximation of either the partial product generation with encoders or the partial product reductions with compressors, the proposed method considers two major processing steps jointly by forcing the generated error directions to be opposite to each other. As the internal errors are naturally balanced to have zero mean, as a result, the proposed approximate Booth multiplier can minimize the required processing energy under the same number of approximate bits compared to the previous designs. Simulation results on FIR filtering and image classification applications reveal that the proposed approximate Booth multiplier shows the most attractive energy-performance trade-offs, achieving 28% and 34% of energy reduction compared to the exact Booth multiplier, respectively, with negligible accuracy loss.

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks

Approximate computing has emerged as a new paradigm that provides power-efficient and high-performance arithmetic designs by relaxing the stringent requirement of accuracy. Nonlinear functions (such as softmax, rectified linear unit (ReLU), Tanh, and Sigmoid) are extensively used in deep neural networks (DNNs). However, they incur significant power dissipation due to the high circuit complexity. As DNNs are error-tolerant, the design of approximation-linear functions is possible and desired. In this article, the design of an approximate softmax function (AxSF) is proposed. AxSF is based on a double hybrid structure (DHS). AxSF divides the input of the softmax function into two parts for different processing methods. The most significant bits (MSBs) are processed with lookup tables (LUTs) and an exact restoring array divider (EXDr). Taylor’s expansion and a logarithmic divider are used for the less significant bits (LSBs). An improved DHS (IDHS) is also proposed to reduce the hardware complexity. In IDHS, a novel Booth multiplier is utilized for the hybrid scheme to improve the partial product generation and compression, while the truncated implementation is applied to the divider unit. The proposed DHS and IDHS are compared with existing softmax designs. The results show that the proposed approximate softmax design reduces hardware by 48% and delay by 54% while retaining a high accuracy.

Editorial

Dear Readers, It gives me great pleasure to announce the eighth regular issue of 2022. In this issue, various topical aspects of computer science are covered by 18 authors from 5 countries in 5 articles. As always, I would like to thank all the authors for their sound research and the editorial board for their highly valuable review effort and suggestions for improvement. These contributions, together with the generous support of the consortium members, sustain the quality of our journal. In an ongoing effort to further strengthen our journal, I would like to expand the editorial board: If you are a tenured associate professor or above with a strong publication record, you are welcome to apply to join our editorial board. We are also interested in receiving high-quality proposals for special issues on new topics and trends. Please consider yourself and encourage your colleagues to submit high-quality articles or special issue proposals for our journal. In this regular issue, I am very pleased to introduce the following 5 accepted articles: Raoua Abdelkhalek, Imen Boukhris, and Zied Elouedi from Tunisia present their research on more trustworthy predictions based on the uncertain framework of belief function theory to support the representation, quantification and management of imperfect evidence. In a research collaboration between Jordan and the USA, Abd Al-Rahman Al-Nounou, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel present a methodology for designing binary multipliers, in which different sizes of customized partial products generation cells are designed and used as smaller building blocks. Venilton FalvoJr, Anderson da Silva Marcolino, Nemesio Freitas Duarte Filho, Edson OliveiraJr, and Ellen Francine Barbosa present the design, development and experimental evaluation of a software product line for mobile learning applications. Ghazala Hcini, Imen Jdey, and Hela Ltifi from Tunesia introduce their research on a new and robust deep learning model for automatically classifying malaria cells as infected or uninfected, built on a convolutional neural network. And last but not least, Sercan Yalçın, Musa Eşit, and Mehmet İshak Yüce from Turkiye discuss their approach to estimating climatological parameters based on artificial intelligence techniques with particle swarm optimization and deep neural networks.

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.

Design and Implementation of Low Power, High-Speed Configurable Approximation 8-Bit Booth Multiplier

Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.

Low power low area VLSI implementation of adaptive FIR filter using DA for decision feed back equalizer

In this paper, a low-complexity pipelined adaptive FIR filter is designed using Distributed Arithmetic (DA) architecture for signal processing applications. Generally adaptive filters will occupy more area and power consumption because of using memories in the filters for partial product (PP) generation. To get rid of this, We use the pipeline concept to reduce the registers in the filters and also to reduce the area further compressor adders are used in the adaptive filter architectures instead of using normal adders. With these two concepts the area and power consumption of the adaptive filters will be reduced. The proposed design is coded in Verilog HDL language and synthesized in Synapsis design compiler tool with SAED 90 nm technology for finding the area, power, minimum sampling period, maximum sampling frequency, area delay product (ADP), power delay product (PDP). By using proposed adaptive filter we can design and implement higher order filters more easily and also the complexity of the proposed design is very less when compared with the existing designs. When we observe the synthesis results the proposed design will occupy 30% less area when compared with the two memories based existing architecture. Also the power consumption is 25% less when compared with the block based adaptive filters. The ADP and PDP of the proposed design is very less when compared with existing architectures. The proposed design is well suited for signal processing application designs such as adaptive decision feed back equalizers for removing the signal noises and inter symbol interference, hearing aids, ECG signal analysis and software defined radio.

Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications

Approximate computing at the nanoscale provides sufficiently accurate and often adaptive results to improve hardware efficiency for error-tolerant applications. Differently from conventional Boolean logic-based designs, many emerging nanotechnologies extensively assemble circuits using the voter-based majority logic (ML). In this letter, we investigate designs of approximate radix-4 Booth multipliers based on ML. Initially, we propose two new radix-4 Booth partial product (PP) generation methods by exploiting the characteristics of ML. Based on these methods, approximate PP generators are designed to produce single-sided or double-sided errors. The PPs are then reduced by using the features of errors to construct approximate multipliers. Specifically, complementary strategies guided by an analysis of error effects are developed to compensate for the accuracy loss and to reduce the hardware overhead during the PP reduction. The reduced PPs are then compressed by using full adders. Four approximate multipliers are proposed to offer various accuracy requirements for different applications. These designs show superior performance in power and area for emerging nanotechnologies. As case studies, image processing, a multiple-layer perceptron and a multi-task convolutional neural network are presented to show the validity and advantages of the proposed designs.