Generation Nanoelectronic Devices Research Articles

English

emiconductor nanostructures such as quantum wells, quantum wires or quantum dots exhibit superior properties in comparison to their bulk forms. Quantum dots are described aszero-dimensional electron gas system, as carriers are confined in all the three directions. Densityof states is discrete function of energy. Allowed energy spectrum is discrete like in an atom.Energy band gap is broadened due to carriers confinement. Semiconductor quantum dots exhibittypical coulomb blockade characteristic which is exploited for development of new generationof nanoelectronic devices namely single-electron transistor, memories, etc, whose operationdepends on quantum mechanical tunneling of carriers through energy barriers. Thesesemiconductor nanostructures emit light in visible range upon excitation by optical means. Inrecent years, research has been focused on different nano-scale materials; metals (Au, Ag, Fe,Mn, Ni), metal oxides (SnO2, ZnO2), compound semiconductors (GaAs, GaAlAs, CdSe, CdS,GaN), and elemental semiconductors (silicon and germanium). As silicon is the most favouredmaterial in the established integrated circuits manufacturing technology, research is being donefor controlled synthesis and characterisation of Si nanoparticles. The Si nanoparticles havebeen synthesised on oxide and nitride layers over Si substrate by IC technology compatiblelow-pressure chemical vapour deposition technique. Atomic force microscopy (AFM)characterisation has been extensively carried out on the samples. It is shown that the tip radiusand shape of tip lead to less accurate estimate of the actual size. The AFM images have been evaluated based on the real surface topography and shape of the tip. Photolumine scence (PL) studies have been performed to characterise the samples. The PL measurements showed visiblelight emission from synthesised silicon nanoparticles.Defence Science Journal, 2008, 58(4), pp.550-558, DOI:http://dx.doi.org/10.14429/dsj.58.1676

Large‐scale “atomistic” approach to discrete‐dopant‐induced characteristic fluctuations in silicon nanowire transistors

AbstractNanowire fin‐typed field effect transistors (FinFETs) are ultimate structures and potential candidates for next generation nanoelectronic devices. Due to the limitation of manufacturability, nanowire transistors with a perfect gate structure (i.e., a surrounding gate with 100% gate‐coverage ratio) theoretically are not always guaranteed. Impact of the discrete dopants on device performance is crucial in determining the behaviour of nanoscale semiconductor devices. The immunity of nanowire transistor against random discrete‐dopant‐induced fluctuation may suffer from the variation of gate‐coverage‐ratio. Therefore, in this paper, we for the fist time study the impact of non‐ideal gate coverage on immunity against random‐dopant‐induced fluctuations for nanowire FinFETs. A 3D statistically sound “atomistic” approach for analyzing random‐dopant effect in nanodevice is presented. Discrete dopants are statistically positioned into the channel region to examine associated carrier transportation characteristics, concurrently capturing “dopant concentration variation” and “dopant position fluctuation”. Our results confirm that the influence of non‐ideal gate coverage disturbs the channel controllability of nanowire FinFETs and thus decreases the immunity against discrete‐dopant‐induced fluctuation. This study provides an insight into the problem of fluctuation in nanowire transistors and shows the importance of gate‐coverage ratio on device's immunity against discrete‐dopant‐induced fluctuation. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Large-scale growth of single-walled carbon nanotubes using cold-wall chemical vapor deposition

Carbon nanotubes have been considered as an alternative material for next generation nanoelectronic devices, such as the carbon nanotube field-effect transistor (CNT-FET) or nanosensor. Large-scale growth of single-walled carbon nanotubes (SWNTs) is particularly essential to the fabrication of the CNT-FET on a full wafer. In this study, SWNTs grown at designated positions on broken pieces in a conventional thermal furnace chemical vapor deposition (CVD) system and on a 4-in. full size silicon wafer in a cold-wall thermal CVD were compared. The distinct characteristics of SWNTs grown by the two systems are explained by the differences in the temperature distribution and the gas flow pattern, and their interplay with the catalysis and the feedstock gas decomposition. The adoption of cold-wall CVD process provides a simple method, but an essential step, toward commercial applications of SWNT-based devices.

Ferroelectrics onto silicon prepared by chemical solution deposition methods: from the thin film to the self-assembled systems

The work of the authors during the last years on ferroelectric thin and ultra-thin films deposited by Chemical Solution Deposition (CSD) onto silicon based substrates is reviewed in this paper. Ferroelectric layers integrated with silicon substrates have potential use in the new micro/nanoelectronic devices. Two hot issues are here considered: 1) the use of low processing temperatures of the ferroelectric film, with the objective of not producing any damage on the different elements of the device heterostructure, and 2) the downscaling of the ferroelectric material with the aim of achieving the high densities of integration required in the next generation of nanoelectronic devices. The UV-assisted Rapid Thermal Processing has successfully been used in our laboratory for the fabrication of ferroelectric films at low temperatures. Preliminary results on the CSD preparation of nanosized ferroelectric structures are shown.

Semiconductor Research Needs in the Nanoscale Physical Sciences: A Semiconductor Research Corporation Working Paper

The purpose of this paper is to identify areas in the basic physical sciences where additional research is needed to sustain the extraordinary progress in electronics that has now extended for several decades. Also, it is argued that basic research will provide the foundation for the discovery of new generations of nanoelectronic devices that will continue the experimental rate of reduction in cost per function. Some of the fundamental areas requiring further research are the chemistry and physics of material interfaces, conductivity at small dimensions, deterministic doping effects, and nanomagnetics. Discovery research also is needed in the functional synergy of nanoelectronic materials and non-traditional fabrication methods.