General Purpose Digital Signal Processor Research Articles

Improving Structured Grid-Based Sparse Matrix-Vector Multiplication and Gauss–Seidel Iteration on GPDSP

Structured grid-based sparse matrix-vector multiplication and Gauss–Seidel iterations are very important kernel functions in scientific and engineering computations, both of which are memory intensive and bandwidth-limited. GPDSP is a general purpose digital signal processor, which is a very significant embedded processor that has been introduced into high-performance computing. In this paper, we designed various optimization methods, which included a blocking method to improve data locality and increase memory access efficiency, a multicolor reordering method to develop Gauss–Seidel fine-grained parallelism, a data partitioning method designed for GPDSP memory structures, and a double buffering method to overlap computation and access memory on structured grid-based SpMV and Gauss–Seidel iterations for GPDSP. At last, we combined the above optimization methods to design a multicore vectorization algorithm. We tested the matrices generated with structured grids of different sizes on the GPDSP platform and obtained speedups of up to 41× and 47× compared to the unoptimized SpMV and Gauss–Seidel iterations, with maximum bandwidth efficiencies of 72% and 81%, respectively. The experiment results show that our algorithms could fully utilize the external memory bandwidth. We also implemented the commonly used mixed precision algorithm on the GPDSP and obtained speedups of 1.60× and 1.45× for the SpMV and Gauss–Seidel iterations, respectively.

Computationally efficient low-power sigma delta modulation-based image processing algorithm

Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multi-bit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment.

A Low-Cost, High-Performance Digital Signal Processor (DSP) for Audio Applications

Digital audio signal processing has become increasingly common in multimedia systems as a result of the development of general-purpose digital signal processors (DSP processors) and high-precision oversampling analog-to-digital (A/D) converters. Nevertheless, the solution based on standard DSP chips could be too expensive and power-hungry for portable and home entertainment audio systems. As a result, it is necessary to locate an alternative solution that is both low-cost and low-power. In the context of digital audio applications, this paper will describe how a DSP (Digital Signal Processor) is created, as well as how its architecture functions. The proposed digital signal processor (DSP) has six stages of pipeline with a fixed 24-bit data format, and each stage has 125 instructions. The instructions for the audio signal processing are provided in a very specific manner. Each and every command is handled within the confines of a single cycle.

How to Transfer Strided Data into Accelerator

Data transfer from a host central processing unit (CPU) into an accelerator is a performance bottleneck for applications accelerated by accelerators (such as general purpose digital signal processing (GPDSP), many integrated core (MIC), and general purpose graphics processing unit (GPGPU)). It is complicated and inefficient to transfer non-contiguous data with special respect to strided data. In this work, we present three approaches to transfer strided data for different scenarios: Redundant copy (RC), selective copy (SC), and transfer after transformed (TaT). We propose a space and time efficient method named TaT, in which strided data are transformed on the CPU first and then transferred into the accelerator. We simulated regions-of-interest (ROI) coding and validate proposed techniques. TaT was superior to RC on space efficiency and close to SC on saving space, but better than SC on time waste respectively.

A Novel DSP Architecture for Scientific Computing and Deep Learning

Exascale computing requires accelerators with ultrahigh power efficiency. Digital signal processors (DSPs), the most important embedded processors widely known for high power efficiency, are rarely explored in the HPC community. We propose a 64-bit general purpose DSP architecture, FT-Matrix2000, which not only integrates the main features of DSPs but also presents several novel enhancements for scientific computing. The FT-Matrix2000 architecture comprises multiple FT-Matrix2 cores and optional RISC CPU cores. The FT-Matrix2 core utilizes a VLIW+SIMD architecture, provides support for double precision operations, and optimizes both the data and control path for scientific computing. Our evaluations show that the performance and efficiency of FT-Matrix2000 are 1107GFLOPS and 92.25%. Compared with the MIC and a 40nm process GPU, FT-Matrix2000 improves the GEMM power efficiency with a factor of 1.49 and 2.68, respectively. We build up a prototype supercomputer with FT-Matrix2000/12. Its HPL efficiency achieves 62.2%, and the performance power ratio is 5.33 GFLOPS/W, which can rank the fourth in the latest Green500 list. These results validate that the FT-Matrix2000 architecture is suitable for scientific computing while maintaining the efficiency of signal processing well. Moreover, the enhancement of FT-Matrix2000 in vector and matrix related computations also enable it to efficiently support deep learning related applications. We have implemented some typical DCNN models on FT-Matrx2000, NVIDIA GPUs, and Vision P6 DSP. The experiments demonstrate that the average computation efficiency of the proposed architecture based on Matrix2000 is about 20 ~ 35% and 8% higher respectively than GPUs and Cadence Vision P6 DSP.

PWM and PFM Hybrid Control Method for LLC Resonant Converters in High Switching Frequency Operation

High switching frequency is an effective method to improve power density for LLC resonant converters. However, conventional digital controllers, such as general-purpose digital signal processors and microprocessors, have limited frequency resolution, which induces high primary- and secondary-side current variation and leads to poor output voltage regulation. In this paper, a hybrid control method combining pulse frequency modulation (PFM) and pulse width modulation is proposed to overcome the limited frequency resolution issue. The proposed hybrid control method focuses on steady-state operation, and its operating principles are introduced and analyzed. In addition, the proper magnetizing inductance and dead time duration are derived to ensure that the power mosfet s achieve zero voltage switching with the proposed control method. The improved voltage regulation performance is compared with the conventional PFM control and verified through simulation and experimental results using a 240 W prototype converter operating at a switching frequency of 1 MHz.

Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

An Implementation of Real-Time Phased Array Radar Fundamental Functions on a DSP-Focused, High-Performance, Embedded Computing Platform

This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of general purpose digital signal processors. First, we obtained the lab-scale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on a Micro Telecom Computing Architecture (MTCA) chassis using the Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebones design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including the Open Computing Language.

TECHNOLOGY DESIGN OF HIGH SPEED FIR FILTER ON FPGA BY USING MULTIPLEXER ARRAY OPTIMIZATION IN DA-OBC ALGORITHM

The main objective of the project is to implement FIR filter on FPGA using Distributed Arithmetic-Offset Binary Coding (DA-OBC) reduction technique. Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and applicationspecific integrated circuits (ASICs) for higher rates. This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs). Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the digital FIR filter. Based on the design specification, careful choice of implementation method and tools can save a lot of time and work. Mat Lab is an excellent tool to design filters. There are toolboxes available to generate VHDL descriptions of the filters which reduce dramatically the time required to generate a solution. Time can be spent evaluating different implementation alternatives. Computation algorithms are required that exploit the FPGA architecture to make it efficient in terms of speed and/or area. By using this algorithm, memory size can be reduced and also the speed of the operation can be increased. The FIR filter can be simulated on FPGA device by VHDL language in MODEL SIM and simulation on MATLAB is in this project.

A novel real-time resource efficient implementation of Sobel operator-based edge detection on FPGA

A new resource efficient FPGA-based hardware architecture for real-time edge detection using Sobel operator for video surveillance applications has been proposed. The choice of Sobel operator is due to its property to counteract the noise sensitivity of the simple gradient operator. FPGA is chosen for this implementation due to its flexibility to provide the possibility to perform algorithmic changes in later stage of the system development and its capability to provide real-time performance, hard to achieve with general purpose processor or digital signal processor, while limiting the extensive design work, time and cost required for application specific integrated circuit. The proposed architecture uses single processing element for both horizontal and vertical gradient computation for Sobel operator and utilised approximately 38% less FPGA resources as compared to standard Sobel edge detection architecture while maintaining real-time frame rates for high definition videos (1920 × 1080 image sizes). The complete system is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board.

Cluster based MPSoC architecture: an on-chip message passing implementation

This paper proposes a hardware memory management unit to implement an on-chip message passing protocol for cluster based multi-processors system on chip architectures. Within the architecture each cluster is composed of general purpose processors or digital signal processors, along with a memory. To maintain the coherence of the memory a hardware memory management unit is added in the cluster to increase the performance and support an on-chip message passing communication. The hardware memory management unit has the capacity to allocate, control and limit the access to the memory. In order to show the benefit of our architecture a performance comparison over a classical flat architecture and against a state of the art architecture is driven. The results show an improvement that ranges from 1.2 to 21.77 % over these two architectural models. Finally the hardware cost overhead is studied.

The impact of alternative encoding techniques on field programmable gate array implementation of sigma-delta modulated ternary finite impulse response filters

This paper presents the design and synthesis of a single-bit ternary finite impulse response filter with balanced ternary coefficients (ie. -1, 0, +1) implemented in VHDL on small commercial field programmable gate arrays (FPGAs). A comparison is made between implementations based on 2s complement, redundant binary signed digit (RBSD) and canonical signed digit (CSD) encoding techniques. Through simulation, the area and performance of an example filter are analysed using pipelined and non-pipelined modes for all three techniques. The simulation results show that, unlike in the equivalent multi-bit filters, CSD offers no advantages in single-bit sigma-delta modulated (ΔSigmaM) systems. Similarly, RBSD occupies twice the area and exhibits much poorer performance compared to a conventional 2s complement representation due to the small symbol size in single-bit systems. These results demonstrate that simple, short word length ΔSigmaM filters will be useful in greatly reducing the number of general-purpose digital multipliers in general purpose digital signal processor applications using FPGA and especially ASIC.

The Impact of Alternative Encoding Techniques on Field Programmable Gate Array Implementation of Sigma-Delta Modulated Ternary Finite Impulse Response Filters

This paper presents the design and synthesis of a single-bit ternary finite impulse response filter with balanced ternary coefficients (ie. -1, 0, +1) implemented in VHDL on small commercial field programmable gate arrays (FPGAs). A comparison is made between implementations based on 2s complement, redundant binary signed digit (RBSD) and canonical signed digit (CSD) encoding techniques. Through simulation, the area and performance of an example filter are analysed using pipelined and non-pipelined modes for all three techniques. The simulation results show that, unlike in the equivalent multi-bit filters, CSD offers no advantages in single-bit sigma-delta modulated (∑ΔM) systems. Similarly, RBSD occupies twice the area and exhibits much poorer performance compared to a conventional 2s complement representation due to the small symbol size in single-bit systems. These results demonstrate that simple, short word length ∑ΔM filters will be useful in greatly reducing the number of general-purpose digital multipliers in general purpose digital signal processor applications using FPGA and especially ASIC.

Performance evaluation of platform-specific implementations of numerically complex control designs for nano-positioning applications

Developing machines capable of positioning and measuring in nano-metre dimensions is an overall challenging endeavour, which not at least includes providing a highly dynamic and precise trajectory tracking control system. To effectively employ such a control system an adequately performing implementation on an embedded real-time processing system is essential for process performance and quality. In this article an implementation study of a Kalman filter component is presented, comparing the solutions for general purpose processor and digital signal processor to a range of designs for field-programmble gate arrays. Evaluating the performance of the respective implementations for a PXI platform and thus indicating the feasibility of industrial and standard-compliant application is the emphasis of this contribution.

A Parameterized Programmable MIMO Decoding Architecture With a Scalable Instruction Set and Compiler

We present a novel multiple-input multiple-output (MIMO) decoder accelerator and its associated integrated design environment. The accelerator architecture allows tradeoffs in decoding algorithm, antenna configuration, modulation scheme, and bandwidth at run-time via user programming. The accelerator delivers an improvement over a general purpose digital signal processor (DSP) reaching three orders of magnitude for matrix processing and linear MIMO decoding. The hardware architecture is user-configurable through ten independently set parameters. The parameterization allows independent control over the size and structure of the processing core as well as the structure, size, and access scheme of data memory. We provide a custom high level script and a scalable machine level instruction set and compiler. The elements of hardware configuration and programmability are combined in a user-friendly design flow that takes the MIMO decoder designer from simulation to hardware with dedicated-hardware-like performance in no time.

周波数領域目的音抽出システムの試作と実環境性能評価

In this paper, we present a real-time implementation of target sound extraction operating in a frequency domain using a microphone array, and describe its performance evaluation in actual room environments. In the realized system, the target sound extraction can be achieved by using the FDGSC (Frequency Domain Generalized Sidelobe Canceler) which is one of GSCS. In each frequency band, the FDGSC is composed of a fixed beamformer part for target sound enhancement and an adaptive filter part for noisy sound reduction. Since the FDGSC is required to apply the DFT (Discrete Fourier Transform) in every sound data block, the processing for a series of block data must be completed within the transfer time of block data in the real-time system. Thus, we implemented the FDGSC using a general-purpose DSP (Digital Signal Processor) evaluation board which enabled us to perform high-speed signal processing. Superior performance of real-time processing and target sound extraction are shown by several experimental results in real room environments. © 2011 Wiley Periodicals, Inc. Electron Comm Jpn, 94(7): 9–16, 2011; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10334

Optical Doppler tomography based on a field programmable gate array

We report the design of and results obtained by using a field programmable gate array (FPGA) to digitally process optical Doppler tomography signals. The processor fits into the analog signal path in an existing optical coherence tomography setup. We demonstrate both Doppler frequency and envelope extraction using the Hilbert transform, all in a single FPGA. An FPGA implementation has certain advantages over general purpose digital signal processor (DSP) due to the fact that the processing elements operate in parallel as opposed to the DSP, which is primarily a sequential processor.

Polyphase Boost Converter with Digital Control

Boost d.c.-d.c. converters have very good source interface properties. The input inductor makes the source current smooth and hence these converters provide very good EMI performance. On account of this good property, the boost converter is also the preferred converter for off-line UPF rectifiers. One of the issues of concern in these converters is the large size of the storage capacitor on the dc link. The boost converter suffers from the disadvantage of discontinuous current injected to the load. The size of the capacitor is large. Further, the ripple current in the capacitor is as much as the load current; hence the ESR specification of the tank capacitor is demanding. This paper presents the polyphase boost converter, which overcomes the problem of high ripple current in the tank capacitor, which has not been discussed earlier. Comparison between the specifications of single stage and multistage is thoroughly examined. Digital control is more convenient for such a topology on account of the requirement of synchronization, phase shifted operation and current balancing. The control method is simpler and faster than its original form [10]. It does not depend on the previous duty ratio and it has been tested on four boost converters in parallel. Each is a 35W unit switched at 200 kHz. Experimental results in digital control, synchronization operation and current sharing are presented. The control method is implemented using a TI’s general purpose Digital Signal Processor eZdspF2812. This control scheme is applicable for PFC rectifiers as well.

A Biosignal-Based Human Interface Controlling a Power-Wheelchair for People with Motor Disabilities

An alternative human interface enabling people with severe motor disabilities to control an assistive system is presented. Since this interface relies on the biosignals originating from the contraction of muscles on the face during particular movements, even individuals with a paralyzed limb can use it with ease. For real-world application, a dedicated hardware module employing a general-purpose digital signal processor was implemented and its validity tested on an electrically powered wheelchair. Furthermore, an additional attempt to reduce error rates to a minimum for stable operation was also made based on the entropy information inherent in the signals during the classification phase. In the experiments, most of the five participating subjects could control the target system at their own will, and thus it is found that the proposed interface can be considered a potential alternative for the interaction of the severely disabled with electronic systems. disabled lead a more improved life have been addressed, and corresponding effort has also been made in the fields related to rehabilitation engineering and user interface (UI) development. One attempt attracting considerable attention in those fields involves the utilization of biosignals such as an electroencephalogram (EEG) or electromyogram (EMG) obtainable from the human body as a means for interaction with the surrounding world. In the field of brain-computer interface (BCI), meaningful information derived directly from a user's brain activity has been used to manipulate systems. However, despite the definite advantage unique to EEG signals that allows a system to be controlled only by one's thoughts, the poor signal-to-noise ratios in the spontaneous EEG signals and the lack of consistency in the signal patterns still make their application impractical. Compared to such drawbacks of EEG signals, EMG signals have more possibility to be applied to a wide range of users due to their easy controllability and insensitiveness to noises (1). In this letter, a special interface based on these EMG signals that runs in a stand-alone mode is proposed, and its usefulness as a communication channel is investigated through a practical test on an electrically powered wheelchair, called a power-wheelchair throughout this letter.

프랙탈 알고리즘 기반의 실시간 영상 부호화기의 설계 및 구현

이 논문에서는 범용 DSP칩인 ADSP2181를 사용하여 프랙탈 알고리즘 기반의 영상 부호화기를 설계 제작하였다. 제작된 부호화기는 고정소수점을 지원하는 Analog Device사의 ADSP2181 두 개를 사용하여 구현되었고, 영상부호화는 3단계의 파이프라인 구조에 의해 이루어진다. 첫 번째 파이프라인단인 영상 획득부는 NTSC표준 영상 신호로부터 디지털 영상 데이터를 획득하여 프레임 메모리에 저장한다. 두 번째 단에서의 주제어부에서는 영상 데이터를 프랙탈 알고리즘을 이용하여 부호화를 수행한다. 마지막 단인 출력 제어부는 부호화된 영상 계수를 RS422 포트를 통하여 출력하도록 한다. 설계 제작된 프랙탈 영상 부호화기의 성능은 QCIF 영상 포맷에서 정지영상에 대하여 초당 10프레임 이상의 부호화 속도를 얻었다. 프랙탈 알고리즘을 이용하여 프레임간 중복성을 이용한 영상 부호화시에는 초당 평균 30 프레임 이상의 부호화속도를 얻을 수 있었다. In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.